From 7944e854dda297193328e00b4f9b08ce4d843915 Mon Sep 17 00:00:00 2001 From: Tyler Gilbert Date: Wed, 3 Jan 2024 11:07:57 -0600 Subject: [PATCH] Fix formatting of comments --- embassy-stm32/src/rcc/u5.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs index ceed46176..dff08dc9b 100644 --- a/embassy-stm32/src/rcc/u5.rs +++ b/embassy-stm32/src/rcc/u5.rs @@ -45,13 +45,13 @@ pub struct PllConfig { /// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544 /// MHz. The upper limit may be lower depending on the `Config { voltage_range }`. pub n: Plln, - /// The divider for the P output. - /// + /// The divider for the P output. + /// /// The P output is one of several options /// that can be used to feed the SAI/MDF/ADF Clock mux's. pub p: Plldiv, - /// The divider for the Q output. - /// + /// The divider for the Q output. + /// /// The Q ouput is one of severals options that can be used to feed the 48MHz clocks /// and the OCTOSPI clock. It may also be used on the MDF/ADF clock mux's. pub q: Plldiv,