Handle Uarte RX errors
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dcce40c8a2
commit
7ff21e8b8b
2 changed files with 85 additions and 11 deletions
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@ -133,6 +133,7 @@ embedded-io = { version = "0.6.0" }
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embedded-io-async = { version = "0.6.1" }
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defmt = { version = "0.3", optional = true }
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bitflags = "2.4.2"
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log = { version = "0.4.14", optional = true }
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cortex-m-rt = ">=0.6.15,<0.8"
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cortex-m = "0.7.6"
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@ -52,6 +52,39 @@ impl Default for Config {
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}
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}
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bitflags::bitflags! {
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/// Error source flags
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pub struct ErrorSource: u32 {
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/// Buffer overrun
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const OVERRUN = 0x01;
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/// Parity error
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const PARITY = 0x02;
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/// Framing error
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const FRAMING = 0x04;
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/// Break condition
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const BREAK = 0x08;
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}
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}
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impl TryFrom<ErrorSource> for () {
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type Error = Error;
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#[inline]
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fn try_from(errors: ErrorSource) -> Result<Self, Self::Error> {
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if errors.contains(ErrorSource::OVERRUN) {
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Err(Error::Overrun)
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} else if errors.contains(ErrorSource::PARITY) {
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Err(Error::Parity)
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} else if errors.contains(ErrorSource::FRAMING) {
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Err(Error::Framing)
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} else if errors.contains(ErrorSource::BREAK) {
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Err(Error::Break)
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} else {
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Ok(())
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}
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}
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}
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/// UART error.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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@ -61,6 +94,14 @@ pub enum Error {
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BufferTooLong,
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/// The buffer is not in data RAM. It's most likely in flash, and nRF's DMA cannot access flash.
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BufferNotInRAM,
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/// Framing Error
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Framing,
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/// Parity Error
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Parity,
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/// Buffer Overrun
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Overrun,
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/// Break condition
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Break,
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}
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/// Interrupt handler.
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@ -73,9 +114,16 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
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let r = T::regs();
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let s = T::state();
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if r.events_endrx.read().bits() != 0 {
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let endrx = r.events_endrx.read().bits();
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let error = r.events_error.read().bits();
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if endrx != 0 || error != 0 {
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s.endrx_waker.wake();
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r.intenclr.write(|w| w.endrx().clear());
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if endrx != 0 {
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r.intenclr.write(|w| w.endrx().clear());
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}
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if error != 0 {
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r.intenclr.write(|w| w.error().clear());
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}
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}
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if r.events_endtx.read().bits() != 0 {
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s.endtx_waker.wake();
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@ -486,6 +534,13 @@ impl<'d, T: Instance> UarteRx<'d, T> {
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Self::new_inner(uarte, rxd.map_into(), Some(rts.map_into()), config)
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}
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fn read_and_clear_errors(&mut self) -> Result<(), Error> {
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let r = T::regs();
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let err_bits = r.errorsrc.read().bits();
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r.errorsrc.write(|w| unsafe { w.bits(err_bits) });
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ErrorSource::from_bits_truncate(err_bits).try_into()
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}
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fn new_inner(
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uarte: impl Peripheral<P = T> + 'd,
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rxd: PeripheralRef<'d, AnyPin>,
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@ -572,7 +627,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
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/// Read bytes until the buffer is filled.
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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if buffer.len() == 0 {
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if buffer.is_empty() {
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return Ok(());
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}
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if buffer.len() > EASY_DMA_SIZE {
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@ -588,8 +643,13 @@ impl<'d, T: Instance> UarteRx<'d, T> {
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let drop = OnDrop::new(move || {
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trace!("read drop: stopping");
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r.intenclr.write(|w| w.endrx().clear());
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r.intenclr.write(|w| {
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w.endrx().clear();
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w.error().clear()
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});
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r.events_rxto.reset();
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r.events_error.reset();
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r.errorsrc.reset();
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r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
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while r.events_endrx.read().bits() == 0 {}
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@ -601,17 +661,26 @@ impl<'d, T: Instance> UarteRx<'d, T> {
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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r.events_endrx.reset();
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r.intenset.write(|w| w.endrx().set());
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r.events_error.reset();
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r.intenset.write(|w| {
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w.endrx().set();
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w.error().set()
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});
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compiler_fence(Ordering::SeqCst);
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trace!("startrx");
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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poll_fn(|cx| {
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let result = poll_fn(|cx| {
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s.endrx_waker.register(cx.waker());
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let maybe_err = self.read_and_clear_errors();
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if let Err(e) = maybe_err {
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return Poll::Ready(Err(e));
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}
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if r.events_endrx.read().bits() != 0 {
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return Poll::Ready(());
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return Poll::Ready(Ok(()));
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}
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Poll::Pending
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})
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@ -621,7 +690,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
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r.events_rxstarted.reset();
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drop.defuse();
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Ok(())
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result
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}
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/// Read bytes until the buffer is filled.
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@ -642,19 +711,23 @@ impl<'d, T: Instance> UarteRx<'d, T> {
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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r.events_endrx.reset();
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r.intenclr.write(|w| w.endrx().clear());
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r.events_error.reset();
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r.intenclr.write(|w| {
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w.endrx().clear();
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w.error().clear()
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});
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compiler_fence(Ordering::SeqCst);
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trace!("startrx");
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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while r.events_endrx.read().bits() == 0 {}
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while r.events_endrx.read().bits() == 0 && r.events_error.read().bits() == 0 {}
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compiler_fence(Ordering::SeqCst);
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r.events_rxstarted.reset();
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Ok(())
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self.read_and_clear_errors()
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}
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}
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