update DAC triggers to incorporate v3

embassy-stm32/Cargo.toml

@@ -57,7 +57,7 @@ sdio-host = "0.5.0"
 embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
 critical-section = "1.1"
 atomic-polyfill = "1.0.1"
-stm32-metapac = "12"
+stm32-metapac = "13"
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
@@ -74,7 +74,7 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-stm32-metapac = { version = "12", default-features = false, features = ["metadata"]}
+stm32-metapac = { version = "13", default-features = false, features = ["metadata"]}
 
 [features]
 default = ["rt"]

embassy-stm32/src/dac/mod.rs

@@ -38,11 +38,30 @@ impl Channel {
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 /// Trigger sources for CH1
 pub enum Ch1Trigger {
-    Tim6,
+    #[cfg(dac_v3)]
-    Tim3,
+    Tim1,
-    Tim7,
-    Tim15,
     Tim2,
+    #[cfg(not(dac_v2))]
+    Tim3,
+    #[cfg(dac_v3)]
+    Tim4,
+    #[cfg(dac_v3)]
+    Tim5,
+    Tim6,
+    Tim7,
+    #[cfg(dac_v3)]
+    Tim8,
+    Tim15,
+    #[cfg(dac_v3)]
+    Hrtim1Dactrg1,
+    #[cfg(dac_v3)]
+    Hrtim1Dactrg2,
+    #[cfg(dac_v3)]
+    Lptim1,
+    #[cfg(dac_v3)]
+    Lptim2,
+    #[cfg(dac_v3)]
+    Lptim3,
     Exti9,
     Software,
 }
@@ -50,11 +69,30 @@ pub enum Ch1Trigger {
 impl Ch1Trigger {
     fn tsel(&self) -> dac::vals::Tsel1 {
         match self {
-            Ch1Trigger::Tim6 => dac::vals::Tsel1::TIM6_TRGO,
+            #[cfg(dac_v3)]
-            Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM3_TRGO,
+            Ch1Trigger::Tim1 => dac::vals::Tsel1::TIM1_TRGO,
-            Ch1Trigger::Tim7 => dac::vals::Tsel1::TIM7_TRGO,
-            Ch1Trigger::Tim15 => dac::vals::Tsel1::TIM15_TRGO,
             Ch1Trigger::Tim2 => dac::vals::Tsel1::TIM2_TRGO,
+            #[cfg(dac_v2)]
+            Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM3_TRGO,
+            #[cfg(dac_v3)]
+            Ch1Trigger::Tim4 => dac::vals::Tsel1::TIM4_TRGO,
+            #[cfg(dac_v3)]
+            Ch1Trigger::Tim5 => dac::vals::Tsel1::TIM5_TRGO,
+            Ch1Trigger::Tim6 => dac::vals::Tsel1::TIM6_TRGO,
+            Ch1Trigger::Tim7 => dac::vals::Tsel1::TIM7_TRGO,
+            #[cfg(dac_v3)]
+            Ch1Trigger::Tim8 => dac::vals::Tsel1::TIM8_TRGO,
+            Ch1Trigger::Tim15 => dac::vals::Tsel1::TIM15_TRGO,
+            #[cfg(dac_v3)]
+            Ch1Trigger::Hrtim1Dactrg1 => dac::vals::Tsel1::HRTIM1_DACTRG1,
+            #[cfg(dac_v3)]
+            Ch1Trigger::Hrtim1Dactrg2 => dac::vals::Tsel1::HRTIM1_DACTRG2,
+            #[cfg(dac_v3)]
+            Ch1Trigger::Lptim1 => dac::vals::Tsel1::LPTIM1_OUT,
+            #[cfg(dac_v3)]
+            Ch1Trigger::Lptim2 => dac::vals::Tsel1::LPTIM2_OUT,
+            #[cfg(dac_v3)]
+            Ch1Trigger::Lptim3 => dac::vals::Tsel1::LPTIM3_OUT,
             Ch1Trigger::Exti9 => dac::vals::Tsel1::EXTI9,
             Ch1Trigger::Software => dac::vals::Tsel1::SOFTWARE,
         }
@@ -363,7 +401,6 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
     /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
     ///
     /// **Important:** Channel 2 has to be configured for the DAC instance!
-    #[cfg(all(bdma, not(dma)))] // It currently only works with BDMA-only chips (DMA should theoretically work though)
     pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
     where
         Tx: DmaCh2<T>,
@@ -467,7 +504,7 @@ impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
         dac_ch1.enable_channel().unwrap();
         dac_ch1.set_trigger_enable(true).unwrap();
 
-        #[cfg(dac_v2)]
+        #[cfg(any(dac_v2, dac_v3))]
         dac_ch2.set_channel_mode(0).unwrap();
         dac_ch2.enable_channel().unwrap();
         dac_ch2.set_trigger_enable(true).unwrap();

embassy-stm32/src/dma/dma.rs

@@ -28,6 +28,12 @@ pub struct TransferOptions {
     pub flow_ctrl: FlowControl,
     /// FIFO threshold for DMA FIFO mode. If none, direct mode is used.
     pub fifo_threshold: Option<FifoThreshold>,
+    /// Enable circular DMA
+    pub circular: bool,
+    /// Enable half transfer interrupt
+    pub half_transfer_ir: bool,
+    /// Enable transfer complete interrupt
+    pub complete_transfer_ir: bool,
 }
 
 impl Default for TransferOptions {
@@ -37,6 +43,9 @@ impl Default for TransferOptions {
             mburst: Burst::Single,
             flow_ctrl: FlowControl::Dma,
             fifo_threshold: None,
+            circular: false,
+            half_transfer_ir: false,
+            complete_transfer_ir: true,
         }
     }
 }
@@ -365,7 +374,13 @@ impl<'a, C: Channel> Transfer<'a, C> {
             });
             w.set_pinc(vals::Inc::FIXED);
             w.set_teie(true);
-            w.set_tcie(true);
+            w.set_tcie(options.complete_transfer_ir);
+            if options.circular {
+                w.set_circ(vals::Circ::ENABLED);
+                debug!("Setting circular mode");
+            } else {
+                w.set_circ(vals::Circ::DISABLED);
+            }
             #[cfg(dma_v1)]
             w.set_trbuff(true);
 
@@ -646,7 +661,7 @@ impl<'a, C: Channel, W: Word> RingBuffer<'a, C, W> {
         w.set_minc(vals::Inc::INCREMENTED);
         w.set_pinc(vals::Inc::FIXED);
         w.set_teie(true);
-        w.set_htie(true);
+        w.set_htie(options.half_transfer_ir);
         w.set_tcie(true);
         w.set_circ(vals::Circ::ENABLED);
         #[cfg(dma_v1)]