From ee3b82b74347cef97b58fee075972e175f98874b Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Wed, 2 Jun 2021 16:34:37 +0200 Subject: [PATCH 1/9] Auto generate SPI v2 clock enable Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral. Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI. --- embassy-stm32/src/dac/mod.rs | 2 ++ embassy-stm32/src/rcc/mod.rs | 38 ++++++++++++++++++++++++++++++++++++ embassy-stm32/src/spi/v2.rs | 17 +++++++++------- stm32-metapac/build.rs | 15 ++++++++++++++ 4 files changed, 65 insertions(+), 7 deletions(-) diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs index 0a15563ef..c74261595 100644 --- a/embassy-stm32/src/dac/mod.rs +++ b/embassy-stm32/src/dac/mod.rs @@ -51,3 +51,5 @@ crate::pac::peripheral_pins!( } }; ); + + diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs index 7112ad02f..6ad90eb82 100644 --- a/embassy-stm32/src/rcc/mod.rs +++ b/embassy-stm32/src/rcc/mod.rs @@ -1,3 +1,6 @@ +#![macro_use] + +use crate::peripherals; use crate::time::Hertz; use core::mem::MaybeUninit; @@ -44,3 +47,38 @@ cfg_if::cfg_if! { } } } + +pub(crate) mod sealed { + pub trait RccPeripheral { + fn reset(); + fn enable(); + fn disable(); + } +} + +pub trait RccPeripheral: sealed::RccPeripheral + 'static {} + +crate::pac::peripheral_rcc!( + ($inst:ident, $enable:ident, $reset:ident, $perien:ident, $perirst:ident) => { + impl sealed::RccPeripheral for peripherals::$inst { + fn enable() { + unsafe { + crate::pac::RCC.$enable().modify(|w| w.$perien(true)); + } + } + fn disable() { + unsafe { + crate::pac::RCC.$enable().modify(|w| w.$perien(false)); + } + } + fn reset() { + unsafe { + crate::pac::RCC.$reset().modify(|w| w.$perirst(true)); + crate::pac::RCC.$reset().modify(|w| w.$perirst(false)); + } + } + } + + impl RccPeripheral for peripherals::$inst {} + }; +); diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs index 46fe817ea..8f91ca5a7 100644 --- a/embassy-stm32/src/spi/v2.rs +++ b/embassy-stm32/src/spi/v2.rs @@ -4,6 +4,7 @@ use crate::gpio::{AnyPin, Pin}; use crate::pac::gpio::vals::{Afr, Moder}; use crate::pac::gpio::Gpio; use crate::pac::spi; +use crate::rcc::RccPeripheral; use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; use crate::time::Hertz; use core::marker::PhantomData; @@ -28,14 +29,14 @@ impl WordSize { } } -pub struct Spi<'d, T: Instance> { +pub struct Spi<'d, T: Instance + RccPeripheral> { sck: AnyPin, mosi: AnyPin, miso: AnyPin, phantom: PhantomData<&'d mut T>, } -impl<'d, T: Instance> Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> Spi<'d, T> { pub fn new( pclk: Hertz, _peri: impl Unborrow + 'd, @@ -63,6 +64,8 @@ impl<'d, T: Instance> Spi<'d, T> { let br = Self::compute_baud_rate(pclk, freq.into()); unsafe { + T::enable(); + T::reset(); T::regs().cr2().modify(|w| { w.set_ssoe(false); }); @@ -140,7 +143,7 @@ impl<'d, T: Instance> Spi<'d, T> { } } -impl<'d, T: Instance> Drop for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> Drop for Spi<'d, T> { fn drop(&mut self) { unsafe { Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _); @@ -198,7 +201,7 @@ fn read_word(regs: &'static crate::pac::spi::Spi) -> Result { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { @@ -214,7 +217,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { @@ -230,7 +233,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> { @@ -246,7 +249,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> { diff --git a/stm32-metapac/build.rs b/stm32-metapac/build.rs index 083e06bfd..91b76b2a4 100644 --- a/stm32-metapac/build.rs +++ b/stm32-metapac/build.rs @@ -136,6 +136,7 @@ fn main() { let mut interrupt_table: Vec> = Vec::new(); let mut peripherals_table: Vec> = Vec::new(); let mut peripheral_pins_table: Vec> = Vec::new(); + let mut peripheral_rcc_table: Vec> = Vec::new(); let dma_base = chip .peripherals @@ -216,6 +217,19 @@ fn main() { }; assert_eq!(p.address, dma_base + dma_stride * dma_num); } + "spi" => { + if let Some(clock) = &p.clock { + let reg = clock.to_ascii_lowercase(); + let field = name.to_ascii_lowercase(); + peripheral_rcc_table.push(vec![ + name.clone(), + format!("{}enr", reg), + format!("{}rstr", reg), + format!("set_{}en", field), + format!("set_{}rst", field), + ]); + } + } _ => {} } } @@ -255,6 +269,7 @@ fn main() { make_table(&mut extra, "peripherals", &peripherals_table); make_table(&mut extra, "peripheral_versions", &peripheral_version_table); make_table(&mut extra, "peripheral_pins", &peripheral_pins_table); + make_table(&mut extra, "peripheral_rcc", &peripheral_rcc_table); for (module, version) in peripheral_versions { println!("loading {} {}", module, version); From ee47a3e802a674cd002f944b3362e2ab71e2cf5e Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 8 Jun 2021 10:41:02 +0200 Subject: [PATCH 2/9] Add workaround for STM32H7 --- stm32-metapac/build.rs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/stm32-metapac/build.rs b/stm32-metapac/build.rs index 91b76b2a4..46660d9bd 100644 --- a/stm32-metapac/build.rs +++ b/stm32-metapac/build.rs @@ -219,7 +219,12 @@ fn main() { } "spi" => { if let Some(clock) = &p.clock { - let reg = clock.to_ascii_lowercase(); + // Workaround for APB1 register being split on some chip families + let reg = if chip.family == "STM32H7" && clock == "APB1" { + format!("{}l", clock.to_ascii_lowercase()) + } else { + clock.to_ascii_lowercase() + }; let field = name.to_ascii_lowercase(); peripheral_rcc_table.push(vec![ name.clone(), From 459049d60436e177a628df0104959b7789e710af Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 8 Jun 2021 10:57:52 +0200 Subject: [PATCH 3/9] Workaround for L4 --- stm32-metapac/build.rs | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/stm32-metapac/build.rs b/stm32-metapac/build.rs index 46660d9bd..72750267d 100644 --- a/stm32-metapac/build.rs +++ b/stm32-metapac/build.rs @@ -219,17 +219,22 @@ fn main() { } "spi" => { if let Some(clock) = &p.clock { - // Workaround for APB1 register being split on some chip families - let reg = if chip.family == "STM32H7" && clock == "APB1" { - format!("{}l", clock.to_ascii_lowercase()) + // Workaround for APB1 register being split on some chip families. Assume + // first register until we can find a way to hint which register is used + let reg = clock.to_ascii_lowercase(); + let (enable_reg, reset_reg) = if chip.family == "STM32H7" && clock == "APB1" + { + (format!("{}lenr", reg), format!("{}lrstr", reg)) + } else if chip.family == "STM32L4" && clock == "APB1" { + (format!("{}enr1", reg), format!("{}rstr1", reg)) } else { - clock.to_ascii_lowercase() + (format!("{}enr", reg), format!("{}rstr", reg)) }; let field = name.to_ascii_lowercase(); peripheral_rcc_table.push(vec![ name.clone(), - format!("{}enr", reg), - format!("{}rstr", reg), + enable_reg, + reset_reg, format!("set_{}en", field), format!("set_{}rst", field), ]); From a57482fddde69777ffc3c964d2d2d92d15d45340 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 8 Jun 2021 11:02:35 +0200 Subject: [PATCH 4/9] Cargo fmt --- embassy-stm32/src/dac/mod.rs | 2 -- 1 file changed, 2 deletions(-) diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs index c74261595..0a15563ef 100644 --- a/embassy-stm32/src/dac/mod.rs +++ b/embassy-stm32/src/dac/mod.rs @@ -51,5 +51,3 @@ crate::pac::peripheral_pins!( } }; ); - - From 212bda09406923b22cf5b5ed70cd8dbf7f9a7f3f Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 8 Jun 2021 11:04:44 +0200 Subject: [PATCH 5/9] Enable clock for SPI v1 and v3 --- embassy-stm32/src/spi/v1.rs | 17 ++++++++++------- embassy-stm32/src/spi/v3.rs | 17 ++++++++++------- 2 files changed, 20 insertions(+), 14 deletions(-) diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs index e3057a3b5..a4e4c0ba1 100644 --- a/embassy-stm32/src/spi/v1.rs +++ b/embassy-stm32/src/spi/v1.rs @@ -2,6 +2,7 @@ use crate::gpio::{sealed::Pin, AnyPin}; use crate::pac::spi; +use crate::rcc::RccPeripheral; use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; use crate::time::Hertz; use core::marker::PhantomData; @@ -19,7 +20,7 @@ impl WordSize { } } -pub struct Spi<'d, T: Instance> { +pub struct Spi<'d, T: Instance + RccPeripheral> { sck: AnyPin, mosi: AnyPin, miso: AnyPin, @@ -27,7 +28,7 @@ pub struct Spi<'d, T: Instance> { phantom: PhantomData<&'d mut T>, } -impl<'d, T: Instance> Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> Spi<'d, T> { pub fn new( pclk: Hertz, _peri: impl Unborrow + 'd, @@ -61,6 +62,8 @@ impl<'d, T: Instance> Spi<'d, T> { let br = Self::compute_baud_rate(pclk, freq.into()); unsafe { + T::enable(); + T::reset(); T::regs().cr1().modify(|w| { w.set_cpha( match config.mode.phase == Phase::CaptureOnSecondTransition { @@ -128,7 +131,7 @@ impl<'d, T: Instance> Spi<'d, T> { } } -impl<'d, T: Instance> Drop for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> Drop for Spi<'d, T> { fn drop(&mut self) { unsafe { self.sck.set_as_analog(); @@ -138,7 +141,7 @@ impl<'d, T: Instance> Drop for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { @@ -174,7 +177,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { @@ -215,7 +218,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> { @@ -251,7 +254,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> { diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs index da4686b9c..3b768751d 100644 --- a/embassy-stm32/src/spi/v3.rs +++ b/embassy-stm32/src/spi/v3.rs @@ -4,6 +4,7 @@ use crate::gpio::{AnyPin, Pin}; use crate::pac::gpio::vals::{Afr, Moder}; use crate::pac::gpio::Gpio; use crate::pac::spi; +use crate::rcc::RccPeripheral; use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; use crate::time::Hertz; use core::marker::PhantomData; @@ -28,14 +29,14 @@ impl WordSize { } } -pub struct Spi<'d, T: Instance> { +pub struct Spi<'d, T: Instance + RccPeripheral> { sck: AnyPin, mosi: AnyPin, miso: AnyPin, phantom: PhantomData<&'d mut T>, } -impl<'d, T: Instance> Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> Spi<'d, T> { pub fn new( pclk: Hertz, _peri: impl Unborrow + 'd, @@ -64,6 +65,8 @@ impl<'d, T: Instance> Spi<'d, T> { let br = Self::compute_baud_rate(pclk, freq.into()); unsafe { + T::enable(); + T::reset(); T::regs().ifcr().write(|w| w.0 = 0xffff_ffff); T::regs().cfg2().modify(|w| { //w.set_ssoe(true); @@ -161,7 +164,7 @@ impl<'d, T: Instance> Spi<'d, T> { } } -impl<'d, T: Instance> Drop for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> Drop for Spi<'d, T> { fn drop(&mut self) { unsafe { Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _); @@ -171,7 +174,7 @@ impl<'d, T: Instance> Drop for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { @@ -208,7 +211,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { @@ -265,7 +268,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> { @@ -302,7 +305,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> { From ed29d820719a18afd708e2a54585425ab70db82e Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 8 Jun 2021 13:10:40 +0200 Subject: [PATCH 6/9] Use critical_section --- embassy-stm32/src/rcc/mod.rs | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs index 6ad90eb82..3c5b53b05 100644 --- a/embassy-stm32/src/rcc/mod.rs +++ b/embassy-stm32/src/rcc/mod.rs @@ -62,20 +62,26 @@ crate::pac::peripheral_rcc!( ($inst:ident, $enable:ident, $reset:ident, $perien:ident, $perirst:ident) => { impl sealed::RccPeripheral for peripherals::$inst { fn enable() { - unsafe { - crate::pac::RCC.$enable().modify(|w| w.$perien(true)); - } + critical_section::with(|_| { + unsafe { + crate::pac::RCC.$enable().modify(|w| w.$perien(true)); + } + }) } fn disable() { - unsafe { - crate::pac::RCC.$enable().modify(|w| w.$perien(false)); - } + critical_section::with(|_| { + unsafe { + crate::pac::RCC.$enable().modify(|w| w.$perien(false)); + } + }) } fn reset() { - unsafe { - crate::pac::RCC.$reset().modify(|w| w.$perirst(true)); - crate::pac::RCC.$reset().modify(|w| w.$perirst(false)); - } + critical_section::with(|_| { + unsafe { + crate::pac::RCC.$reset().modify(|w| w.$perirst(true)); + crate::pac::RCC.$reset().modify(|w| w.$perirst(false)); + } + }) } } From 939ea3bbd0bb41a1deed3ac27ca3974db0f7d043 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 8 Jun 2021 13:10:58 +0200 Subject: [PATCH 7/9] Reduce generics noise --- embassy-stm32/src/spi/mod.rs | 4 ++-- embassy-stm32/src/spi/v1.rs | 15 +++++++-------- embassy-stm32/src/spi/v2.rs | 15 +++++++-------- embassy-stm32/src/spi/v3.rs | 15 +++++++-------- 4 files changed, 23 insertions(+), 26 deletions(-) diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index 730169ec0..9b04c03aa 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -4,7 +4,7 @@ #[cfg_attr(spi_v2, path = "v2.rs")] #[cfg_attr(spi_v3, path = "v3.rs")] mod _version; -use crate::peripherals; +use crate::{peripherals, rcc::RccPeripheral}; pub use _version::*; use crate::gpio::Pin; @@ -64,7 +64,7 @@ pub(crate) mod sealed { } } -pub trait Instance: sealed::Instance + 'static {} +pub trait Instance: sealed::Instance + RccPeripheral + 'static {} pub trait SckPin: sealed::SckPin + 'static {} diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs index a4e4c0ba1..227a36a89 100644 --- a/embassy-stm32/src/spi/v1.rs +++ b/embassy-stm32/src/spi/v1.rs @@ -2,7 +2,6 @@ use crate::gpio::{sealed::Pin, AnyPin}; use crate::pac::spi; -use crate::rcc::RccPeripheral; use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; use crate::time::Hertz; use core::marker::PhantomData; @@ -20,7 +19,7 @@ impl WordSize { } } -pub struct Spi<'d, T: Instance + RccPeripheral> { +pub struct Spi<'d, T: Instance> { sck: AnyPin, mosi: AnyPin, miso: AnyPin, @@ -28,7 +27,7 @@ pub struct Spi<'d, T: Instance + RccPeripheral> { phantom: PhantomData<&'d mut T>, } -impl<'d, T: Instance + RccPeripheral> Spi<'d, T> { +impl<'d, T: Instance> Spi<'d, T> { pub fn new( pclk: Hertz, _peri: impl Unborrow + 'd, @@ -131,7 +130,7 @@ impl<'d, T: Instance + RccPeripheral> Spi<'d, T> { } } -impl<'d, T: Instance + RccPeripheral> Drop for Spi<'d, T> { +impl<'d, T: Instance> Drop for Spi<'d, T> { fn drop(&mut self) { unsafe { self.sck.set_as_analog(); @@ -141,7 +140,7 @@ impl<'d, T: Instance + RccPeripheral> Drop for Spi<'d, T> { } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { @@ -177,7 +176,7 @@ impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { @@ -218,7 +217,7 @@ impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> { @@ -254,7 +253,7 @@ impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write fo } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> { diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs index 8f91ca5a7..a7ac54cdd 100644 --- a/embassy-stm32/src/spi/v2.rs +++ b/embassy-stm32/src/spi/v2.rs @@ -4,7 +4,6 @@ use crate::gpio::{AnyPin, Pin}; use crate::pac::gpio::vals::{Afr, Moder}; use crate::pac::gpio::Gpio; use crate::pac::spi; -use crate::rcc::RccPeripheral; use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; use crate::time::Hertz; use core::marker::PhantomData; @@ -29,14 +28,14 @@ impl WordSize { } } -pub struct Spi<'d, T: Instance + RccPeripheral> { +pub struct Spi<'d, T: Instance> { sck: AnyPin, mosi: AnyPin, miso: AnyPin, phantom: PhantomData<&'d mut T>, } -impl<'d, T: Instance + RccPeripheral> Spi<'d, T> { +impl<'d, T: Instance> Spi<'d, T> { pub fn new( pclk: Hertz, _peri: impl Unborrow + 'd, @@ -143,7 +142,7 @@ impl<'d, T: Instance + RccPeripheral> Spi<'d, T> { } } -impl<'d, T: Instance + RccPeripheral> Drop for Spi<'d, T> { +impl<'d, T: Instance> Drop for Spi<'d, T> { fn drop(&mut self) { unsafe { Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _); @@ -201,7 +200,7 @@ fn read_word(regs: &'static crate::pac::spi::Spi) -> Result { } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { @@ -217,7 +216,7 @@ impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { @@ -233,7 +232,7 @@ impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> { @@ -249,7 +248,7 @@ impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write fo } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> { diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs index 3b768751d..6073616bd 100644 --- a/embassy-stm32/src/spi/v3.rs +++ b/embassy-stm32/src/spi/v3.rs @@ -4,7 +4,6 @@ use crate::gpio::{AnyPin, Pin}; use crate::pac::gpio::vals::{Afr, Moder}; use crate::pac::gpio::Gpio; use crate::pac::spi; -use crate::rcc::RccPeripheral; use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; use crate::time::Hertz; use core::marker::PhantomData; @@ -29,14 +28,14 @@ impl WordSize { } } -pub struct Spi<'d, T: Instance + RccPeripheral> { +pub struct Spi<'d, T: Instance> { sck: AnyPin, mosi: AnyPin, miso: AnyPin, phantom: PhantomData<&'d mut T>, } -impl<'d, T: Instance + RccPeripheral> Spi<'d, T> { +impl<'d, T: Instance> Spi<'d, T> { pub fn new( pclk: Hertz, _peri: impl Unborrow + 'd, @@ -164,7 +163,7 @@ impl<'d, T: Instance + RccPeripheral> Spi<'d, T> { } } -impl<'d, T: Instance + RccPeripheral> Drop for Spi<'d, T> { +impl<'d, T: Instance> Drop for Spi<'d, T> { fn drop(&mut self) { unsafe { Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _); @@ -174,7 +173,7 @@ impl<'d, T: Instance + RccPeripheral> Drop for Spi<'d, T> { } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { @@ -211,7 +210,7 @@ impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { @@ -268,7 +267,7 @@ impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> { @@ -305,7 +304,7 @@ impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Write fo } } -impl<'d, T: Instance + RccPeripheral> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> { From 6e63bf7e4462db75d88cc76b1bbf52cbbced320c Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 8 Jun 2021 16:51:55 +0200 Subject: [PATCH 8/9] Update submodule ref --- stm32-data | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/stm32-data b/stm32-data index 6e4da8f04..4bb1b178c 160000 --- a/stm32-data +++ b/stm32-data @@ -1 +1 @@ -Subproject commit 6e4da8f04205dcc48767d12fac5cdfd170e52f18 +Subproject commit 4bb1b178cd1c555cfedaea31ad0be3c6a7b99563 From f7394e56ef6275ffc528e68ff6532dc14a976611 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 8 Jun 2021 17:37:41 +0200 Subject: [PATCH 9/9] Handle other L4 variants --- stm32-metapac/build.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/stm32-metapac/build.rs b/stm32-metapac/build.rs index 72750267d..008c9eb37 100644 --- a/stm32-metapac/build.rs +++ b/stm32-metapac/build.rs @@ -225,7 +225,7 @@ fn main() { let (enable_reg, reset_reg) = if chip.family == "STM32H7" && clock == "APB1" { (format!("{}lenr", reg), format!("{}lrstr", reg)) - } else if chip.family == "STM32L4" && clock == "APB1" { + } else if chip.family.starts_with("STM32L4") && clock == "APB1" { (format!("{}enr1", reg), format!("{}rstr1", reg)) } else { (format!("{}enr", reg), format!("{}rstr", reg))