From f5d084552d9f44d24f020269cc605de0fb4d1041 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Sat, 17 Jun 2023 11:48:21 +0200
Subject: [PATCH 01/48] implement mwe of a DMA write() method for DAC
---
embassy-stm32/build.rs | 2 +
embassy-stm32/src/{dac.rs => dac/mod.rs} | 76 +++++++++++++++++++++---
2 files changed, 71 insertions(+), 7 deletions(-)
rename embassy-stm32/src/{dac.rs => dac/mod.rs} (76%)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 9e597f187..e2bd01d7b 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -699,6 +699,8 @@ fn main() {
// SDMMCv1 uses the same channel for both directions, so just implement for RX
(("sdmmc", "RX"), quote!(crate::sdmmc::SdmmcDma)),
(("quadspi", "QUADSPI"), quote!(crate::qspi::QuadDma)),
+ (("dac", "CH1"), quote!(crate::dac::Dma)),
+ (("dac", "CH2"), quote!(crate::dac::Dma)),
]
.into();
diff --git a/embassy-stm32/src/dac.rs b/embassy-stm32/src/dac/mod.rs
similarity index 76%
rename from embassy-stm32/src/dac.rs
rename to embassy-stm32/src/dac/mod.rs
index 60e856c78..348d8bccd 100644
--- a/embassy-stm32/src/dac.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -2,6 +2,7 @@
use embassy_hal_common::{into_ref, PeripheralRef};
+use crate::dma::{slice_ptr_parts, word, Transfer};
use crate::pac::dac;
use crate::rcc::RccPeripheral;
use crate::{peripherals, Peripheral};
@@ -97,39 +98,58 @@ pub enum Value {
Bit12(u16, Alignment),
}
-pub struct Dac<'d, T: Instance> {
+pub struct Dac<'d, T: Instance, Tx> {
channels: u8,
+ txdma: PeripheralRef<'d, Tx>,
_peri: PeripheralRef<'d, T>,
}
-impl<'d, T: Instance> Dac<'d, T> {
- pub fn new_1ch(peri: impl Peripheral + 'd, _ch1: impl Peripheral
> + 'd) -> Self {
+impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
+ pub fn new_1ch(
+ peri: impl Peripheral
+ 'd,
+ txdma: impl Peripheral
+ 'd,
+ _ch1: impl Peripheral
> + 'd,
+ ) -> Self {
into_ref!(peri);
- Self::new_inner(peri, 1)
+ Self::new_inner(peri, 1, txdma)
}
pub fn new_2ch(
peri: impl Peripheral
+ 'd,
+ txdma: impl Peripheral
+ 'd,
_ch1: impl Peripheral
> + 'd,
_ch2: impl Peripheral
> + 'd,
) -> Self {
into_ref!(peri);
- Self::new_inner(peri, 2)
+ Self::new_inner(peri, 2, txdma)
}
- fn new_inner(peri: PeripheralRef<'d, T>, channels: u8) -> Self {
+ fn new_inner(peri: PeripheralRef<'d, T>, channels: u8, txdma: impl Peripheral
+ 'd) -> Self {
+ into_ref!(txdma);
T::enable();
T::reset();
unsafe {
+ T::regs().mcr().modify(|reg| {
+ for ch in 0..channels {
+ reg.set_mode(ch as usize, 0);
+ reg.set_mode(ch as usize, 0);
+ }
+ });
+
T::regs().cr().modify(|reg| {
for ch in 0..channels {
reg.set_en(ch as usize, true);
+ reg.set_ten(ch as usize, true);
}
});
}
- Self { channels, _peri: peri }
+ Self {
+ channels,
+ txdma,
+ _peri: peri,
+ }
}
/// Check the channel is configured
@@ -215,6 +235,47 @@ impl<'d, T: Instance> Dac<'d, T> {
}
Ok(())
}
+
+ /// TODO: Allow an array of Value instead of only u16, right-aligned
+ pub async fn write(&mut self, data: &[u16]) -> Result<(), Error>
+ where
+ Tx: Dma,
+ {
+ // TODO: Make this a parameter or get it from the struct or so...
+ const CHANNEL: usize = 0;
+
+ //debug!("Starting DAC");
+ unsafe {
+ T::regs().cr().modify(|w| {
+ w.set_en(CHANNEL, true);
+ w.set_dmaen(CHANNEL, true);
+ });
+ }
+
+ let tx_request = self.txdma.request();
+
+ // Use the 12 bit right-aligned register for now. TODO: distinguish values
+ let tx_dst = T::regs().dhr12r(CHANNEL).ptr() as *mut u16;
+
+ let tx_f = unsafe { Transfer::new_write(&mut self.txdma, tx_request, data, tx_dst, Default::default()) };
+
+ //debug!("Awaiting tx_f");
+
+ tx_f.await;
+
+ // finish dma
+ unsafe {
+ // TODO: Do we need to check any status registers here?
+
+ T::regs().cr().modify(|w| {
+ // Disable the dac peripheral
+ //w.set_en(CHANNEL, false);
+ // Disable the DMA. TODO: Is this necessary?
+ //w.set_dmaen(CHANNEL, false);
+ });
+ }
+ Ok(())
+ }
}
pub(crate) mod sealed {
@@ -224,6 +285,7 @@ pub(crate) mod sealed {
}
pub trait Instance: sealed::Instance + RccPeripheral + 'static {}
+dma_trait!(Dma, Instance);
pub trait DacPin: crate::gpio::Pin + 'static {}
From 78a2ca8a0e5af3fe2c76a6cd025b74ea4322f6cf Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Sat, 17 Jun 2023 11:51:57 +0200
Subject: [PATCH 02/48] remove unnecessary use, disable DAC and DMA after
transfer
---
embassy-stm32/src/dac/mod.rs | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 348d8bccd..7b81ec1f2 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -2,7 +2,7 @@
use embassy_hal_common::{into_ref, PeripheralRef};
-use crate::dma::{slice_ptr_parts, word, Transfer};
+use crate::dma::Transfer;
use crate::pac::dac;
use crate::rcc::RccPeripheral;
use crate::{peripherals, Peripheral};
@@ -269,9 +269,9 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
T::regs().cr().modify(|w| {
// Disable the dac peripheral
- //w.set_en(CHANNEL, false);
+ w.set_en(CHANNEL, false);
// Disable the DMA. TODO: Is this necessary?
- //w.set_dmaen(CHANNEL, false);
+ w.set_dmaen(CHANNEL, false);
});
}
Ok(())
From f8ee33abb9943d6fe57c126eeecb36db9935c4ba Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Sun, 18 Jun 2023 18:51:36 +0200
Subject: [PATCH 03/48] add half transfer interrupt and circular dma
---
embassy-stm32/src/dac/mod.rs | 17 ++++++++++++++---
embassy-stm32/src/dma/bdma.rs | 26 ++++++++++++++++++++++----
2 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 7b81ec1f2..525d45d72 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -2,7 +2,7 @@
use embassy_hal_common::{into_ref, PeripheralRef};
-use crate::dma::Transfer;
+use crate::dma::{Transfer, TransferOptions};
use crate::pac::dac;
use crate::rcc::RccPeripheral;
use crate::{peripherals, Peripheral};
@@ -237,7 +237,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
}
/// TODO: Allow an array of Value instead of only u16, right-aligned
- pub async fn write(&mut self, data: &[u16]) -> Result<(), Error>
+ pub async fn write(&mut self, data: &[u16], circular: bool) -> Result<(), Error>
where
Tx: Dma,
{
@@ -257,7 +257,18 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
// Use the 12 bit right-aligned register for now. TODO: distinguish values
let tx_dst = T::regs().dhr12r(CHANNEL).ptr() as *mut u16;
- let tx_f = unsafe { Transfer::new_write(&mut self.txdma, tx_request, data, tx_dst, Default::default()) };
+ let tx_f = unsafe {
+ Transfer::new_write(
+ &mut self.txdma,
+ tx_request,
+ data,
+ tx_dst,
+ TransferOptions {
+ circular,
+ halt_transfer_ir: false,
+ },
+ )
+ };
//debug!("Awaiting tx_f");
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index c0a503e25..ca18047e7 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -1,6 +1,7 @@
#![macro_use]
use core::future::Future;
+use core::option;
use core::pin::Pin;
use core::sync::atomic::{fence, Ordering};
use core::task::{Context, Poll, Waker};
@@ -21,11 +22,17 @@ use crate::pac::bdma::{regs, vals};
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive]
-pub struct TransferOptions {}
+pub struct TransferOptions {
+ pub circular: bool,
+ pub halt_transfer_ir: bool,
+}
impl Default for TransferOptions {
fn default() -> Self {
- Self {}
+ Self {
+ circular: false,
+ halt_transfer_ir: false,
+ }
}
}
@@ -253,7 +260,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
mem_len: usize,
incr_mem: bool,
data_size: WordSize,
- _options: TransferOptions,
+ options: TransferOptions,
) -> Self {
let ch = channel.regs().ch(channel.num());
@@ -284,6 +291,14 @@ impl<'a, C: Channel> Transfer<'a, C> {
w.set_dir(dir.into());
w.set_teie(true);
w.set_tcie(true);
+ w.set_htie(options.halt_transfer_ir);
+ if options.circular {
+ w.set_circ(vals::Circ::ENABLED);
+ debug!("Setting circular mode");
+ } else {
+ w.set_circ(vals::Circ::DISABLED);
+ }
+ w.set_pl(vals::Pl::VERYHIGH);
w.set_en(true);
});
@@ -314,8 +329,9 @@ impl<'a, C: Channel> Transfer<'a, C> {
pub fn is_running(&mut self) -> bool {
let ch = self.channel.regs().ch(self.channel.num());
let en = unsafe { ch.cr().read() }.en();
+ let circular = unsafe { ch.cr().read() }.circ() == vals::Circ::ENABLED;
let tcif = STATE.complete_count[self.channel.index()].load(Ordering::Acquire) != 0;
- en && !tcif
+ en && (circular || !tcif)
}
/// Gets the total remaining transfers for the channel
@@ -482,6 +498,8 @@ impl<'a, C: Channel, W: Word> RingBuffer<'a, C, W> {
let ch = self.channel.regs().ch(self.channel.num());
// Disable the channel. Keep the IEs enabled so the irqs still fire.
+ // If the channel is enabled and transfer is not completed, we need to perform
+ // two separate write access to the CR register to disable the channel.
unsafe {
ch.cr().write(|w| {
w.set_teie(true);
From e0747e937f06ed280594e17c97d19784410b6e85 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Mon, 19 Jun 2023 11:15:09 +0200
Subject: [PATCH 04/48] remove unsafe for circular dma reg access
---
embassy-stm32/src/dma/bdma.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index be4571440..3d315e20b 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -325,7 +325,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
pub fn is_running(&mut self) -> bool {
let ch = self.channel.regs().ch(self.channel.num());
let en = ch.cr().read().en();
- let circular = unsafe { ch.cr().read() }.circ() == vals::Circ::ENABLED;
+ let circular = ch.cr().read().circ() == vals::Circ::ENABLED;
let tcif = STATE.complete_count[self.channel.index()].load(Ordering::Acquire) != 0;
en && (circular || !tcif)
}
From fe7b72948ab5d3682f23e305f3eb7186cc308b1b Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Mon, 19 Jun 2023 13:42:25 +0200
Subject: [PATCH 05/48] add ValueArray type and respective write functions
---
embassy-stm32/src/dac/mod.rs | 206 +++++++++++++++++++++--------------
1 file changed, 124 insertions(+), 82 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 525d45d72..4384a7c34 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -98,6 +98,14 @@ pub enum Value {
Bit12(u16, Alignment),
}
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum ValueArray<'a> {
+ Bit8(&'a [u8]),
+ Bit12Left(&'a [u16]),
+ Bit12Right(&'a [u16]),
+}
+
pub struct Dac<'d, T: Instance, Tx> {
channels: u8,
txdma: PeripheralRef<'d, Tx>,
@@ -129,21 +137,19 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
T::enable();
T::reset();
- unsafe {
- T::regs().mcr().modify(|reg| {
- for ch in 0..channels {
- reg.set_mode(ch as usize, 0);
- reg.set_mode(ch as usize, 0);
- }
- });
+ T::regs().mcr().modify(|reg| {
+ for ch in 0..channels {
+ reg.set_mode(ch as usize, 0);
+ reg.set_mode(ch as usize, 0);
+ }
+ });
- T::regs().cr().modify(|reg| {
- for ch in 0..channels {
- reg.set_en(ch as usize, true);
- reg.set_ten(ch as usize, true);
- }
- });
- }
+ T::regs().cr().modify(|reg| {
+ for ch in 0..channels {
+ reg.set_en(ch as usize, true);
+ reg.set_ten(ch as usize, true);
+ }
+ });
Self {
channels,
@@ -161,13 +167,12 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
}
}
+ /// Set the enable register of the given channel
fn set_channel_enable(&mut self, ch: Channel, on: bool) -> Result<(), Error> {
self.check_channel_exists(ch)?;
- unsafe {
- T::regs().cr().modify(|reg| {
- reg.set_en(ch.index(), on);
- })
- }
+ T::regs().cr().modify(|reg| {
+ reg.set_en(ch.index(), on);
+ });
Ok(())
}
@@ -179,112 +184,149 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
self.set_channel_enable(ch, false)
}
+ /// Performs all register accesses necessary to select a new trigger for CH1
pub fn select_trigger_ch1(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
self.check_channel_exists(Channel::Ch1)?;
unwrap!(self.disable_channel(Channel::Ch1));
- unsafe {
- T::regs().cr().modify(|reg| {
- reg.set_tsel1(trigger.tsel());
- })
- }
+ T::regs().cr().modify(|reg| {
+ reg.set_tsel1(trigger.tsel());
+ });
Ok(())
}
+ /// Performs all register accesses necessary to select a new trigger for CH2
pub fn select_trigger_ch2(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
self.check_channel_exists(Channel::Ch2)?;
unwrap!(self.disable_channel(Channel::Ch2));
- unsafe {
- T::regs().cr().modify(|reg| {
- reg.set_tsel2(trigger.tsel());
- })
- }
+ T::regs().cr().modify(|reg| {
+ reg.set_tsel2(trigger.tsel());
+ });
Ok(())
}
+ /// Perform a software trigger on a given channel
pub fn trigger(&mut self, ch: Channel) -> Result<(), Error> {
self.check_channel_exists(ch)?;
- unsafe {
- T::regs().swtrigr().write(|reg| {
- reg.set_swtrig(ch.index(), true);
- });
- }
+ T::regs().swtrigr().write(|reg| {
+ reg.set_swtrig(ch.index(), true);
+ });
Ok(())
}
+ /// Perform a software trigger on all channels
pub fn trigger_all(&mut self) {
- unsafe {
- T::regs().swtrigr().write(|reg| {
- reg.set_swtrig(Channel::Ch1.index(), true);
- reg.set_swtrig(Channel::Ch2.index(), true);
- })
- }
+ T::regs().swtrigr().write(|reg| {
+ reg.set_swtrig(Channel::Ch1.index(), true);
+ reg.set_swtrig(Channel::Ch2.index(), true);
+ });
}
pub fn set(&mut self, ch: Channel, value: Value) -> Result<(), Error> {
self.check_channel_exists(ch)?;
match value {
- Value::Bit8(v) => unsafe {
- T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v));
- },
- Value::Bit12(v, Alignment::Left) => unsafe {
- T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v));
- },
- Value::Bit12(v, Alignment::Right) => unsafe {
- T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v));
- },
+ Value::Bit8(v) => T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v)),
+ Value::Bit12(v, Alignment::Left) => T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v)),
+ Value::Bit12(v, Alignment::Right) => T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v)),
}
Ok(())
}
+ /// Write `data` to the DAC via DMA.
+ ///
+ /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
+ /// This will configure a circular DMA transfer that periodically outputs the `data`.
+ ///
+ /// ## Current limitations
+ /// - Only CH1 Supported
+ ///
/// TODO: Allow an array of Value instead of only u16, right-aligned
- pub async fn write(&mut self, data: &[u16], circular: bool) -> Result<(), Error>
+ pub async fn write_8bit(&mut self, data_ch1: &[u8], circular: bool) -> Result<(), Error>
+ where
+ Tx: Dma,
+ {
+ self.write_inner(ValueArray::Bit8(data_ch1), circular).await
+ }
+
+ pub async fn write_12bit_right_aligned(&mut self, data_ch1: &[u16], circular: bool) -> Result<(), Error>
+ where
+ Tx: Dma,
+ {
+ self.write_inner(ValueArray::Bit12Right(data_ch1), circular).await
+ }
+
+ pub async fn write_12bit_left_aligned(&mut self, data_ch1: &[u16], circular: bool) -> Result<(), Error>
+ where
+ Tx: Dma,
+ {
+ self.write_inner(ValueArray::Bit12Left(data_ch1), circular).await
+ }
+
+ async fn write_inner(&mut self, data_ch1: ValueArray<'_>, circular: bool) -> Result<(), Error>
where
Tx: Dma,
{
// TODO: Make this a parameter or get it from the struct or so...
const CHANNEL: usize = 0;
- //debug!("Starting DAC");
- unsafe {
- T::regs().cr().modify(|w| {
- w.set_en(CHANNEL, true);
- w.set_dmaen(CHANNEL, true);
- });
- }
+ // Enable DAC and DMA
+ T::regs().cr().modify(|w| {
+ w.set_en(CHANNEL, true);
+ w.set_dmaen(CHANNEL, true);
+ });
let tx_request = self.txdma.request();
- // Use the 12 bit right-aligned register for now. TODO: distinguish values
- let tx_dst = T::regs().dhr12r(CHANNEL).ptr() as *mut u16;
-
- let tx_f = unsafe {
- Transfer::new_write(
- &mut self.txdma,
- tx_request,
- data,
- tx_dst,
- TransferOptions {
- circular,
- halt_transfer_ir: false,
- },
- )
+ // Initiate the correct type of DMA transfer depending on what data is passed
+ let tx_f = match data_ch1 {
+ ValueArray::Bit8(buf) => unsafe {
+ Transfer::new_write(
+ &mut self.txdma,
+ tx_request,
+ buf,
+ T::regs().dhr8r(CHANNEL).as_ptr() as *mut u8,
+ TransferOptions {
+ circular,
+ halt_transfer_ir: false,
+ },
+ )
+ },
+ ValueArray::Bit12Left(buf) => unsafe {
+ Transfer::new_write(
+ &mut self.txdma,
+ tx_request,
+ buf,
+ T::regs().dhr12l(CHANNEL).as_ptr() as *mut u16,
+ TransferOptions {
+ circular,
+ halt_transfer_ir: false,
+ },
+ )
+ },
+ ValueArray::Bit12Right(buf) => unsafe {
+ Transfer::new_write(
+ &mut self.txdma,
+ tx_request,
+ buf,
+ T::regs().dhr12r(CHANNEL).as_ptr() as *mut u16,
+ TransferOptions {
+ circular,
+ halt_transfer_ir: false,
+ },
+ )
+ },
};
- //debug!("Awaiting tx_f");
-
tx_f.await;
// finish dma
- unsafe {
- // TODO: Do we need to check any status registers here?
+ // TODO: Do we need to check any status registers here?
+ T::regs().cr().modify(|w| {
+ // Disable the DAC peripheral
+ w.set_en(CHANNEL, false);
+ // Disable the DMA. TODO: Is this necessary?
+ w.set_dmaen(CHANNEL, false);
+ });
- T::regs().cr().modify(|w| {
- // Disable the dac peripheral
- w.set_en(CHANNEL, false);
- // Disable the DMA. TODO: Is this necessary?
- w.set_dmaen(CHANNEL, false);
- });
- }
Ok(())
}
}
From 218b102b2840c9786944aa6f613450c876b6110b Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Mon, 19 Jun 2023 13:46:17 +0200
Subject: [PATCH 06/48] remove Alignment and make Value and Value array look
the same
---
embassy-stm32/src/dac/mod.rs | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 4384a7c34..0fbf67673 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -84,25 +84,25 @@ impl Ch2Trigger {
}
}
-#[derive(Debug, Copy, Clone, Eq, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Alignment {
- Left,
- Right,
-}
-
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Value {
+ // 8 bit value
Bit8(u8),
- Bit12(u16, Alignment),
+ // 12 bit value stored in a u16, left-aligned
+ Bit12Left(u16),
+ // 12 bit value stored in a u16, right-aligned
+ Bit12Right(u16),
}
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum ValueArray<'a> {
+ // 8 bit values
Bit8(&'a [u8]),
+ // 12 bit value stored in a u16, left-aligned
Bit12Left(&'a [u16]),
+ // 12 bit values stored in a u16, right-aligned
Bit12Right(&'a [u16]),
}
@@ -225,8 +225,8 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
self.check_channel_exists(ch)?;
match value {
Value::Bit8(v) => T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v)),
- Value::Bit12(v, Alignment::Left) => T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v)),
- Value::Bit12(v, Alignment::Right) => T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v)),
+ Value::Bit12Left(v) => T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v)),
+ Value::Bit12Right(v) => T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v)),
}
Ok(())
}
From 88052480b14b8dd38e7c4ba179b7035390f59618 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Mon, 19 Jun 2023 13:50:17 +0200
Subject: [PATCH 07/48] fix typo, minor cleanup
---
embassy-stm32/src/dac/mod.rs | 13 +++++++------
embassy-stm32/src/dma/bdma.rs | 7 +++----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 0fbf67673..704b77b37 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -275,42 +275,43 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
});
let tx_request = self.txdma.request();
+ let channel = &mut self.txdma;
// Initiate the correct type of DMA transfer depending on what data is passed
let tx_f = match data_ch1 {
ValueArray::Bit8(buf) => unsafe {
Transfer::new_write(
- &mut self.txdma,
+ channel,
tx_request,
buf,
T::regs().dhr8r(CHANNEL).as_ptr() as *mut u8,
TransferOptions {
circular,
- halt_transfer_ir: false,
+ half_transfer_ir: false,
},
)
},
ValueArray::Bit12Left(buf) => unsafe {
Transfer::new_write(
- &mut self.txdma,
+ channel,
tx_request,
buf,
T::regs().dhr12l(CHANNEL).as_ptr() as *mut u16,
TransferOptions {
circular,
- halt_transfer_ir: false,
+ half_transfer_ir: false,
},
)
},
ValueArray::Bit12Right(buf) => unsafe {
Transfer::new_write(
- &mut self.txdma,
+ channel,
tx_request,
buf,
T::regs().dhr12r(CHANNEL).as_ptr() as *mut u16,
TransferOptions {
circular,
- halt_transfer_ir: false,
+ half_transfer_ir: false,
},
)
},
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index 3d315e20b..0ad20579a 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -1,7 +1,6 @@
#![macro_use]
use core::future::Future;
-use core::option;
use core::pin::Pin;
use core::sync::atomic::{fence, Ordering};
use core::task::{Context, Poll, Waker};
@@ -24,14 +23,14 @@ use crate::pac::bdma::{regs, vals};
#[non_exhaustive]
pub struct TransferOptions {
pub circular: bool,
- pub halt_transfer_ir: bool,
+ pub half_transfer_ir: bool,
}
impl Default for TransferOptions {
fn default() -> Self {
Self {
circular: false,
- halt_transfer_ir: false,
+ half_transfer_ir: false,
}
}
}
@@ -291,7 +290,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
w.set_dir(dir.into());
w.set_teie(true);
w.set_tcie(true);
- w.set_htie(options.halt_transfer_ir);
+ w.set_htie(options.half_transfer_ir);
if options.circular {
w.set_circ(vals::Circ::ENABLED);
debug!("Setting circular mode");
From 56ab6d9f143ecc3041ac9726e621eedea729ca4d Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Mon, 19 Jun 2023 13:54:22 +0200
Subject: [PATCH 08/48] remove write_X variants
---
embassy-stm32/src/dac/mod.rs | 26 +++-----------------------
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 704b77b37..f02adeed9 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -86,6 +86,7 @@ impl Ch2Trigger {
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Single 8 or 12 bit value that can be output by the DAC
pub enum Value {
// 8 bit value
Bit8(u8),
@@ -97,6 +98,7 @@ pub enum Value {
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Array variant of [`Value`]
pub enum ValueArray<'a> {
// 8 bit values
Bit8(&'a [u8]),
@@ -239,29 +241,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
/// ## Current limitations
/// - Only CH1 Supported
///
- /// TODO: Allow an array of Value instead of only u16, right-aligned
- pub async fn write_8bit(&mut self, data_ch1: &[u8], circular: bool) -> Result<(), Error>
- where
- Tx: Dma,
- {
- self.write_inner(ValueArray::Bit8(data_ch1), circular).await
- }
-
- pub async fn write_12bit_right_aligned(&mut self, data_ch1: &[u16], circular: bool) -> Result<(), Error>
- where
- Tx: Dma,
- {
- self.write_inner(ValueArray::Bit12Right(data_ch1), circular).await
- }
-
- pub async fn write_12bit_left_aligned(&mut self, data_ch1: &[u16], circular: bool) -> Result<(), Error>
- where
- Tx: Dma,
- {
- self.write_inner(ValueArray::Bit12Left(data_ch1), circular).await
- }
-
- async fn write_inner(&mut self, data_ch1: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ pub async fn write(&mut self, data_ch1: ValueArray<'_>, circular: bool) -> Result<(), Error>
where
Tx: Dma,
{
From 8d0095c61808b88ad95349c7f24e91797d93dc83 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Thu, 22 Jun 2023 10:43:45 +0200
Subject: [PATCH 09/48] add option to enable/disable complete transfer
interrupt
---
embassy-stm32/src/dma/bdma.rs | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index 162ca9adb..32b75bb68 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -22,8 +22,12 @@ use crate::pac::bdma::{regs, vals};
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive]
pub struct TransferOptions {
+ /// Enable circular DMA
pub circular: bool,
+ /// Enable half transfer interrupt
pub half_transfer_ir: bool,
+ /// Enable transfer complete interrupt
+ pub complete_transfer_ir: bool,
}
impl Default for TransferOptions {
@@ -31,6 +35,7 @@ impl Default for TransferOptions {
Self {
circular: false,
half_transfer_ir: false,
+ complete_transfer_ir: false,
}
}
}
@@ -289,7 +294,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
}
w.set_dir(dir.into());
w.set_teie(true);
- w.set_tcie(true);
+ w.set_tcie(options.complete_transfer_ir);
w.set_htie(options.half_transfer_ir);
if options.circular {
w.set_circ(vals::Circ::ENABLED);
From 78736328a042e7c7f6565ed44ac301be22953f7a Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Thu, 22 Jun 2023 10:44:08 +0200
Subject: [PATCH 10/48] update docs and update to new dma interface
---
embassy-stm32/src/dac/mod.rs | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index f02adeed9..42646d20d 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -115,6 +115,7 @@ pub struct Dac<'d, T: Instance, Tx> {
}
impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
+ /// Create a new instance with one channel
pub fn new_1ch(
peri: impl Peripheral + 'd,
txdma: impl Peripheral
+ 'd,
@@ -124,6 +125,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
Self::new_inner(peri, 1, txdma)
}
+ /// Create a new instance with two channels
pub fn new_2ch(
peri: impl Peripheral
+ 'd,
txdma: impl Peripheral
+ 'd,
@@ -134,6 +136,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
Self::new_inner(peri, 2, txdma)
}
+ /// Perform initialisation steps for the DAC
fn new_inner(peri: PeripheralRef<'d, T>, channels: u8, txdma: impl Peripheral
+ 'd) -> Self {
into_ref!(txdma);
T::enable();
@@ -178,15 +181,17 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
Ok(())
}
+ /// Enable the DAC channel `ch`
pub fn enable_channel(&mut self, ch: Channel) -> Result<(), Error> {
self.set_channel_enable(ch, true)
}
+ /// Disable the DAC channel `ch`
pub fn disable_channel(&mut self, ch: Channel) -> Result<(), Error> {
self.set_channel_enable(ch, false)
}
- /// Performs all register accesses necessary to select a new trigger for CH1
+ /// Select a new trigger for CH1 (disables the channel)
pub fn select_trigger_ch1(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
self.check_channel_exists(Channel::Ch1)?;
unwrap!(self.disable_channel(Channel::Ch1));
@@ -196,7 +201,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
Ok(())
}
- /// Performs all register accesses necessary to select a new trigger for CH2
+ /// Select a new trigger for CH2 (disables the channel)
pub fn select_trigger_ch2(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
self.check_channel_exists(Channel::Ch2)?;
unwrap!(self.disable_channel(Channel::Ch2));
@@ -206,7 +211,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
Ok(())
}
- /// Perform a software trigger on a given channel
+ /// Perform a software trigger on `ch`
pub fn trigger(&mut self, ch: Channel) -> Result<(), Error> {
self.check_channel_exists(ch)?;
T::regs().swtrigr().write(|reg| {
@@ -223,6 +228,9 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
});
}
+ /// Set a value to be output by the DAC on trigger.
+ ///
+ /// The `value` is written to the corresponding "data holding register"
pub fn set(&mut self, ch: Channel, value: Value) -> Result<(), Error> {
self.check_channel_exists(ch)?;
match value {
@@ -237,6 +245,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
///
/// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
/// This will configure a circular DMA transfer that periodically outputs the `data`.
+ /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
///
/// ## Current limitations
/// - Only CH1 Supported
@@ -255,7 +264,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
});
let tx_request = self.txdma.request();
- let channel = &mut self.txdma;
+ let channel = &self.txdma;
// Initiate the correct type of DMA transfer depending on what data is passed
let tx_f = match data_ch1 {
@@ -268,6 +277,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
TransferOptions {
circular,
half_transfer_ir: false,
+ complete_transfer_ir: !circular,
},
)
},
@@ -280,6 +290,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
TransferOptions {
circular,
half_transfer_ir: false,
+ complete_transfer_ir: !circular,
},
)
},
@@ -292,6 +303,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
TransferOptions {
circular,
half_transfer_ir: false,
+ complete_transfer_ir: !circular,
},
)
},
From ea04a0277bb19719188e904a86e28c34f9801c96 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Fri, 23 Jun 2023 12:14:26 +0200
Subject: [PATCH 11/48] change dma complete transfer IR default to true
---
embassy-stm32/src/dma/bdma.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index 32b75bb68..5a87888b7 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -35,7 +35,7 @@ impl Default for TransferOptions {
Self {
circular: false,
half_transfer_ir: false,
- complete_transfer_ir: false,
+ complete_transfer_ir: true,
}
}
}
From 915f79c974ace037e914397b42eb9d2448bd5ca3 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Fri, 23 Jun 2023 12:14:40 +0200
Subject: [PATCH 12/48] allow independent use of ch1 and ch2 on dac
---
embassy-stm32/src/dac/mod.rs | 152 +++++++++++++++++++++++------------
1 file changed, 101 insertions(+), 51 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 42646d20d..5b39758bf 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -22,7 +22,7 @@ pub enum Channel {
}
impl Channel {
- fn index(&self) -> usize {
+ const fn index(&self) -> usize {
match self {
Channel::Ch1 => 0,
Channel::Ch2 => 1,
@@ -109,72 +109,100 @@ pub enum ValueArray<'a> {
}
pub struct Dac<'d, T: Instance, Tx> {
- channels: u8,
+ ch1: bool,
+ ch2: bool,
txdma: PeripheralRef<'d, Tx>,
_peri: PeripheralRef<'d, T>,
}
impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
- /// Create a new instance with one channel
- pub fn new_1ch(
+ pub fn new_ch1(
peri: impl Peripheral
+ 'd,
txdma: impl Peripheral
+ 'd,
_ch1: impl Peripheral
> + 'd,
) -> Self {
into_ref!(peri);
- Self::new_inner(peri, 1, txdma)
+ Self::new_inner(peri, true, false, txdma)
}
- /// Create a new instance with two channels
- pub fn new_2ch(
+ pub fn new_ch2(
+ peri: impl Peripheral
+ 'd,
+ txdma: impl Peripheral
+ 'd,
+ _ch2: impl Peripheral
> + 'd,
+ ) -> Self {
+ into_ref!(peri);
+ Self::new_inner(peri, false, true, txdma)
+ }
+
+ pub fn new_ch1_and_ch2(
peri: impl Peripheral
+ 'd,
txdma: impl Peripheral
+ 'd,
_ch1: impl Peripheral
> + 'd,
_ch2: impl Peripheral
> + 'd,
) -> Self {
into_ref!(peri);
- Self::new_inner(peri, 2, txdma)
+ Self::new_inner(peri, true, true, txdma)
}
/// Perform initialisation steps for the DAC
- fn new_inner(peri: PeripheralRef<'d, T>, channels: u8, txdma: impl Peripheral
+ 'd) -> Self {
+ fn new_inner(peri: PeripheralRef<'d, T>, ch1: bool, ch2: bool, txdma: impl Peripheral
+ 'd) -> Self {
into_ref!(txdma);
T::enable();
T::reset();
- T::regs().mcr().modify(|reg| {
- for ch in 0..channels {
- reg.set_mode(ch as usize, 0);
- reg.set_mode(ch as usize, 0);
- }
- });
-
- T::regs().cr().modify(|reg| {
- for ch in 0..channels {
- reg.set_en(ch as usize, true);
- reg.set_ten(ch as usize, true);
- }
- });
-
- Self {
- channels,
+ let mut dac = Self {
+ ch1,
+ ch2,
txdma,
_peri: peri,
+ };
+
+ // Configure each activated channel. All results can be `unwrap`ed since they
+ // will only error if the channel is not configured (i.e. ch1, ch2 are false)
+ if ch1 {
+ dac.set_channel_mode(Channel::Ch1, 0).unwrap();
+ dac.enable_channel(Channel::Ch1).unwrap();
+ dac.set_trigger_enable(Channel::Ch1, true).unwrap();
}
+ if ch2 {
+ dac.set_channel_mode(Channel::Ch2, 0).unwrap();
+ dac.enable_channel(Channel::Ch2).unwrap();
+ dac.set_trigger_enable(Channel::Ch2, true).unwrap();
+ }
+
+ dac
}
/// Check the channel is configured
- fn check_channel_exists(&self, ch: Channel) -> Result<(), Error> {
- if ch == Channel::Ch2 && self.channels < 2 {
+ fn check_channel_configured(&self, ch: Channel) -> Result<(), Error> {
+ if (ch == Channel::Ch1 && !self.ch1) || (ch == Channel::Ch2 && !self.ch2) {
Err(Error::UnconfiguredChannel)
} else {
Ok(())
}
}
- /// Set the enable register of the given channel
+ /// Enable trigger of the given channel
+ fn set_trigger_enable(&mut self, ch: Channel, on: bool) -> Result<(), Error> {
+ self.check_channel_configured(ch)?;
+ T::regs().cr().modify(|reg| {
+ reg.set_ten(ch.index(), on);
+ });
+ Ok(())
+ }
+
+ /// Set mode register of the given channel
+ fn set_channel_mode(&mut self, ch: Channel, val: u8) -> Result<(), Error> {
+ self.check_channel_configured(ch)?;
+ T::regs().mcr().modify(|reg| {
+ reg.set_mode(ch.index(), val);
+ });
+ Ok(())
+ }
+
+ /// Set enable register of the given channel
fn set_channel_enable(&mut self, ch: Channel, on: bool) -> Result<(), Error> {
- self.check_channel_exists(ch)?;
+ self.check_channel_configured(ch)?;
T::regs().cr().modify(|reg| {
reg.set_en(ch.index(), on);
});
@@ -193,7 +221,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
/// Select a new trigger for CH1 (disables the channel)
pub fn select_trigger_ch1(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
- self.check_channel_exists(Channel::Ch1)?;
+ self.check_channel_configured(Channel::Ch1)?;
unwrap!(self.disable_channel(Channel::Ch1));
T::regs().cr().modify(|reg| {
reg.set_tsel1(trigger.tsel());
@@ -203,7 +231,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
/// Select a new trigger for CH2 (disables the channel)
pub fn select_trigger_ch2(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
- self.check_channel_exists(Channel::Ch2)?;
+ self.check_channel_configured(Channel::Ch2)?;
unwrap!(self.disable_channel(Channel::Ch2));
T::regs().cr().modify(|reg| {
reg.set_tsel2(trigger.tsel());
@@ -213,7 +241,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
/// Perform a software trigger on `ch`
pub fn trigger(&mut self, ch: Channel) -> Result<(), Error> {
- self.check_channel_exists(ch)?;
+ self.check_channel_configured(ch)?;
T::regs().swtrigr().write(|reg| {
reg.set_swtrig(ch.index(), true);
});
@@ -232,7 +260,7 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
///
/// The `value` is written to the corresponding "data holding register"
pub fn set(&mut self, ch: Channel, value: Value) -> Result<(), Error> {
- self.check_channel_exists(ch)?;
+ self.check_channel_configured(ch)?;
match value {
Value::Bit8(v) => T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v)),
Value::Bit12Left(v) => T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v)),
@@ -241,39 +269,61 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
Ok(())
}
- /// Write `data` to the DAC via DMA.
+ /// Write `data` to the DAC CH1 via DMA.
///
/// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
/// This will configure a circular DMA transfer that periodically outputs the `data`.
/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
///
- /// ## Current limitations
- /// - Only CH1 Supported
- ///
- pub async fn write(&mut self, data_ch1: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ /// **Important:** Channel 1 has to be configured for the DAC instance!
+ pub async fn write_ch1(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
where
Tx: Dma,
{
- // TODO: Make this a parameter or get it from the struct or so...
- const CHANNEL: usize = 0;
+ self.check_channel_configured(Channel::Ch1)?;
+ self.write_inner(data, circular, Channel::Ch1).await
+ }
+
+ /// Write `data` to the DAC CH2 via DMA.
+ ///
+ /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
+ /// This will configure a circular DMA transfer that periodically outputs the `data`.
+ /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
+ ///
+ /// **Important:** Channel 2 has to be configured for the DAC instance!
+ pub async fn write_ch2(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ where
+ Tx: Dma,
+ {
+ self.check_channel_configured(Channel::Ch2)?;
+ self.write_inner(data, circular, Channel::Ch2).await
+ }
+
+ /// Performs the dma write for the given channel.
+ /// TODO: Should self be &mut?
+ async fn write_inner(&self, data_ch1: ValueArray<'_>, circular: bool, channel: Channel) -> Result<(), Error>
+ where
+ Tx: Dma,
+ {
+ let channel = channel.index();
// Enable DAC and DMA
T::regs().cr().modify(|w| {
- w.set_en(CHANNEL, true);
- w.set_dmaen(CHANNEL, true);
+ w.set_en(channel, true);
+ w.set_dmaen(channel, true);
});
let tx_request = self.txdma.request();
- let channel = &self.txdma;
+ let dma_channel = &self.txdma;
// Initiate the correct type of DMA transfer depending on what data is passed
let tx_f = match data_ch1 {
ValueArray::Bit8(buf) => unsafe {
Transfer::new_write(
- channel,
+ dma_channel,
tx_request,
buf,
- T::regs().dhr8r(CHANNEL).as_ptr() as *mut u8,
+ T::regs().dhr8r(channel).as_ptr() as *mut u8,
TransferOptions {
circular,
half_transfer_ir: false,
@@ -283,10 +333,10 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
},
ValueArray::Bit12Left(buf) => unsafe {
Transfer::new_write(
- channel,
+ dma_channel,
tx_request,
buf,
- T::regs().dhr12l(CHANNEL).as_ptr() as *mut u16,
+ T::regs().dhr12l(channel).as_ptr() as *mut u16,
TransferOptions {
circular,
half_transfer_ir: false,
@@ -296,10 +346,10 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
},
ValueArray::Bit12Right(buf) => unsafe {
Transfer::new_write(
- channel,
+ dma_channel,
tx_request,
buf,
- T::regs().dhr12r(CHANNEL).as_ptr() as *mut u16,
+ T::regs().dhr12r(channel).as_ptr() as *mut u16,
TransferOptions {
circular,
half_transfer_ir: false,
@@ -315,9 +365,9 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
// TODO: Do we need to check any status registers here?
T::regs().cr().modify(|w| {
// Disable the DAC peripheral
- w.set_en(CHANNEL, false);
+ w.set_en(channel, false);
// Disable the DMA. TODO: Is this necessary?
- w.set_dmaen(CHANNEL, false);
+ w.set_dmaen(channel, false);
});
Ok(())
From 388d3e273d3d003e6a058b4bad9e2517dd33d626 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Sat, 24 Jun 2023 13:10:59 +0200
Subject: [PATCH 13/48] first attempt at fixing the 2nd channel problem
---
embassy-stm32/src/dac/mod.rs | 386 +++++++++++++++++++++--------------
1 file changed, 234 insertions(+), 152 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 5b39758bf..e87292b86 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -1,5 +1,7 @@
#![macro_use]
+use core::marker::PhantomData;
+
use embassy_hal_common::{into_ref, PeripheralRef};
use crate::dma::{Transfer, TransferOptions};
@@ -108,166 +110,108 @@ pub enum ValueArray<'a> {
Bit12Right(&'a [u16]),
}
-pub struct Dac<'d, T: Instance, Tx> {
- ch1: bool,
- ch2: bool,
- txdma: PeripheralRef<'d, Tx>,
- _peri: PeripheralRef<'d, T>,
-}
-
-impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
- pub fn new_ch1(
- peri: impl Peripheral + 'd,
- txdma: impl Peripheral
+ 'd,
- _ch1: impl Peripheral
> + 'd,
- ) -> Self {
- into_ref!(peri);
- Self::new_inner(peri, true, false, txdma)
- }
-
- pub fn new_ch2(
- peri: impl Peripheral
+ 'd,
- txdma: impl Peripheral
+ 'd,
- _ch2: impl Peripheral
> + 'd,
- ) -> Self {
- into_ref!(peri);
- Self::new_inner(peri, false, true, txdma)
- }
-
- pub fn new_ch1_and_ch2(
- peri: impl Peripheral
+ 'd,
- txdma: impl Peripheral
+ 'd,
- _ch1: impl Peripheral
> + 'd,
- _ch2: impl Peripheral
> + 'd,
- ) -> Self {
- into_ref!(peri);
- Self::new_inner(peri, true, true, txdma)
- }
-
- /// Perform initialisation steps for the DAC
- fn new_inner(peri: PeripheralRef<'d, T>, ch1: bool, ch2: bool, txdma: impl Peripheral
+ 'd) -> Self {
- into_ref!(txdma);
- T::enable();
- T::reset();
-
- let mut dac = Self {
- ch1,
- ch2,
- txdma,
- _peri: peri,
- };
-
- // Configure each activated channel. All results can be `unwrap`ed since they
- // will only error if the channel is not configured (i.e. ch1, ch2 are false)
- if ch1 {
- dac.set_channel_mode(Channel::Ch1, 0).unwrap();
- dac.enable_channel(Channel::Ch1).unwrap();
- dac.set_trigger_enable(Channel::Ch1, true).unwrap();
- }
- if ch2 {
- dac.set_channel_mode(Channel::Ch2, 0).unwrap();
- dac.enable_channel(Channel::Ch2).unwrap();
- dac.set_trigger_enable(Channel::Ch2, true).unwrap();
- }
-
- dac
- }
-
- /// Check the channel is configured
- fn check_channel_configured(&self, ch: Channel) -> Result<(), Error> {
- if (ch == Channel::Ch1 && !self.ch1) || (ch == Channel::Ch2 && !self.ch2) {
- Err(Error::UnconfiguredChannel)
- } else {
- Ok(())
- }
- }
+pub trait DacChannel {
+ const CHANNEL: Channel;
/// Enable trigger of the given channel
- fn set_trigger_enable(&mut self, ch: Channel, on: bool) -> Result<(), Error> {
- self.check_channel_configured(ch)?;
+ fn set_trigger_enable(&mut self, on: bool) -> Result<(), Error> {
T::regs().cr().modify(|reg| {
- reg.set_ten(ch.index(), on);
+ reg.set_ten(Self::CHANNEL.index(), on);
});
Ok(())
}
/// Set mode register of the given channel
- fn set_channel_mode(&mut self, ch: Channel, val: u8) -> Result<(), Error> {
- self.check_channel_configured(ch)?;
+ fn set_channel_mode(&mut self, val: u8) -> Result<(), Error> {
T::regs().mcr().modify(|reg| {
- reg.set_mode(ch.index(), val);
+ reg.set_mode(Self::CHANNEL.index(), val);
});
Ok(())
}
/// Set enable register of the given channel
- fn set_channel_enable(&mut self, ch: Channel, on: bool) -> Result<(), Error> {
- self.check_channel_configured(ch)?;
+ fn set_channel_enable(&mut self, on: bool) -> Result<(), Error> {
T::regs().cr().modify(|reg| {
- reg.set_en(ch.index(), on);
+ reg.set_en(Self::CHANNEL.index(), on);
});
Ok(())
}
/// Enable the DAC channel `ch`
- pub fn enable_channel(&mut self, ch: Channel) -> Result<(), Error> {
- self.set_channel_enable(ch, true)
+ fn enable_channel(&mut self) -> Result<(), Error> {
+ self.set_channel_enable(true)
}
/// Disable the DAC channel `ch`
- pub fn disable_channel(&mut self, ch: Channel) -> Result<(), Error> {
- self.set_channel_enable(ch, false)
- }
-
- /// Select a new trigger for CH1 (disables the channel)
- pub fn select_trigger_ch1(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
- self.check_channel_configured(Channel::Ch1)?;
- unwrap!(self.disable_channel(Channel::Ch1));
- T::regs().cr().modify(|reg| {
- reg.set_tsel1(trigger.tsel());
- });
- Ok(())
- }
-
- /// Select a new trigger for CH2 (disables the channel)
- pub fn select_trigger_ch2(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
- self.check_channel_configured(Channel::Ch2)?;
- unwrap!(self.disable_channel(Channel::Ch2));
- T::regs().cr().modify(|reg| {
- reg.set_tsel2(trigger.tsel());
- });
- Ok(())
+ fn disable_channel(&mut self) -> Result<(), Error> {
+ self.set_channel_enable(false)
}
/// Perform a software trigger on `ch`
- pub fn trigger(&mut self, ch: Channel) -> Result<(), Error> {
- self.check_channel_configured(ch)?;
+ fn trigger(&mut self) -> Result<(), Error> {
T::regs().swtrigr().write(|reg| {
- reg.set_swtrig(ch.index(), true);
+ reg.set_swtrig(Self::CHANNEL.index(), true);
});
Ok(())
}
- /// Perform a software trigger on all channels
- pub fn trigger_all(&mut self) {
- T::regs().swtrigr().write(|reg| {
- reg.set_swtrig(Channel::Ch1.index(), true);
- reg.set_swtrig(Channel::Ch2.index(), true);
- });
- }
-
/// Set a value to be output by the DAC on trigger.
///
/// The `value` is written to the corresponding "data holding register"
- pub fn set(&mut self, ch: Channel, value: Value) -> Result<(), Error> {
- self.check_channel_configured(ch)?;
+ fn set(&mut self, value: Value) -> Result<(), Error> {
match value {
- Value::Bit8(v) => T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v)),
- Value::Bit12Left(v) => T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v)),
- Value::Bit12Right(v) => T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v)),
+ Value::Bit8(v) => T::regs().dhr8r(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
+ Value::Bit12Left(v) => T::regs().dhr12l(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
+ Value::Bit12Right(v) => T::regs().dhr12r(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
}
Ok(())
}
+}
+
+pub struct Dac<'d, T: Instance, Tx> {
+ ch1: DacCh1<'d, T, Tx>,
+ ch2: DacCh2<'d, T, Tx>,
+}
+
+pub struct DacCh1<'d, T: Instance, Tx> {
+ _peri: PeripheralRef<'d, T>,
+ dma: PeripheralRef<'d, Tx>,
+}
+
+pub struct DacCh2<'d, T: Instance, Tx> {
+ phantom: PhantomData<&'d mut T>,
+ dma: PeripheralRef<'d, Tx>,
+}
+
+impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
+ /// Perform initialisation steps for the DAC
+ pub fn new(
+ peri: impl Peripheral + 'd,
+ dma: impl Peripheral
+ 'd,
+ _pin: impl Peripheral
> + 'd,
+ ) -> Self {
+ into_ref!(peri, dma);
+ T::enable();
+ T::reset();
+
+ let mut dac = Self { _peri: peri, dma };
+
+ // Configure each activated channel. All results can be `unwrap`ed since they
+ // will only error if the channel is not configured (i.e. ch1, ch2 are false)
+ dac.set_channel_mode(0).unwrap();
+ dac.enable_channel().unwrap();
+ dac.set_trigger_enable(true).unwrap();
+
+ dac
+ }
+ /// Select a new trigger for CH1 (disables the channel)
+ pub fn select_trigger(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
+ unwrap!(self.disable_channel());
+ T::regs().cr().modify(|reg| {
+ reg.set_tsel1(trigger.tsel());
+ });
+ Ok(())
+ }
/// Write `data` to the DAC CH1 via DMA.
///
@@ -276,36 +220,12 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
///
/// **Important:** Channel 1 has to be configured for the DAC instance!
- pub async fn write_ch1(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
where
Tx: Dma,
{
- self.check_channel_configured(Channel::Ch1)?;
- self.write_inner(data, circular, Channel::Ch1).await
- }
-
- /// Write `data` to the DAC CH2 via DMA.
- ///
- /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
- /// This will configure a circular DMA transfer that periodically outputs the `data`.
- /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
- ///
- /// **Important:** Channel 2 has to be configured for the DAC instance!
- pub async fn write_ch2(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
- where
- Tx: Dma,
- {
- self.check_channel_configured(Channel::Ch2)?;
- self.write_inner(data, circular, Channel::Ch2).await
- }
-
- /// Performs the dma write for the given channel.
- /// TODO: Should self be &mut?
- async fn write_inner(&self, data_ch1: ValueArray<'_>, circular: bool, channel: Channel) -> Result<(), Error>
- where
- Tx: Dma,
- {
- let channel = channel.index();
+ let channel = Channel::Ch1.index();
+ debug!("Writing to channel {}", channel);
// Enable DAC and DMA
T::regs().cr().modify(|w| {
@@ -313,11 +233,11 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
w.set_dmaen(channel, true);
});
- let tx_request = self.txdma.request();
- let dma_channel = &self.txdma;
+ let tx_request = self.dma.request();
+ let dma_channel = &self.dma;
// Initiate the correct type of DMA transfer depending on what data is passed
- let tx_f = match data_ch1 {
+ let tx_f = match data {
ValueArray::Bit8(buf) => unsafe {
Transfer::new_write(
dma_channel,
@@ -374,6 +294,168 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
}
}
+impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
+ /// Perform initialisation steps for the DAC
+ pub fn new_ch2(
+ peri: impl Peripheral + 'd,
+ dma: impl Peripheral
+ 'd,
+ _pin: impl Peripheral
> + 'd,
+ ) -> Self {
+ into_ref!(peri, dma);
+ T::enable();
+ T::reset();
+
+ let mut dac = Self {
+ phantom: PhantomData,
+ dma,
+ };
+
+ // Configure each activated channel. All results can be `unwrap`ed since they
+ // will only error if the channel is not configured (i.e. ch1, ch2 are false)
+ dac.set_channel_mode(0).unwrap();
+ dac.enable_channel().unwrap();
+ dac.set_trigger_enable(true).unwrap();
+
+ dac
+ }
+
+ /// Select a new trigger for CH1 (disables the channel)
+ pub fn select_trigger(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
+ unwrap!(self.disable_channel());
+ T::regs().cr().modify(|reg| {
+ reg.set_tsel2(trigger.tsel());
+ });
+ Ok(())
+ }
+
+ /// Write `data` to the DAC CH1 via DMA.
+ ///
+ /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
+ /// This will configure a circular DMA transfer that periodically outputs the `data`.
+ /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
+ ///
+ /// **Important:** Channel 1 has to be configured for the DAC instance!
+ async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ where
+ Tx: Dma,
+ {
+ let channel = Channel::Ch2.index();
+ debug!("Writing to channel {}", channel);
+
+ // Enable DAC and DMA
+ T::regs().cr().modify(|w| {
+ w.set_en(channel, true);
+ w.set_dmaen(channel, true);
+ });
+
+ let tx_request = self.dma.request();
+ let dma_channel = &self.dma;
+
+ // Initiate the correct type of DMA transfer depending on what data is passed
+ let tx_f = match data {
+ ValueArray::Bit8(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr8r(channel).as_ptr() as *mut u8,
+ TransferOptions {
+ circular,
+ half_transfer_ir: false,
+ complete_transfer_ir: !circular,
+ },
+ )
+ },
+ ValueArray::Bit12Left(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr12l(channel).as_ptr() as *mut u16,
+ TransferOptions {
+ circular,
+ half_transfer_ir: false,
+ complete_transfer_ir: !circular,
+ },
+ )
+ },
+ ValueArray::Bit12Right(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr12r(channel).as_ptr() as *mut u16,
+ TransferOptions {
+ circular,
+ half_transfer_ir: false,
+ complete_transfer_ir: !circular,
+ },
+ )
+ },
+ };
+
+ tx_f.await;
+
+ // finish dma
+ // TODO: Do we need to check any status registers here?
+ T::regs().cr().modify(|w| {
+ // Disable the DAC peripheral
+ w.set_en(channel, false);
+ // Disable the DMA. TODO: Is this necessary?
+ w.set_dmaen(channel, false);
+ });
+
+ Ok(())
+ }
+}
+
+impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
+ pub fn new(
+ peri: impl Peripheral + 'd,
+ dma_ch1: impl Peripheral
+ 'd,
+ dma_ch2: impl Peripheral
+ 'd,
+ _pin_ch1: impl Peripheral
> + 'd,
+ _pin_ch2: impl Peripheral
> + 'd,
+ ) -> Self {
+ into_ref!(peri, dma_ch1, dma_ch2);
+ T::enable();
+ T::reset();
+
+ let mut dac_ch1 = DacCh1 {
+ _peri: peri,
+ dma: dma_ch1,
+ };
+
+ let mut dac_ch2 = DacCh2 {
+ phantom: PhantomData,
+ dma: dma_ch2,
+ };
+
+ // Configure each activated channel. All results can be `unwrap`ed since they
+ // will only error if the channel is not configured (i.e. ch1, ch2 are false)
+ dac_ch1.set_channel_mode(0).unwrap();
+ dac_ch1.enable_channel().unwrap();
+ dac_ch1.set_trigger_enable(true).unwrap();
+
+ dac_ch1.set_channel_mode(0).unwrap();
+ dac_ch1.enable_channel().unwrap();
+ dac_ch1.set_trigger_enable(true).unwrap();
+
+ Self {
+ ch1: dac_ch1,
+ ch2: dac_ch2,
+ }
+ }
+}
+
+impl<'d, T: Instance, Tx> DacChannel for DacCh1<'d, T, Tx> {
+ const CHANNEL: Channel = Channel::Ch1;
+}
+
+impl<'d, T: Instance, Tx> DacChannel for DacCh2<'d, T, Tx> {
+ const CHANNEL: Channel = Channel::Ch2;
+}
+
pub(crate) mod sealed {
pub trait Instance {
fn regs() -> &'static crate::pac::dac::Dac;
From df944edeef738590f481d35ee9e2a1afb09601fa Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Sun, 25 Jun 2023 10:53:35 +0200
Subject: [PATCH 14/48] fix minor issues with splitting channels etc
---
embassy-stm32/src/dac/mod.rs | 46 ++++++++++++++++++++++++++----------
1 file changed, 33 insertions(+), 13 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index e87292b86..3dcd6b771 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -168,9 +168,9 @@ pub trait DacChannel {
}
}
-pub struct Dac<'d, T: Instance, Tx> {
- ch1: DacCh1<'d, T, Tx>,
- ch2: DacCh2<'d, T, Tx>,
+pub struct Dac<'d, T: Instance, TxCh1, TxCh2> {
+ ch1: DacCh1<'d, T, TxCh1>,
+ ch2: DacCh2<'d, T, TxCh2>,
}
pub struct DacCh1<'d, T: Instance, Tx> {
@@ -220,7 +220,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
///
/// **Important:** Channel 1 has to be configured for the DAC instance!
- async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
where
Tx: Dma,
{
@@ -297,11 +297,11 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
/// Perform initialisation steps for the DAC
pub fn new_ch2(
- peri: impl Peripheral + 'd,
+ _peri: impl Peripheral
+ 'd,
dma: impl Peripheral
+ 'd,
_pin: impl Peripheral
> + 'd,
) -> Self {
- into_ref!(peri, dma);
+ into_ref!(_peri, dma);
T::enable();
T::reset();
@@ -335,7 +335,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
///
/// **Important:** Channel 1 has to be configured for the DAC instance!
- async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
where
Tx: Dma,
{
@@ -409,11 +409,11 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
}
}
-impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
+impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
pub fn new(
peri: impl Peripheral + 'd,
- dma_ch1: impl Peripheral
+ 'd,
- dma_ch2: impl Peripheral
+ 'd,
+ dma_ch1: impl Peripheral
+ 'd,
+ dma_ch2: impl Peripheral
+ 'd,
_pin_ch1: impl Peripheral
> + 'd,
_pin_ch2: impl Peripheral
> + 'd,
) -> Self {
@@ -437,15 +437,35 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
dac_ch1.enable_channel().unwrap();
dac_ch1.set_trigger_enable(true).unwrap();
- dac_ch1.set_channel_mode(0).unwrap();
- dac_ch1.enable_channel().unwrap();
- dac_ch1.set_trigger_enable(true).unwrap();
+ dac_ch2.set_channel_mode(0).unwrap();
+ dac_ch2.enable_channel().unwrap();
+ dac_ch2.set_trigger_enable(true).unwrap();
Self {
ch1: dac_ch1,
ch2: dac_ch2,
}
}
+
+ pub fn split(self) -> (DacCh1<'d, T, TxCh1>, DacCh2<'d, T, TxCh2>) {
+ (self.ch1, self.ch2)
+ }
+
+ pub fn ch1_mut(&mut self) -> &mut DacCh1<'d, T, TxCh1> {
+ &mut self.ch1
+ }
+
+ pub fn ch2_mut(&mut self) -> &mut DacCh2<'d, T, TxCh2> {
+ &mut self.ch2
+ }
+
+ pub fn ch1(&mut self) -> &DacCh1<'d, T, TxCh1> {
+ &self.ch1
+ }
+
+ pub fn ch2(&mut self) -> &DacCh2<'d, T, TxCh2> {
+ &self.ch2
+ }
}
impl<'d, T: Instance, Tx> DacChannel for DacCh1<'d, T, Tx> {
From 8cafaa1f3c9b75e8dba30a7f37f60d9fee6e65e2 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Sun, 25 Jun 2023 11:54:25 +0200
Subject: [PATCH 15/48] add docs, cleanup
---
embassy-stm32/src/dac/mod.rs | 322 +++++++++++++++++------------------
1 file changed, 155 insertions(+), 167 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 3dcd6b771..d95674ff0 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -1,5 +1,6 @@
#![macro_use]
+//! Provide access to the STM32 digital-to-analog converter (DAC).
use core::marker::PhantomData;
use embassy_hal_common::{into_ref, PeripheralRef};
@@ -11,6 +12,7 @@ use crate::{peripherals, Peripheral};
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Curstom Errors
pub enum Error {
UnconfiguredChannel,
InvalidValue,
@@ -18,6 +20,7 @@ pub enum Error {
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// DAC Channels
pub enum Channel {
Ch1,
Ch2,
@@ -34,6 +37,7 @@ impl Channel {
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Trigger sources for CH1
pub enum Ch1Trigger {
Tim6,
Tim3,
@@ -60,6 +64,7 @@ impl Ch1Trigger {
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Trigger sources for CH2
pub enum Ch2Trigger {
Tim6,
Tim8,
@@ -109,7 +114,7 @@ pub enum ValueArray<'a> {
// 12 bit values stored in a u16, right-aligned
Bit12Right(&'a [u16]),
}
-
+/// Provide common functions for DAC channels
pub trait DacChannel {
const CHANNEL: Channel;
@@ -157,7 +162,7 @@ pub trait DacChannel {
/// Set a value to be output by the DAC on trigger.
///
- /// The `value` is written to the corresponding "data holding register"
+ /// The `value` is written to the corresponding "data holding register".
fn set(&mut self, value: Value) -> Result<(), Error> {
match value {
Value::Bit8(v) => T::regs().dhr8r(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
@@ -166,25 +171,51 @@ pub trait DacChannel {
}
Ok(())
}
+
+ /// Write `data` to the DAC channel via DMA.
+ ///
+ /// `circular` sets the DMA to circular mode.
+ async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ where
+ Tx: Dma;
}
+/// Hold two DAC channels
+///
+/// Note: This consumes the DAC `Instance` only once, allowing to get both channels simultaneously.
+///
+/// # Example for obtaining both DAC channels
+///
+/// ```no_run
+/// // DMA channels and pins may need to be changed for your controller
+/// let (dac_ch1, dac_ch2) =
+/// embassy_stm32::dac::Dac::new(p.DAC1, p.DMA1_CH3, p.DMA1_CH4, p.PA4, p.PA5).split();
+/// ```
pub struct Dac<'d, T: Instance, TxCh1, TxCh2> {
ch1: DacCh1<'d, T, TxCh1>,
ch2: DacCh2<'d, T, TxCh2>,
}
+/// DAC CH1
+///
+/// Note: This consumes the DAC `Instance`. Use [`Dac::new`] to get both channels simultaneously.
pub struct DacCh1<'d, T: Instance, Tx> {
+ /// To consume T
_peri: PeripheralRef<'d, T>,
dma: PeripheralRef<'d, Tx>,
}
+/// DAC CH2
+///
+/// Note: This consumes the DAC `Instance`. Use [`Dac::new`] to get both channels simultaneously.
pub struct DacCh2<'d, T: Instance, Tx> {
+ /// Instead of PeripheralRef to consume T
phantom: PhantomData<&'d mut T>,
dma: PeripheralRef<'d, Tx>,
}
impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
- /// Perform initialisation steps for the DAC
+ /// Obtain DAC CH1
pub fn new(
peri: impl Peripheral + 'd,
dma: impl Peripheral
+ 'd,
@@ -204,7 +235,8 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
dac
}
- /// Select a new trigger for CH1 (disables the channel)
+
+ /// Select a new trigger for this channel
pub fn select_trigger(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
unwrap!(self.disable_channel());
T::regs().cr().modify(|reg| {
@@ -212,91 +244,11 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
});
Ok(())
}
-
- /// Write `data` to the DAC CH1 via DMA.
- ///
- /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
- /// This will configure a circular DMA transfer that periodically outputs the `data`.
- /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
- ///
- /// **Important:** Channel 1 has to be configured for the DAC instance!
- pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
- where
- Tx: Dma,
- {
- let channel = Channel::Ch1.index();
- debug!("Writing to channel {}", channel);
-
- // Enable DAC and DMA
- T::regs().cr().modify(|w| {
- w.set_en(channel, true);
- w.set_dmaen(channel, true);
- });
-
- let tx_request = self.dma.request();
- let dma_channel = &self.dma;
-
- // Initiate the correct type of DMA transfer depending on what data is passed
- let tx_f = match data {
- ValueArray::Bit8(buf) => unsafe {
- Transfer::new_write(
- dma_channel,
- tx_request,
- buf,
- T::regs().dhr8r(channel).as_ptr() as *mut u8,
- TransferOptions {
- circular,
- half_transfer_ir: false,
- complete_transfer_ir: !circular,
- },
- )
- },
- ValueArray::Bit12Left(buf) => unsafe {
- Transfer::new_write(
- dma_channel,
- tx_request,
- buf,
- T::regs().dhr12l(channel).as_ptr() as *mut u16,
- TransferOptions {
- circular,
- half_transfer_ir: false,
- complete_transfer_ir: !circular,
- },
- )
- },
- ValueArray::Bit12Right(buf) => unsafe {
- Transfer::new_write(
- dma_channel,
- tx_request,
- buf,
- T::regs().dhr12r(channel).as_ptr() as *mut u16,
- TransferOptions {
- circular,
- half_transfer_ir: false,
- complete_transfer_ir: !circular,
- },
- )
- },
- };
-
- tx_f.await;
-
- // finish dma
- // TODO: Do we need to check any status registers here?
- T::regs().cr().modify(|w| {
- // Disable the DAC peripheral
- w.set_en(channel, false);
- // Disable the DMA. TODO: Is this necessary?
- w.set_dmaen(channel, false);
- });
-
- Ok(())
- }
}
impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
- /// Perform initialisation steps for the DAC
- pub fn new_ch2(
+ /// Obtain DAC CH2
+ pub fn new(
_peri: impl Peripheral + 'd,
dma: impl Peripheral
+ 'd,
_pin: impl Peripheral
> + 'd,
@@ -319,7 +271,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
dac
}
- /// Select a new trigger for CH1 (disables the channel)
+ /// Select a new trigger for this channel
pub fn select_trigger(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
unwrap!(self.disable_channel());
T::regs().cr().modify(|reg| {
@@ -327,89 +279,12 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
});
Ok(())
}
-
- /// Write `data` to the DAC CH1 via DMA.
- ///
- /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
- /// This will configure a circular DMA transfer that periodically outputs the `data`.
- /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
- ///
- /// **Important:** Channel 1 has to be configured for the DAC instance!
- pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
- where
- Tx: Dma,
- {
- let channel = Channel::Ch2.index();
- debug!("Writing to channel {}", channel);
-
- // Enable DAC and DMA
- T::regs().cr().modify(|w| {
- w.set_en(channel, true);
- w.set_dmaen(channel, true);
- });
-
- let tx_request = self.dma.request();
- let dma_channel = &self.dma;
-
- // Initiate the correct type of DMA transfer depending on what data is passed
- let tx_f = match data {
- ValueArray::Bit8(buf) => unsafe {
- Transfer::new_write(
- dma_channel,
- tx_request,
- buf,
- T::regs().dhr8r(channel).as_ptr() as *mut u8,
- TransferOptions {
- circular,
- half_transfer_ir: false,
- complete_transfer_ir: !circular,
- },
- )
- },
- ValueArray::Bit12Left(buf) => unsafe {
- Transfer::new_write(
- dma_channel,
- tx_request,
- buf,
- T::regs().dhr12l(channel).as_ptr() as *mut u16,
- TransferOptions {
- circular,
- half_transfer_ir: false,
- complete_transfer_ir: !circular,
- },
- )
- },
- ValueArray::Bit12Right(buf) => unsafe {
- Transfer::new_write(
- dma_channel,
- tx_request,
- buf,
- T::regs().dhr12r(channel).as_ptr() as *mut u16,
- TransferOptions {
- circular,
- half_transfer_ir: false,
- complete_transfer_ir: !circular,
- },
- )
- },
- };
-
- tx_f.await;
-
- // finish dma
- // TODO: Do we need to check any status registers here?
- T::regs().cr().modify(|w| {
- // Disable the DAC peripheral
- w.set_en(channel, false);
- // Disable the DMA. TODO: Is this necessary?
- w.set_dmaen(channel, false);
- });
-
- Ok(())
- }
}
impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
+ /// Create a new DAC instance with both channels.
+ ///
+ /// This is used to obtain two independent channels via `split()` for use e.g. with DMA.
pub fn new(
peri: impl Peripheral + 'd,
dma_ch1: impl Peripheral
+ 'd,
@@ -447,22 +322,27 @@ impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
}
}
+ /// Split the DAC into CH1 and CH2 for independent use.
pub fn split(self) -> (DacCh1<'d, T, TxCh1>, DacCh2<'d, T, TxCh2>) {
(self.ch1, self.ch2)
}
+ /// Get mutable reference to CH1
pub fn ch1_mut(&mut self) -> &mut DacCh1<'d, T, TxCh1> {
&mut self.ch1
}
+ /// Get mutable reference to CH2
pub fn ch2_mut(&mut self) -> &mut DacCh2<'d, T, TxCh2> {
&mut self.ch2
}
+ /// Get reference to CH1
pub fn ch1(&mut self) -> &DacCh1<'d, T, TxCh1> {
&self.ch1
}
+ /// Get reference to CH2
pub fn ch2(&mut self) -> &DacCh2<'d, T, TxCh2> {
&self.ch2
}
@@ -470,10 +350,117 @@ impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
impl<'d, T: Instance, Tx> DacChannel for DacCh1<'d, T, Tx> {
const CHANNEL: Channel = Channel::Ch1;
+
+ /// Write `data` to the DAC CH1 via DMA.
+ ///
+ /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
+ /// This will configure a circular DMA transfer that periodically outputs the `data`.
+ /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
+ ///
+ /// **Important:** Channel 1 has to be configured for the DAC instance!
+ async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ where
+ Tx: Dma,
+ {
+ write_inner(Self::CHANNEL, &self.dma, data, circular).await
+ }
}
impl<'d, T: Instance, Tx> DacChannel for DacCh2<'d, T, Tx> {
const CHANNEL: Channel = Channel::Ch2;
+
+ /// Write `data` to the DAC CH2 via DMA.
+ ///
+ /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
+ /// This will configure a circular DMA transfer that periodically outputs the `data`.
+ /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
+ ///
+ /// **Important:** Channel 2 has to be configured for the DAC instance!
+ async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ where
+ Tx: Dma,
+ {
+ write_inner(Self::CHANNEL, &self.dma, data, circular).await
+ }
+}
+
+/// Shared utility function to perform the actual DMA config and write.
+async fn write_inner(
+ ch: Channel,
+ dma: &PeripheralRef<'_, Tx>,
+ data: ValueArray<'_>,
+ circular: bool,
+) -> Result<(), Error>
+where
+ Tx: Dma,
+{
+ let channel = ch.index();
+ debug!("Writing to channel {}", channel);
+
+ // Enable DAC and DMA
+ T::regs().cr().modify(|w| {
+ w.set_en(channel, true);
+ w.set_dmaen(channel, true);
+ });
+
+ let tx_request = dma.request();
+ let dma_channel = dma;
+
+ // Initiate the correct type of DMA transfer depending on what data is passed
+ let tx_f = match data {
+ ValueArray::Bit8(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr8r(channel).as_ptr() as *mut u8,
+ TransferOptions {
+ circular,
+ half_transfer_ir: false,
+ complete_transfer_ir: !circular,
+ },
+ )
+ },
+ ValueArray::Bit12Left(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr12l(channel).as_ptr() as *mut u16,
+ TransferOptions {
+ circular,
+ half_transfer_ir: false,
+ complete_transfer_ir: !circular,
+ },
+ )
+ },
+ ValueArray::Bit12Right(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr12r(channel).as_ptr() as *mut u16,
+ TransferOptions {
+ circular,
+ half_transfer_ir: false,
+ complete_transfer_ir: !circular,
+ },
+ )
+ },
+ };
+
+ tx_f.await;
+
+ // finish dma
+ // TODO: Do we need to check any status registers here?
+ T::regs().cr().modify(|w| {
+ // Disable the DAC peripheral
+ w.set_en(channel, false);
+ // Disable the DMA. TODO: Is this necessary?
+ w.set_dmaen(channel, false);
+ });
+
+ Ok(())
}
pub(crate) mod sealed {
@@ -485,6 +472,7 @@ pub(crate) mod sealed {
pub trait Instance: sealed::Instance + RccPeripheral + 'static {}
dma_trait!(Dma, Instance);
+/// Marks a pin that can be used with the DAC
pub trait DacPin: crate::gpio::Pin + 'static {}
foreach_peripheral!(
From e7bc84dda8cc28835d1b7d3574a94b6142e29864 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Mon, 26 Jun 2023 09:42:25 +0200
Subject: [PATCH 16/48] fix issues when DAC2 present, add additional options to
DMA (NOT YET WORKING with STM32H7A3ZI)
---
embassy-stm32/build.rs | 4 +-
embassy-stm32/src/dac/mod.rs | 267 ++++++++++++++++++++---------------
embassy-stm32/src/dma/dma.rs | 26 +++-
3 files changed, 178 insertions(+), 119 deletions(-)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index f7a25743c..7fa4fae45 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -699,8 +699,8 @@ fn main() {
// SDMMCv1 uses the same channel for both directions, so just implement for RX
(("sdmmc", "RX"), quote!(crate::sdmmc::SdmmcDma)),
(("quadspi", "QUADSPI"), quote!(crate::qspi::QuadDma)),
- (("dac", "CH1"), quote!(crate::dac::Dma)),
- (("dac", "CH2"), quote!(crate::dac::Dma)),
+ (("dac", "CH1"), quote!(crate::dac::DmaCh1)),
+ (("dac", "CH2"), quote!(crate::dac::DmaCh2)),
]
.into();
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index d95674ff0..6ead00e15 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -171,13 +171,6 @@ pub trait DacChannel {
}
Ok(())
}
-
- /// Write `data` to the DAC channel via DMA.
- ///
- /// `circular` sets the DMA to circular mode.
- async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
- where
- Tx: Dma;
}
/// Hold two DAC channels
@@ -244,6 +237,81 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
});
Ok(())
}
+
+ /// Write `data` to the DAC CH1 via DMA.
+ ///
+ /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
+ /// This will configure a circular DMA transfer that periodically outputs the `data`.
+ /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
+ ///
+ /// **Important:** Channel 1 has to be configured for the DAC instance!
+ pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ where
+ Tx: DmaCh1,
+ {
+ let channel = Channel::Ch1.index();
+ debug!("Writing to channel {}", channel);
+
+ // Enable DAC and DMA
+ T::regs().cr().modify(|w| {
+ w.set_en(channel, true);
+ w.set_dmaen(channel, true);
+ });
+
+ let tx_request = self.dma.request();
+ let dma_channel = &self.dma;
+
+ let tx_options = TransferOptions {
+ circular,
+ half_transfer_ir: false,
+ complete_transfer_ir: !circular,
+ ..Default::default()
+ };
+
+ // Initiate the correct type of DMA transfer depending on what data is passed
+ let tx_f = match data {
+ ValueArray::Bit8(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr8r(channel).as_ptr() as *mut u8,
+ tx_options,
+ )
+ },
+ ValueArray::Bit12Left(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr12l(channel).as_ptr() as *mut u16,
+ tx_options,
+ )
+ },
+ ValueArray::Bit12Right(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr12r(channel).as_ptr() as *mut u16,
+ tx_options,
+ )
+ },
+ };
+
+ tx_f.await;
+
+ // finish dma
+ // TODO: Do we need to check any status registers here?
+ T::regs().cr().modify(|w| {
+ // Disable the DAC peripheral
+ w.set_en(channel, false);
+ // Disable the DMA. TODO: Is this necessary?
+ w.set_dmaen(channel, false);
+ });
+
+ Ok(())
+ }
}
impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
@@ -279,6 +347,81 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
});
Ok(())
}
+
+ /// Write `data` to the DAC CH2 via DMA.
+ ///
+ /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
+ /// This will configure a circular DMA transfer that periodically outputs the `data`.
+ /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
+ ///
+ /// **Important:** Channel 2 has to be configured for the DAC instance!
+ pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+ where
+ Tx: DmaCh2,
+ {
+ let channel = Channel::Ch2.index();
+ debug!("Writing to channel {}", channel);
+
+ // Enable DAC and DMA
+ T::regs().cr().modify(|w| {
+ w.set_en(channel, true);
+ w.set_dmaen(channel, true);
+ });
+
+ let tx_request = self.dma.request();
+ let dma_channel = &self.dma;
+
+ let tx_options = TransferOptions {
+ circular,
+ half_transfer_ir: false,
+ complete_transfer_ir: !circular,
+ ..Default::default()
+ };
+
+ // Initiate the correct type of DMA transfer depending on what data is passed
+ let tx_f = match data {
+ ValueArray::Bit8(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr8r(channel).as_ptr() as *mut u8,
+ tx_options,
+ )
+ },
+ ValueArray::Bit12Left(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr12l(channel).as_ptr() as *mut u16,
+ tx_options,
+ )
+ },
+ ValueArray::Bit12Right(buf) => unsafe {
+ Transfer::new_write(
+ dma_channel,
+ tx_request,
+ buf,
+ T::regs().dhr12r(channel).as_ptr() as *mut u16,
+ tx_options,
+ )
+ },
+ };
+
+ tx_f.await;
+
+ // finish dma
+ // TODO: Do we need to check any status registers here?
+ T::regs().cr().modify(|w| {
+ // Disable the DAC peripheral
+ w.set_en(channel, false);
+ // Disable the DMA. TODO: Is this necessary?
+ w.set_dmaen(channel, false);
+ });
+
+ Ok(())
+ }
}
impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
@@ -350,117 +493,10 @@ impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
impl<'d, T: Instance, Tx> DacChannel for DacCh1<'d, T, Tx> {
const CHANNEL: Channel = Channel::Ch1;
-
- /// Write `data` to the DAC CH1 via DMA.
- ///
- /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
- /// This will configure a circular DMA transfer that periodically outputs the `data`.
- /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
- ///
- /// **Important:** Channel 1 has to be configured for the DAC instance!
- async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
- where
- Tx: Dma,
- {
- write_inner(Self::CHANNEL, &self.dma, data, circular).await
- }
}
impl<'d, T: Instance, Tx> DacChannel for DacCh2<'d, T, Tx> {
const CHANNEL: Channel = Channel::Ch2;
-
- /// Write `data` to the DAC CH2 via DMA.
- ///
- /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
- /// This will configure a circular DMA transfer that periodically outputs the `data`.
- /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
- ///
- /// **Important:** Channel 2 has to be configured for the DAC instance!
- async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
- where
- Tx: Dma,
- {
- write_inner(Self::CHANNEL, &self.dma, data, circular).await
- }
-}
-
-/// Shared utility function to perform the actual DMA config and write.
-async fn write_inner(
- ch: Channel,
- dma: &PeripheralRef<'_, Tx>,
- data: ValueArray<'_>,
- circular: bool,
-) -> Result<(), Error>
-where
- Tx: Dma,
-{
- let channel = ch.index();
- debug!("Writing to channel {}", channel);
-
- // Enable DAC and DMA
- T::regs().cr().modify(|w| {
- w.set_en(channel, true);
- w.set_dmaen(channel, true);
- });
-
- let tx_request = dma.request();
- let dma_channel = dma;
-
- // Initiate the correct type of DMA transfer depending on what data is passed
- let tx_f = match data {
- ValueArray::Bit8(buf) => unsafe {
- Transfer::new_write(
- dma_channel,
- tx_request,
- buf,
- T::regs().dhr8r(channel).as_ptr() as *mut u8,
- TransferOptions {
- circular,
- half_transfer_ir: false,
- complete_transfer_ir: !circular,
- },
- )
- },
- ValueArray::Bit12Left(buf) => unsafe {
- Transfer::new_write(
- dma_channel,
- tx_request,
- buf,
- T::regs().dhr12l(channel).as_ptr() as *mut u16,
- TransferOptions {
- circular,
- half_transfer_ir: false,
- complete_transfer_ir: !circular,
- },
- )
- },
- ValueArray::Bit12Right(buf) => unsafe {
- Transfer::new_write(
- dma_channel,
- tx_request,
- buf,
- T::regs().dhr12r(channel).as_ptr() as *mut u16,
- TransferOptions {
- circular,
- half_transfer_ir: false,
- complete_transfer_ir: !circular,
- },
- )
- },
- };
-
- tx_f.await;
-
- // finish dma
- // TODO: Do we need to check any status registers here?
- T::regs().cr().modify(|w| {
- // Disable the DAC peripheral
- w.set_en(channel, false);
- // Disable the DMA. TODO: Is this necessary?
- w.set_dmaen(channel, false);
- });
-
- Ok(())
}
pub(crate) mod sealed {
@@ -470,7 +506,8 @@ pub(crate) mod sealed {
}
pub trait Instance: sealed::Instance + RccPeripheral + 'static {}
-dma_trait!(Dma, Instance);
+dma_trait!(DmaCh1, Instance);
+dma_trait!(DmaCh2, Instance);
/// Marks a pin that can be used with the DAC
pub trait DacPin: crate::gpio::Pin + 'static {}
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
index 8abe541d3..a5f828948 100644
--- a/embassy-stm32/src/dma/dma.rs
+++ b/embassy-stm32/src/dma/dma.rs
@@ -29,6 +29,12 @@ pub struct TransferOptions {
pub flow_ctrl: FlowControl,
/// FIFO threshold for DMA FIFO mode. If none, direct mode is used.
pub fifo_threshold: Option,
+ /// Enable circular DMA
+ pub circular: bool,
+ /// Enable half transfer interrupt
+ pub half_transfer_ir: bool,
+ /// Enable transfer complete interrupt
+ pub complete_transfer_ir: bool,
}
impl Default for TransferOptions {
@@ -38,6 +44,9 @@ impl Default for TransferOptions {
mburst: Burst::Single,
flow_ctrl: FlowControl::Dma,
fifo_threshold: None,
+ circular: false,
+ half_transfer_ir: false,
+ complete_transfer_ir: true,
}
}
}
@@ -366,13 +375,20 @@ impl<'a, C: Channel> Transfer<'a, C> {
});
w.set_pinc(vals::Inc::FIXED);
w.set_teie(true);
- w.set_tcie(true);
+ w.set_tcie(options.complete_transfer_ir);
+ w.set_htie(options.half_transfer_ir);
#[cfg(dma_v1)]
w.set_trbuff(true);
#[cfg(dma_v2)]
w.set_chsel(_request);
+ if options.circular {
+ w.set_circ(vals::Circ::ENABLED);
+ debug!("Setting circular mode");
+ } else {
+ w.set_circ(vals::Circ::DISABLED);
+ }
w.set_pburst(options.pburst.into());
w.set_mburst(options.mburst.into());
w.set_pfctrl(options.flow_ctrl.into());
@@ -404,8 +420,14 @@ impl<'a, C: Channel> Transfer<'a, C> {
}
pub fn is_running(&mut self) -> bool {
+ //let ch = self.channel.regs().st(self.channel.num());
+ //ch.cr().read().en()
+
let ch = self.channel.regs().st(self.channel.num());
- ch.cr().read().en()
+ let en = ch.cr().read().en();
+ let circular = ch.cr().read().circ() == vals::Circ::ENABLED;
+ let tcif = STATE.complete_count[self.channel.index()].load(Ordering::Acquire) != 0;
+ en && (circular || !tcif)
}
/// Gets the total remaining transfers for the channel
From 28fb492c402c74add5c650b9d65687816585c923 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Tue, 27 Jun 2023 00:42:24 +0200
Subject: [PATCH 17/48] stm32/otg: flush fifos on reconfigure and on ep
disable.
---
embassy-stm32/src/usb_otg/usb.rs | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/embassy-stm32/src/usb_otg/usb.rs b/embassy-stm32/src/usb_otg/usb.rs
index 8af5c7bd5..532157e6c 100644
--- a/embassy-stm32/src/usb_otg/usb.rs
+++ b/embassy-stm32/src/usb_otg/usb.rs
@@ -540,6 +540,19 @@ impl<'d, T: Instance> Bus<'d, T> {
fifo_top <= T::FIFO_DEPTH_WORDS,
"FIFO allocations exceeded maximum capacity"
);
+
+ // Flush fifos
+ r.grstctl().write(|w| {
+ w.set_rxfflsh(true);
+ w.set_txfflsh(true);
+ w.set_txfnum(0x10);
+ });
+ loop {
+ let x = r.grstctl().read();
+ if !x.rxfflsh() && !x.txfflsh() {
+ break;
+ }
+ }
}
fn configure_endpoints(&mut self) {
@@ -744,7 +757,19 @@ impl<'d, T: Instance> embassy_usb_driver::Bus for Bus<'d, T> {
r.doepctl(ep_addr.index()).modify(|w| {
w.set_usbaep(enabled);
- })
+ });
+
+ // Flush tx fifo
+ r.grstctl().write(|w| {
+ w.set_txfflsh(true);
+ w.set_txfnum(ep_addr.index() as _);
+ });
+ loop {
+ let x = r.grstctl().read();
+ if !x.txfflsh() {
+ break;
+ }
+ }
});
// Wake `Endpoint::wait_enabled()`
From a575e40a3503f4bf500b7ee3cadcce44727c7c6f Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Tue, 27 Jun 2023 02:12:06 +0200
Subject: [PATCH 18/48] stm32/otg: clear NAK bit on endpoint enable.
---
embassy-stm32/src/usb_otg/usb.rs | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/embassy-stm32/src/usb_otg/usb.rs b/embassy-stm32/src/usb_otg/usb.rs
index 532157e6c..1a0d44fd2 100644
--- a/embassy-stm32/src/usb_otg/usb.rs
+++ b/embassy-stm32/src/usb_otg/usb.rs
@@ -780,13 +780,14 @@ impl<'d, T: Instance> embassy_usb_driver::Bus for Bus<'d, T> {
// cancel transfer if active
if !enabled && r.diepctl(ep_addr.index()).read().epena() {
r.diepctl(ep_addr.index()).modify(|w| {
- w.set_snak(true);
+ w.set_snak(true); // set NAK
w.set_epdis(true);
})
}
r.diepctl(ep_addr.index()).modify(|w| {
w.set_usbaep(enabled);
+ w.set_cnak(enabled); // clear NAK that might've been set by SNAK above.
})
});
From 80407aa930279a7d23bd1295c7703d0d9064aa58 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Tue, 27 Jun 2023 02:12:33 +0200
Subject: [PATCH 19/48] stm32/otg: set tx fifo num in IN endpoints on
configure.
---
embassy-stm32/src/usb_otg/usb.rs | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/usb_otg/usb.rs b/embassy-stm32/src/usb_otg/usb.rs
index 1a0d44fd2..b2f7eb852 100644
--- a/embassy-stm32/src/usb_otg/usb.rs
+++ b/embassy-stm32/src/usb_otg/usb.rs
@@ -124,7 +124,7 @@ impl interrupt::typelevel::Handler for InterruptHandl
}
state.ep_in_wakers[ep_num].wake();
- trace!("in ep={} irq val={:b}", ep_num, ep_ints.0);
+ trace!("in ep={} irq val={:08x}", ep_num, ep_ints.0);
}
ep_mask >>= 1;
@@ -144,7 +144,7 @@ impl interrupt::typelevel::Handler for InterruptHandl
// // clear all
// r.doepint(ep_num).write_value(ep_ints);
// state.ep_out_wakers[ep_num].wake();
- // trace!("out ep={} irq val={=u32:b}", ep_num, ep_ints.0);
+ // trace!("out ep={} irq val={:08x}", ep_num, ep_ints.0);
// }
// ep_mask >>= 1;
@@ -571,6 +571,8 @@ impl<'d, T: Instance> Bus<'d, T> {
w.set_mpsiz(ep.max_packet_size);
w.set_eptyp(to_eptyp(ep.ep_type));
w.set_sd0pid_sevnfrm(true);
+ w.set_txfnum(index as _);
+ w.set_snak(true);
}
});
});
From 5e6e18b310ef3c19fd4cdc42fa74dd8ed455e444 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Tue, 27 Jun 2023 03:56:09 +0200
Subject: [PATCH 20/48] stm32/usb: add TODO: implement VBUS detection.
---
embassy-stm32/src/usb/usb.rs | 95 ++++++++++++++++++------------------
1 file changed, 48 insertions(+), 47 deletions(-)
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 2367127e8..01b158b17 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -480,56 +480,57 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
poll_fn(move |cx| {
BUS_WAKER.register(cx.waker());
- if self.inited {
- let regs = T::regs();
-
- if IRQ_RESUME.load(Ordering::Acquire) {
- IRQ_RESUME.store(false, Ordering::Relaxed);
- return Poll::Ready(Event::Resume);
- }
-
- if IRQ_RESET.load(Ordering::Acquire) {
- IRQ_RESET.store(false, Ordering::Relaxed);
-
- trace!("RESET");
- regs.daddr().write(|w| {
- w.set_ef(true);
- w.set_add(0);
- });
-
- regs.epr(0).write(|w| {
- w.set_ep_type(EpType::CONTROL);
- w.set_stat_rx(Stat::NAK);
- w.set_stat_tx(Stat::NAK);
- });
-
- for i in 1..EP_COUNT {
- regs.epr(i).write(|w| {
- w.set_ea(i as _);
- w.set_ep_type(self.ep_types[i - 1]);
- })
- }
-
- for w in &EP_IN_WAKERS {
- w.wake()
- }
- for w in &EP_OUT_WAKERS {
- w.wake()
- }
-
- return Poll::Ready(Event::Reset);
- }
-
- if IRQ_SUSPEND.load(Ordering::Acquire) {
- IRQ_SUSPEND.store(false, Ordering::Relaxed);
- return Poll::Ready(Event::Suspend);
- }
-
- Poll::Pending
- } else {
+ // TODO: implement VBUS detection.
+ if !self.inited {
self.inited = true;
return Poll::Ready(Event::PowerDetected);
}
+
+ let regs = T::regs();
+
+ if IRQ_RESUME.load(Ordering::Acquire) {
+ IRQ_RESUME.store(false, Ordering::Relaxed);
+ return Poll::Ready(Event::Resume);
+ }
+
+ if IRQ_RESET.load(Ordering::Acquire) {
+ IRQ_RESET.store(false, Ordering::Relaxed);
+
+ trace!("RESET");
+ regs.daddr().write(|w| {
+ w.set_ef(true);
+ w.set_add(0);
+ });
+
+ regs.epr(0).write(|w| {
+ w.set_ep_type(EpType::CONTROL);
+ w.set_stat_rx(Stat::NAK);
+ w.set_stat_tx(Stat::NAK);
+ });
+
+ for i in 1..EP_COUNT {
+ regs.epr(i).write(|w| {
+ w.set_ea(i as _);
+ w.set_ep_type(self.ep_types[i - 1]);
+ })
+ }
+
+ for w in &EP_IN_WAKERS {
+ w.wake()
+ }
+ for w in &EP_OUT_WAKERS {
+ w.wake()
+ }
+
+ return Poll::Ready(Event::Reset);
+ }
+
+ if IRQ_SUSPEND.load(Ordering::Acquire) {
+ IRQ_SUSPEND.store(false, Ordering::Relaxed);
+ return Poll::Ready(Event::Suspend);
+ }
+
+ Poll::Pending
})
.await
}
From a2d1e7f02ca8d94c755ced56f1db11646ac2aa72 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Tue, 27 Jun 2023 03:56:25 +0200
Subject: [PATCH 21/48] rp/usb: add TODO: implement VBUS detection.
---
embassy-rp/src/usb.rs | 1 +
1 file changed, 1 insertion(+)
diff --git a/embassy-rp/src/usb.rs b/embassy-rp/src/usb.rs
index 1900ab416..b3f3bd927 100644
--- a/embassy-rp/src/usb.rs
+++ b/embassy-rp/src/usb.rs
@@ -353,6 +353,7 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
poll_fn(move |cx| {
BUS_WAKER.register(cx.waker());
+ // TODO: implement VBUS detection.
if !self.inited {
self.inited = true;
return Poll::Ready(Event::PowerDetected);
From 219ef5b37a1dff5f6e770da252ec010d55c43257 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Tue, 27 Jun 2023 08:42:51 +0200
Subject: [PATCH 22/48] stm32/otg: add VBUS detection.
Fixes #1442.
---
embassy-stm32/src/usb_otg/usb.rs | 479 +++++++++++++----------
examples/stm32f4/src/bin/usb_ethernet.rs | 4 +-
examples/stm32f4/src/bin/usb_serial.rs | 4 +-
examples/stm32f7/src/bin/usb_serial.rs | 4 +-
examples/stm32h7/src/bin/usb_serial.rs | 4 +-
examples/stm32l4/src/bin/usb_serial.rs | 4 +-
examples/stm32u5/src/bin/usb_serial.rs | 4 +-
7 files changed, 297 insertions(+), 206 deletions(-)
diff --git a/embassy-stm32/src/usb_otg/usb.rs b/embassy-stm32/src/usb_otg/usb.rs
index b2f7eb852..6c00c93d6 100644
--- a/embassy-stm32/src/usb_otg/usb.rs
+++ b/embassy-stm32/src/usb_otg/usb.rs
@@ -6,8 +6,8 @@ use atomic_polyfill::{AtomicBool, AtomicU16, Ordering};
use embassy_hal_common::{into_ref, Peripheral};
use embassy_sync::waitqueue::AtomicWaker;
use embassy_usb_driver::{
- self, Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointIn, EndpointInfo, EndpointOut,
- EndpointType, Event, Unsupported,
+ self, Bus as _, Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointIn, EndpointInfo,
+ EndpointOut, EndpointType, Event, Unsupported,
};
use futures::future::poll_fn;
@@ -31,7 +31,7 @@ impl interrupt::typelevel::Handler for InterruptHandl
let state = T::state();
let ints = r.gintsts().read();
- if ints.wkupint() || ints.usbsusp() || ints.usbrst() || ints.enumdne() {
+ if ints.wkupint() || ints.usbsusp() || ints.usbrst() || ints.enumdne() || ints.otgint() || ints.srqint() {
// Mask interrupts and notify `Bus` to process them
r.gintmsk().write(|_| {});
T::state().bus_waker.wake();
@@ -256,7 +256,34 @@ struct EndpointData {
fifo_size_words: u16,
}
+#[non_exhaustive]
+#[derive(Clone, Copy, PartialEq, Eq, Debug)]
+pub struct Config {
+ /// Enable VBUS detection.
+ ///
+ /// The USB spec requires USB devices monitor for USB cable plug/unplug and react accordingly.
+ /// This is done by checkihg whether there is 5V on the VBUS pin or not.
+ ///
+ /// If your device is bus-powered (powers itself from the USB host via VBUS), then this is optional.
+ /// (if there's no power in VBUS your device would be off anyway, so it's fine to always assume
+ /// there's power in VBUS, i.e. the USB cable is always plugged in.)
+ ///
+ /// If your device is self-powered (i.e. it gets power from a source other than the USB cable, and
+ /// therefore can stay powered through USB cable plug/unplug) then you MUST set this to true.
+ ///
+ /// If you set this to true, you must connect VBUS to PA9 for FS, PB13 for HS, possibly with a
+ /// voltage divider. See ST application note AN4879 and the reference manual for more details.
+ pub vbus_detection: bool,
+}
+
+impl Default for Config {
+ fn default() -> Self {
+ Self { vbus_detection: true }
+ }
+}
+
pub struct Driver<'d, T: Instance> {
+ config: Config,
phantom: PhantomData<&'d mut T>,
ep_in: [Option; MAX_EP_COUNT],
ep_out: [Option; MAX_EP_COUNT],
@@ -279,6 +306,7 @@ impl<'d, T: Instance> Driver<'d, T> {
dp: impl Peripheral> + 'd,
dm: impl Peripheral
> + 'd,
ep_out_buffer: &'d mut [u8],
+ config: Config,
) -> Self {
into_ref!(dp, dm);
@@ -286,6 +314,7 @@ impl<'d, T: Instance> Driver<'d, T> {
dm.set_as_af(dm.af_num(), AFType::OutputPushPull);
Self {
+ config,
phantom: PhantomData,
ep_in: [None; MAX_EP_COUNT],
ep_out: [None; MAX_EP_COUNT],
@@ -318,6 +347,7 @@ impl<'d, T: Instance> Driver<'d, T> {
ulpi_d6: impl Peripheral
> + 'd,
ulpi_d7: impl Peripheral
> + 'd,
ep_out_buffer: &'d mut [u8],
+ config: Config,
) -> Self {
assert!(T::HIGH_SPEED == true, "Peripheral is not capable of high-speed USB");
@@ -327,6 +357,7 @@ impl<'d, T: Instance> Driver<'d, T> {
);
Self {
+ config,
phantom: PhantomData,
ep_in: [None; MAX_EP_COUNT],
ep_out: [None; MAX_EP_COUNT],
@@ -464,11 +495,12 @@ impl<'d, T: Instance> embassy_usb_driver::Driver<'d> for Driver<'d, T> {
(
Bus {
+ config: self.config,
phantom: PhantomData,
ep_in: self.ep_in,
ep_out: self.ep_out,
phy_type: self.phy_type,
- enabled: false,
+ inited: false,
},
ControlPipe {
_phantom: PhantomData,
@@ -481,11 +513,12 @@ impl<'d, T: Instance> embassy_usb_driver::Driver<'d> for Driver<'d, T> {
}
pub struct Bus<'d, T: Instance> {
+ config: Config,
phantom: PhantomData<&'d mut T>,
ep_in: [Option; MAX_EP_COUNT],
ep_out: [Option; MAX_EP_COUNT],
phy_type: PhyType,
- enabled: bool,
+ inited: bool,
}
impl<'d, T: Instance> Bus<'d, T> {
@@ -498,11 +531,202 @@ impl<'d, T: Instance> Bus<'d, T> {
w.set_iepint(true);
w.set_oepint(true);
w.set_rxflvlm(true);
+ w.set_srqim(true);
+ w.set_otgint(true);
});
}
}
impl<'d, T: Instance> Bus<'d, T> {
+ fn init(&mut self) {
+ #[cfg(stm32l4)]
+ {
+ crate::peripherals::PWR::enable();
+ critical_section::with(|_| crate::pac::PWR.cr2().modify(|w| w.set_usv(true)));
+ }
+
+ #[cfg(stm32f7)]
+ {
+ // Enable ULPI clock if external PHY is used
+ let ulpien = !self.phy_type.internal();
+ critical_section::with(|_| {
+ crate::pac::RCC.ahb1enr().modify(|w| {
+ if T::HIGH_SPEED {
+ w.set_usb_otg_hsulpien(ulpien);
+ } else {
+ w.set_usb_otg_hsen(ulpien);
+ }
+ });
+
+ // Low power mode
+ crate::pac::RCC.ahb1lpenr().modify(|w| {
+ if T::HIGH_SPEED {
+ w.set_usb_otg_hsulpilpen(ulpien);
+ } else {
+ w.set_usb_otg_hslpen(ulpien);
+ }
+ });
+ });
+ }
+
+ #[cfg(stm32h7)]
+ {
+ // If true, VDD33USB is generated by internal regulator from VDD50USB
+ // If false, VDD33USB and VDD50USB must be suplied directly with 3.3V (default on nucleo)
+ // TODO: unhardcode
+ let internal_regulator = false;
+
+ // Enable USB power
+ critical_section::with(|_| {
+ crate::pac::PWR.cr3().modify(|w| {
+ w.set_usb33den(true);
+ w.set_usbregen(internal_regulator);
+ })
+ });
+
+ // Wait for USB power to stabilize
+ while !crate::pac::PWR.cr3().read().usb33rdy() {}
+
+ // Use internal 48MHz HSI clock. Should be enabled in RCC by default.
+ critical_section::with(|_| {
+ crate::pac::RCC
+ .d2ccip2r()
+ .modify(|w| w.set_usbsel(crate::pac::rcc::vals::Usbsel::HSI48))
+ });
+
+ // Enable ULPI clock if external PHY is used
+ let ulpien = !self.phy_type.internal();
+ critical_section::with(|_| {
+ crate::pac::RCC.ahb1enr().modify(|w| {
+ if T::HIGH_SPEED {
+ w.set_usb_otg_hs_ulpien(ulpien);
+ } else {
+ w.set_usb_otg_fs_ulpien(ulpien);
+ }
+ });
+ crate::pac::RCC.ahb1lpenr().modify(|w| {
+ if T::HIGH_SPEED {
+ w.set_usb_otg_hs_ulpilpen(ulpien);
+ } else {
+ w.set_usb_otg_fs_ulpilpen(ulpien);
+ }
+ });
+ });
+ }
+
+ #[cfg(stm32u5)]
+ {
+ // Enable USB power
+ critical_section::with(|_| {
+ crate::pac::RCC.ahb3enr().modify(|w| {
+ w.set_pwren(true);
+ });
+ cortex_m::asm::delay(2);
+
+ crate::pac::PWR.svmcr().modify(|w| {
+ w.set_usv(true);
+ w.set_uvmen(true);
+ });
+ });
+
+ // Wait for USB power to stabilize
+ while !crate::pac::PWR.svmsr().read().vddusbrdy() {}
+
+ // Select HSI48 as USB clock source.
+ critical_section::with(|_| {
+ crate::pac::RCC.ccipr1().modify(|w| {
+ w.set_iclksel(crate::pac::rcc::vals::Iclksel::HSI48);
+ })
+ });
+ }
+
+ ::enable();
+ ::reset();
+
+ T::Interrupt::unpend();
+ unsafe { T::Interrupt::enable() };
+
+ let r = T::regs();
+ let core_id = r.cid().read().0;
+ info!("Core id {:08x}", core_id);
+
+ // Wait for AHB ready.
+ while !r.grstctl().read().ahbidl() {}
+
+ // Configure as device.
+ r.gusbcfg().write(|w| {
+ // Force device mode
+ w.set_fdmod(true);
+ // Enable internal full-speed PHY
+ w.set_physel(self.phy_type.internal() && !self.phy_type.high_speed());
+ });
+
+ // Configuring Vbus sense and SOF output
+ match core_id {
+ 0x0000_1200 | 0x0000_1100 => {
+ assert!(self.phy_type != PhyType::InternalHighSpeed);
+
+ r.gccfg_v1().modify(|w| {
+ // Enable internal full-speed PHY, logic is inverted
+ w.set_pwrdwn(self.phy_type.internal());
+ });
+
+ // F429-like chips have the GCCFG.NOVBUSSENS bit
+ r.gccfg_v1().modify(|w| {
+ w.set_novbussens(!self.config.vbus_detection);
+ w.set_vbusasen(false);
+ w.set_vbusbsen(self.config.vbus_detection);
+ w.set_sofouten(false);
+ });
+ }
+ 0x0000_2000 | 0x0000_2100 | 0x0000_2300 | 0x0000_3000 | 0x0000_3100 => {
+ // F446-like chips have the GCCFG.VBDEN bit with the opposite meaning
+ r.gccfg_v2().modify(|w| {
+ // Enable internal full-speed PHY, logic is inverted
+ w.set_pwrdwn(self.phy_type.internal() && !self.phy_type.high_speed());
+ w.set_phyhsen(self.phy_type.internal() && self.phy_type.high_speed());
+ });
+
+ r.gccfg_v2().modify(|w| {
+ w.set_vbden(self.config.vbus_detection);
+ });
+
+ // Force B-peripheral session
+ r.gotgctl().modify(|w| {
+ w.set_bvaloen(!self.config.vbus_detection);
+ w.set_bvaloval(true);
+ });
+ }
+ _ => unimplemented!("Unknown USB core id {:X}", core_id),
+ }
+
+ // Soft disconnect.
+ r.dctl().write(|w| w.set_sdis(true));
+
+ // Set speed.
+ r.dcfg().write(|w| {
+ w.set_pfivl(vals::Pfivl::FRAME_INTERVAL_80);
+ w.set_dspd(self.phy_type.to_dspd());
+ });
+
+ // Unmask transfer complete EP interrupt
+ r.diepmsk().write(|w| {
+ w.set_xfrcm(true);
+ });
+
+ // Unmask and clear core interrupts
+ Bus::::restore_irqs();
+ r.gintsts().write_value(regs::Gintsts(0xFFFF_FFFF));
+
+ // Unmask global interrupt
+ r.gahbcfg().write(|w| {
+ w.set_gint(true); // unmask global interrupt
+ });
+
+ // Connect
+ r.dctl().write(|w| w.set_sdis(false));
+ }
+
fn init_fifo(&mut self) {
trace!("init_fifo");
@@ -613,6 +837,13 @@ impl<'d, T: Instance> Bus<'d, T> {
});
}
+ fn disable_all_endpoints(&mut self) {
+ for i in 0..T::ENDPOINT_COUNT {
+ self.endpoint_set_enabled(EndpointAddress::from_parts(i, Direction::In), false);
+ self.endpoint_set_enabled(EndpointAddress::from_parts(i, Direction::Out), false);
+ }
+ }
+
fn disable(&mut self) {
T::Interrupt::disable();
@@ -627,9 +858,14 @@ impl<'d, T: Instance> Bus<'d, T> {
impl<'d, T: Instance> embassy_usb_driver::Bus for Bus<'d, T> {
async fn poll(&mut self) -> Event {
poll_fn(move |cx| {
- // TODO: implement VBUS detection
- if !self.enabled {
- return Poll::Ready(Event::PowerDetected);
+ if !self.inited {
+ self.init();
+ self.inited = true;
+
+ // If no vbus detection, just return a single PowerDetected event at startup.
+ if !self.config.vbus_detection {
+ return Poll::Ready(Event::PowerDetected);
+ }
}
let r = T::regs();
@@ -637,6 +873,32 @@ impl<'d, T: Instance> embassy_usb_driver::Bus for Bus<'d, T> {
T::state().bus_waker.register(cx.waker());
let ints = r.gintsts().read();
+
+ if ints.srqint() {
+ trace!("vbus detected");
+
+ r.gintsts().write(|w| w.set_srqint(true)); // clear
+ Self::restore_irqs();
+
+ if self.config.vbus_detection {
+ return Poll::Ready(Event::PowerDetected);
+ }
+ }
+
+ if ints.otgint() {
+ let otgints = r.gotgint().read();
+ r.gotgint().write_value(otgints); // clear all
+ Self::restore_irqs();
+
+ if otgints.sedet() {
+ trace!("vbus removed");
+ if self.config.vbus_detection {
+ self.disable_all_endpoints();
+ return Poll::Ready(Event::PowerRemoved);
+ }
+ }
+ }
+
if ints.usbrst() {
trace!("reset");
@@ -801,203 +1063,14 @@ impl<'d, T: Instance> embassy_usb_driver::Bus for Bus<'d, T> {
async fn enable(&mut self) {
trace!("enable");
-
- #[cfg(stm32l4)]
- {
- crate::peripherals::PWR::enable();
- critical_section::with(|_| crate::pac::PWR.cr2().modify(|w| w.set_usv(true)));
- }
-
- #[cfg(stm32f7)]
- {
- // Enable ULPI clock if external PHY is used
- let ulpien = !self.phy_type.internal();
- critical_section::with(|_| {
- crate::pac::RCC.ahb1enr().modify(|w| {
- if T::HIGH_SPEED {
- w.set_usb_otg_hsulpien(ulpien);
- } else {
- w.set_usb_otg_hsen(ulpien);
- }
- });
-
- // Low power mode
- crate::pac::RCC.ahb1lpenr().modify(|w| {
- if T::HIGH_SPEED {
- w.set_usb_otg_hsulpilpen(ulpien);
- } else {
- w.set_usb_otg_hslpen(ulpien);
- }
- });
- });
- }
-
- #[cfg(stm32h7)]
- {
- // If true, VDD33USB is generated by internal regulator from VDD50USB
- // If false, VDD33USB and VDD50USB must be suplied directly with 3.3V (default on nucleo)
- // TODO: unhardcode
- let internal_regulator = false;
-
- // Enable USB power
- critical_section::with(|_| {
- crate::pac::PWR.cr3().modify(|w| {
- w.set_usb33den(true);
- w.set_usbregen(internal_regulator);
- })
- });
-
- // Wait for USB power to stabilize
- while !crate::pac::PWR.cr3().read().usb33rdy() {}
-
- // Use internal 48MHz HSI clock. Should be enabled in RCC by default.
- critical_section::with(|_| {
- crate::pac::RCC
- .d2ccip2r()
- .modify(|w| w.set_usbsel(crate::pac::rcc::vals::Usbsel::HSI48))
- });
-
- // Enable ULPI clock if external PHY is used
- let ulpien = !self.phy_type.internal();
- critical_section::with(|_| {
- crate::pac::RCC.ahb1enr().modify(|w| {
- if T::HIGH_SPEED {
- w.set_usb_otg_hs_ulpien(ulpien);
- } else {
- w.set_usb_otg_fs_ulpien(ulpien);
- }
- });
- crate::pac::RCC.ahb1lpenr().modify(|w| {
- if T::HIGH_SPEED {
- w.set_usb_otg_hs_ulpilpen(ulpien);
- } else {
- w.set_usb_otg_fs_ulpilpen(ulpien);
- }
- });
- });
- }
-
- #[cfg(stm32u5)]
- {
- // Enable USB power
- critical_section::with(|_| {
- crate::pac::RCC.ahb3enr().modify(|w| {
- w.set_pwren(true);
- });
- cortex_m::asm::delay(2);
-
- crate::pac::PWR.svmcr().modify(|w| {
- w.set_usv(true);
- w.set_uvmen(true);
- });
- });
-
- // Wait for USB power to stabilize
- while !crate::pac::PWR.svmsr().read().vddusbrdy() {}
-
- // Select HSI48 as USB clock source.
- critical_section::with(|_| {
- crate::pac::RCC.ccipr1().modify(|w| {
- w.set_iclksel(crate::pac::rcc::vals::Iclksel::HSI48);
- })
- });
- }
-
- ::enable();
- ::reset();
-
- T::Interrupt::unpend();
- unsafe { T::Interrupt::enable() };
-
- let r = T::regs();
- let core_id = r.cid().read().0;
- info!("Core id {:08x}", core_id);
-
- // Wait for AHB ready.
- while !r.grstctl().read().ahbidl() {}
-
- // Configure as device.
- r.gusbcfg().write(|w| {
- // Force device mode
- w.set_fdmod(true);
- // Enable internal full-speed PHY
- w.set_physel(self.phy_type.internal() && !self.phy_type.high_speed());
- });
-
- // Configuring Vbus sense and SOF output
- match core_id {
- 0x0000_1200 | 0x0000_1100 => {
- assert!(self.phy_type != PhyType::InternalHighSpeed);
-
- r.gccfg_v1().modify(|w| {
- // Enable internal full-speed PHY, logic is inverted
- w.set_pwrdwn(self.phy_type.internal());
- });
-
- // F429-like chips have the GCCFG.NOVBUSSENS bit
- r.gccfg_v1().modify(|w| {
- w.set_novbussens(true);
- w.set_vbusasen(false);
- w.set_vbusbsen(false);
- w.set_sofouten(false);
- });
- }
- 0x0000_2000 | 0x0000_2100 | 0x0000_2300 | 0x0000_3000 | 0x0000_3100 => {
- // F446-like chips have the GCCFG.VBDEN bit with the opposite meaning
- r.gccfg_v2().modify(|w| {
- // Enable internal full-speed PHY, logic is inverted
- w.set_pwrdwn(self.phy_type.internal() && !self.phy_type.high_speed());
- w.set_phyhsen(self.phy_type.internal() && self.phy_type.high_speed());
- });
-
- r.gccfg_v2().modify(|w| {
- w.set_vbden(false);
- });
-
- // Force B-peripheral session
- r.gotgctl().modify(|w| {
- w.set_bvaloen(true);
- w.set_bvaloval(true);
- });
- }
- _ => unimplemented!("Unknown USB core id {:X}", core_id),
- }
-
- // Soft disconnect.
- r.dctl().write(|w| w.set_sdis(true));
-
- // Set speed.
- r.dcfg().write(|w| {
- w.set_pfivl(vals::Pfivl::FRAME_INTERVAL_80);
- w.set_dspd(self.phy_type.to_dspd());
- });
-
- // Unmask transfer complete EP interrupt
- r.diepmsk().write(|w| {
- w.set_xfrcm(true);
- });
-
- // Unmask and clear core interrupts
- Bus::::restore_irqs();
- r.gintsts().write_value(regs::Gintsts(0xFFFF_FFFF));
-
- // Unmask global interrupt
- r.gahbcfg().write(|w| {
- w.set_gint(true); // unmask global interrupt
- });
-
- // Connect
- r.dctl().write(|w| w.set_sdis(false));
-
- self.enabled = true;
+ // TODO: enable the peripheral once enable/disable semantics are cleared up in embassy-usb
}
async fn disable(&mut self) {
trace!("disable");
- Bus::disable(self);
-
- self.enabled = false;
+ // TODO: disable the peripheral once enable/disable semantics are cleared up in embassy-usb
+ //Bus::disable(self);
}
async fn remote_wakeup(&mut self) -> Result<(), Unsupported> {
@@ -1140,11 +1213,16 @@ impl<'d, T: Instance> embassy_usb_driver::EndpointIn for Endpoint<'d, T, In> {
state.ep_in_wakers[index].register(cx.waker());
let diepctl = r.diepctl(index).read();
+ let dtxfsts = r.dtxfsts(index).read();
+ info!("diepctl {:08x} ftxfsts {:08x}", diepctl.0, dtxfsts.0);
if !diepctl.usbaep() {
+ trace!("write ep={:?} wait for prev: error disabled", self.info.addr);
Poll::Ready(Err(EndpointError::Disabled))
} else if !diepctl.epena() {
+ trace!("write ep={:?} wait for prev: ready", self.info.addr);
Poll::Ready(Ok(()))
} else {
+ trace!("write ep={:?} wait for prev: pending", self.info.addr);
Poll::Pending
}
})
@@ -1169,6 +1247,7 @@ impl<'d, T: Instance> embassy_usb_driver::EndpointIn for Endpoint<'d, T, In> {
Poll::Pending
} else {
+ trace!("write ep={:?} wait for fifo: ready", self.info.addr);
Poll::Ready(())
}
})
diff --git a/examples/stm32f4/src/bin/usb_ethernet.rs b/examples/stm32f4/src/bin/usb_ethernet.rs
index 953d99a45..b1f01417c 100644
--- a/examples/stm32f4/src/bin/usb_ethernet.rs
+++ b/examples/stm32f4/src/bin/usb_ethernet.rs
@@ -52,7 +52,9 @@ async fn main(spawner: Spawner) {
// Create the driver, from the HAL.
let ep_out_buffer = &mut make_static!([0; 256])[..];
- let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, ep_out_buffer);
+ let mut config = embassy_stm32::usb_otg::Config::default();
+ config.vbus_detection = true;
+ let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, ep_out_buffer, config);
// Create embassy-usb Config
let mut config = embassy_usb::Config::new(0xc0de, 0xcafe);
diff --git a/examples/stm32f4/src/bin/usb_serial.rs b/examples/stm32f4/src/bin/usb_serial.rs
index f8f5940a7..4ff6452ef 100644
--- a/examples/stm32f4/src/bin/usb_serial.rs
+++ b/examples/stm32f4/src/bin/usb_serial.rs
@@ -29,7 +29,9 @@ async fn main(_spawner: Spawner) {
// Create the driver, from the HAL.
let mut ep_out_buffer = [0u8; 256];
- let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer);
+ let mut config = embassy_stm32::usb_otg::Config::default();
+ config.vbus_detection = true;
+ let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer, config);
// Create embassy-usb Config
let mut config = embassy_usb::Config::new(0xc0de, 0xcafe);
diff --git a/examples/stm32f7/src/bin/usb_serial.rs b/examples/stm32f7/src/bin/usb_serial.rs
index 763309ce2..a2c76178b 100644
--- a/examples/stm32f7/src/bin/usb_serial.rs
+++ b/examples/stm32f7/src/bin/usb_serial.rs
@@ -30,7 +30,9 @@ async fn main(_spawner: Spawner) {
// Create the driver, from the HAL.
let mut ep_out_buffer = [0u8; 256];
- let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer);
+ let mut config = embassy_stm32::usb_otg::Config::default();
+ config.vbus_detection = true;
+ let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer, config);
// Create embassy-usb Config
let mut config = embassy_usb::Config::new(0xc0de, 0xcafe);
diff --git a/examples/stm32h7/src/bin/usb_serial.rs b/examples/stm32h7/src/bin/usb_serial.rs
index c622f19f7..97291f60c 100644
--- a/examples/stm32h7/src/bin/usb_serial.rs
+++ b/examples/stm32h7/src/bin/usb_serial.rs
@@ -29,7 +29,9 @@ async fn main(_spawner: Spawner) {
// Create the driver, from the HAL.
let mut ep_out_buffer = [0u8; 256];
- let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer);
+ let mut config = embassy_stm32::usb_otg::Config::default();
+ config.vbus_detection = true;
+ let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer, config);
// Create embassy-usb Config
let mut config = embassy_usb::Config::new(0xc0de, 0xcafe);
diff --git a/examples/stm32l4/src/bin/usb_serial.rs b/examples/stm32l4/src/bin/usb_serial.rs
index 80811a43e..410d6891b 100644
--- a/examples/stm32l4/src/bin/usb_serial.rs
+++ b/examples/stm32l4/src/bin/usb_serial.rs
@@ -30,7 +30,9 @@ async fn main(_spawner: Spawner) {
// Create the driver, from the HAL.
let mut ep_out_buffer = [0u8; 256];
- let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer);
+ let mut config = embassy_stm32::usb_otg::Config::default();
+ config.vbus_detection = true;
+ let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer, config);
// Create embassy-usb Config
let mut config = embassy_usb::Config::new(0xc0de, 0xcafe);
diff --git a/examples/stm32u5/src/bin/usb_serial.rs b/examples/stm32u5/src/bin/usb_serial.rs
index f36daf91b..9e47fb18a 100644
--- a/examples/stm32u5/src/bin/usb_serial.rs
+++ b/examples/stm32u5/src/bin/usb_serial.rs
@@ -31,7 +31,9 @@ async fn main(_spawner: Spawner) {
// Create the driver, from the HAL.
let mut ep_out_buffer = [0u8; 256];
- let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer);
+ let mut config = embassy_stm32::usb_otg::Config::default();
+ config.vbus_detection = true;
+ let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer, config);
// Create embassy-usb Config
let mut config = embassy_usb::Config::new(0xc0de, 0xcafe);
From afec1b439bb40b769c8ccd1c1b19d58edd034c3d Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Tue, 27 Jun 2023 18:17:51 +0200
Subject: [PATCH 23/48] feature-gate dma write, make trigger not return a
result
---
embassy-stm32/src/dac/mod.rs | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 6ead00e15..3e48d558a 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -153,11 +153,10 @@ pub trait DacChannel {
}
/// Perform a software trigger on `ch`
- fn trigger(&mut self) -> Result<(), Error> {
+ fn trigger(&mut self) {
T::regs().swtrigr().write(|reg| {
reg.set_swtrig(Self::CHANNEL.index(), true);
});
- Ok(())
}
/// Set a value to be output by the DAC on trigger.
@@ -230,6 +229,8 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
}
/// Select a new trigger for this channel
+ ///
+ /// **Important**: This disables the channel!
pub fn select_trigger(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
unwrap!(self.disable_channel());
T::regs().cr().modify(|reg| {
@@ -245,6 +246,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
///
/// **Important:** Channel 1 has to be configured for the DAC instance!
+ #[cfg(all(bdma, not(dma)))] // It currently only works with BDMA-only chips (DMA should theoretically work though)
pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
where
Tx: DmaCh1,
@@ -355,6 +357,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
///
/// **Important:** Channel 2 has to be configured for the DAC instance!
+ #[cfg(all(bdma, not(dma)))] // It currently only works with BDMA-only chips (DMA should theoretically work though)
pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
where
Tx: DmaCh2,
From 56dd22f0ac49be2b824e88026d38b69843b56972 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Tue, 27 Jun 2023 21:23:47 +0200
Subject: [PATCH 24/48] feature-gate set_channel_mode, undo dma.rs changes
---
embassy-stm32/src/dac/mod.rs | 17 ++++++++++-------
embassy-stm32/src/dma/dma.rs | 18 +-----------------
2 files changed, 11 insertions(+), 24 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 3e48d558a..b53083524 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -127,6 +127,7 @@ pub trait DacChannel {
}
/// Set mode register of the given channel
+ #[cfg(dac_v2)]
fn set_channel_mode(&mut self, val: u8) -> Result<(), Error> {
T::regs().mcr().modify(|reg| {
reg.set_mode(Self::CHANNEL.index(), val);
@@ -221,6 +222,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
// Configure each activated channel. All results can be `unwrap`ed since they
// will only error if the channel is not configured (i.e. ch1, ch2 are false)
+ #[cfg(dac_v2)]
dac.set_channel_mode(0).unwrap();
dac.enable_channel().unwrap();
dac.set_trigger_enable(true).unwrap();
@@ -334,6 +336,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
// Configure each activated channel. All results can be `unwrap`ed since they
// will only error if the channel is not configured (i.e. ch1, ch2 are false)
+ #[cfg(dac_v2)]
dac.set_channel_mode(0).unwrap();
dac.enable_channel().unwrap();
dac.set_trigger_enable(true).unwrap();
@@ -454,10 +457,12 @@ impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
// Configure each activated channel. All results can be `unwrap`ed since they
// will only error if the channel is not configured (i.e. ch1, ch2 are false)
+ #[cfg(dac_v2)]
dac_ch1.set_channel_mode(0).unwrap();
dac_ch1.enable_channel().unwrap();
dac_ch1.set_trigger_enable(true).unwrap();
+ #[cfg(dac_v2)]
dac_ch2.set_channel_mode(0).unwrap();
dac_ch2.enable_channel().unwrap();
dac_ch2.set_trigger_enable(true).unwrap();
@@ -521,27 +526,25 @@ foreach_peripheral!(
#[cfg(rcc_h7)]
impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
fn frequency() -> crate::time::Hertz {
- critical_section::with(|_| unsafe {
- crate::rcc::get_freqs().apb1
- })
+ critical_section::with(|_| crate::rcc::get_freqs().apb1)
}
fn reset() {
- critical_section::with(|_| unsafe {
+ critical_section::with(|_| {
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(true));
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(false));
})
}
fn enable() {
- critical_section::with(|_| unsafe {
+ critical_section::with(|_| {
crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true));
})
}
fn disable() {
- critical_section::with(|_| unsafe {
- crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(false));
+ critical_section::with(|_| {
+ crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(false))
})
}
}
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
index a5f828948..0b7b60789 100644
--- a/embassy-stm32/src/dma/dma.rs
+++ b/embassy-stm32/src/dma/dma.rs
@@ -29,12 +29,6 @@ pub struct TransferOptions {
pub flow_ctrl: FlowControl,
/// FIFO threshold for DMA FIFO mode. If none, direct mode is used.
pub fifo_threshold: Option,
- /// Enable circular DMA
- pub circular: bool,
- /// Enable half transfer interrupt
- pub half_transfer_ir: bool,
- /// Enable transfer complete interrupt
- pub complete_transfer_ir: bool,
}
impl Default for TransferOptions {
@@ -44,9 +38,6 @@ impl Default for TransferOptions {
mburst: Burst::Single,
flow_ctrl: FlowControl::Dma,
fifo_threshold: None,
- circular: false,
- half_transfer_ir: false,
- complete_transfer_ir: true,
}
}
}
@@ -375,20 +366,13 @@ impl<'a, C: Channel> Transfer<'a, C> {
});
w.set_pinc(vals::Inc::FIXED);
w.set_teie(true);
- w.set_tcie(options.complete_transfer_ir);
- w.set_htie(options.half_transfer_ir);
+ w.set_tcie(true);
#[cfg(dma_v1)]
w.set_trbuff(true);
#[cfg(dma_v2)]
w.set_chsel(_request);
- if options.circular {
- w.set_circ(vals::Circ::ENABLED);
- debug!("Setting circular mode");
- } else {
- w.set_circ(vals::Circ::DISABLED);
- }
w.set_pburst(options.pburst.into());
w.set_mburst(options.mburst.into());
w.set_pfctrl(options.flow_ctrl.into());
From 60c54107ce5cc50f9d9365297d31973d96f00021 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Tue, 27 Jun 2023 21:58:56 +0200
Subject: [PATCH 25/48] fix sdmmc bdma transferconfig fields
---
embassy-stm32/src/sdmmc/mod.rs | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index 80a336a48..698292bff 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -227,7 +227,11 @@ const DMA_TRANSFER_OPTIONS: crate::dma::TransferOptions = crate::dma::TransferOp
fifo_threshold: Some(crate::dma::FifoThreshold::Full),
};
#[cfg(all(sdmmc_v1, not(dma)))]
-const DMA_TRANSFER_OPTIONS: crate::dma::TransferOptions = crate::dma::TransferOptions {};
+const DMA_TRANSFER_OPTIONS: crate::dma::TransferOptions = crate::dma::TransferOptions {
+ circular: false,
+ half_transfer_ir: false,
+ complete_transfer_ir: true,
+};
/// SDMMC configuration
///
From 9c81d6315500b236adc7634d2d2d6ef776f984eb Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Tue, 27 Jun 2023 22:33:17 +0200
Subject: [PATCH 26/48] fix warnings
---
embassy-stm32/src/dac/mod.rs | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index b53083524..6686a387a 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -5,7 +5,6 @@ use core::marker::PhantomData;
use embassy_hal_common::{into_ref, PeripheralRef};
-use crate::dma::{Transfer, TransferOptions};
use crate::pac::dac;
use crate::rcc::RccPeripheral;
use crate::{peripherals, Peripheral};
@@ -195,6 +194,7 @@ pub struct Dac<'d, T: Instance, TxCh1, TxCh2> {
pub struct DacCh1<'d, T: Instance, Tx> {
/// To consume T
_peri: PeripheralRef<'d, T>,
+ #[allow(unused)] // For chips whose DMA is not (yet) supported
dma: PeripheralRef<'d, Tx>,
}
@@ -204,6 +204,7 @@ pub struct DacCh1<'d, T: Instance, Tx> {
pub struct DacCh2<'d, T: Instance, Tx> {
/// Instead of PeripheralRef to consume T
phantom: PhantomData<&'d mut T>,
+ #[allow(unused)] // For chips whose DMA is not (yet) supported
dma: PeripheralRef<'d, Tx>,
}
@@ -265,7 +266,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
let tx_request = self.dma.request();
let dma_channel = &self.dma;
- let tx_options = TransferOptions {
+ let tx_options = crate::dma::TransferOptions {
circular,
half_transfer_ir: false,
complete_transfer_ir: !circular,
@@ -275,7 +276,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
// Initiate the correct type of DMA transfer depending on what data is passed
let tx_f = match data {
ValueArray::Bit8(buf) => unsafe {
- Transfer::new_write(
+ crate::dma::Transfer::new_write(
dma_channel,
tx_request,
buf,
@@ -284,7 +285,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
)
},
ValueArray::Bit12Left(buf) => unsafe {
- Transfer::new_write(
+ crate::dma::Transfer::new_write(
dma_channel,
tx_request,
buf,
@@ -293,7 +294,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
)
},
ValueArray::Bit12Right(buf) => unsafe {
- Transfer::new_write(
+ crate::dma::Transfer::new_write(
dma_channel,
tx_request,
buf,
@@ -377,7 +378,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
let tx_request = self.dma.request();
let dma_channel = &self.dma;
- let tx_options = TransferOptions {
+ let tx_options = crate::dma::TransferOptions {
circular,
half_transfer_ir: false,
complete_transfer_ir: !circular,
@@ -387,7 +388,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
// Initiate the correct type of DMA transfer depending on what data is passed
let tx_f = match data {
ValueArray::Bit8(buf) => unsafe {
- Transfer::new_write(
+ crate::dma::Transfer::new_write(
dma_channel,
tx_request,
buf,
@@ -396,7 +397,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
)
},
ValueArray::Bit12Left(buf) => unsafe {
- Transfer::new_write(
+ crate::dma::Transfer::new_write(
dma_channel,
tx_request,
buf,
@@ -405,7 +406,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
)
},
ValueArray::Bit12Right(buf) => unsafe {
- Transfer::new_write(
+ crate::dma::Transfer::new_write(
dma_channel,
tx_request,
buf,
@@ -526,7 +527,7 @@ foreach_peripheral!(
#[cfg(rcc_h7)]
impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
fn frequency() -> crate::time::Hertz {
- critical_section::with(|_| crate::rcc::get_freqs().apb1)
+ critical_section::with(|_| unsafe { crate::rcc::get_freqs().apb1 })
}
fn reset() {
From f5ca687e9bbeb81ce24f56db6cd7defbcb5c2db2 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Tue, 27 Jun 2023 23:49:12 +0200
Subject: [PATCH 27/48] sync/pipe: fix doc typos.
---
embassy-sync/src/pipe.rs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-sync/src/pipe.rs b/embassy-sync/src/pipe.rs
index db6ebb08b..13bf4ef01 100644
--- a/embassy-sync/src/pipe.rs
+++ b/embassy-sync/src/pipe.rs
@@ -282,7 +282,7 @@ where
/// returns the amount of bytes written.
///
/// If it is not possible to write a nonzero amount of bytes because the pipe's buffer is full,
- /// this method will wait until it is. See [`try_write`](Self::try_write) for a variant that
+ /// this method will wait until it isn't. See [`try_write`](Self::try_write) for a variant that
/// returns an error instead of waiting.
///
/// It is not guaranteed that all bytes in the buffer are written, even if there's enough
@@ -319,7 +319,7 @@ where
/// returns the amount of bytes read.
///
/// If it is not possible to read a nonzero amount of bytes because the pipe's buffer is empty,
- /// this method will wait until it is. See [`try_read`](Self::try_read) for a variant that
+ /// this method will wait until it isn't. See [`try_read`](Self::try_read) for a variant that
/// returns an error instead of waiting.
///
/// It is not guaranteed that all bytes in the buffer are read, even if there's enough
From ed493be869fa653dc14d31060375e17e2469ce11 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Tue, 27 Jun 2023 23:49:30 +0200
Subject: [PATCH 28/48] stm32: update metapac, includes fix for OTG with 9
endpoints (H7)
---
embassy-stm32/Cargo.toml | 4 ++--
embassy-stm32/src/rcc/l0.rs | 4 ++--
examples/stm32g4/src/bin/usb_serial.rs | 4 +++-
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 3d9ee8261..f15c6d0b7 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -57,7 +57,7 @@ sdio-host = "0.5.0"
embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
critical-section = "1.1"
atomic-polyfill = "1.0.1"
-stm32-metapac = "10"
+stm32-metapac = "11"
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -74,7 +74,7 @@ critical-section = { version = "1.1", features = ["std"] }
[build-dependencies]
proc-macro2 = "1.0.36"
quote = "1.0.15"
-stm32-metapac = { version = "10", default-features = false, features = ["metadata"]}
+stm32-metapac = { version = "11", default-features = false, features = ["metadata"]}
[features]
default = ["rt"]
diff --git a/embassy-stm32/src/rcc/l0.rs b/embassy-stm32/src/rcc/l0.rs
index 42a481a74..d53b61069 100644
--- a/embassy-stm32/src/rcc/l0.rs
+++ b/embassy-stm32/src/rcc/l0.rs
@@ -1,7 +1,7 @@
use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
use crate::pac::RCC;
#[cfg(crs)]
-use crate::pac::{CRS, SYSCFG};
+use crate::pac::{crs, CRS, SYSCFG};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@@ -338,7 +338,7 @@ pub(crate) unsafe fn init(config: Config) {
CRS.cfgr().write(|w|
// Select LSE as synchronization source
- w.set_syncsrc(0b01));
+ w.set_syncsrc(crs::vals::Syncsrc::LSE));
CRS.cr().modify(|w| {
w.set_autotrimen(true);
w.set_cen(true);
diff --git a/examples/stm32g4/src/bin/usb_serial.rs b/examples/stm32g4/src/bin/usb_serial.rs
index c111a9787..289d0ed86 100644
--- a/examples/stm32g4/src/bin/usb_serial.rs
+++ b/examples/stm32g4/src/bin/usb_serial.rs
@@ -38,7 +38,9 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(config);
info!("Hello World!");
- pac::RCC.ccipr().write(|w| w.set_clk48sel(0b10));
+ pac::RCC.ccipr().write(|w| {
+ w.set_clk48sel(pac::rcc::vals::Clk48sel::PLLQCLK);
+ });
let driver = Driver::new(p.USB, Irqs, p.PA12, p.PA11);
From 91c31d5e437b510af3c535f5e597881042563496 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Wed, 28 Jun 2023 11:58:25 +0200
Subject: [PATCH 29/48] Update DAC examples, add DAC + DMA example
---
embassy-stm32/src/dac/mod.rs | 2 +-
examples/stm32f4/src/bin/dac.rs | 9 +-
examples/stm32h7/src/bin/dac.rs | 9 +-
examples/stm32l4/Cargo.toml | 2 +
examples/stm32l4/src/bin/dac.rs | 16 ++-
examples/stm32l4/src/bin/dac_dma.rs | 148 ++++++++++++++++++++++++++++
6 files changed, 167 insertions(+), 19 deletions(-)
create mode 100644 examples/stm32l4/src/bin/dac_dma.rs
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 6686a387a..1dc13949d 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -178,7 +178,7 @@ pub trait DacChannel {
///
/// # Example for obtaining both DAC channels
///
-/// ```no_run
+/// ```ignore
/// // DMA channels and pins may need to be changed for your controller
/// let (dac_ch1, dac_ch2) =
/// embassy_stm32::dac::Dac::new(p.DAC1, p.DMA1_CH3, p.DMA1_CH4, p.PA4, p.PA5).split();
diff --git a/examples/stm32f4/src/bin/dac.rs b/examples/stm32f4/src/bin/dac.rs
index d97ae7082..3a6216712 100644
--- a/examples/stm32f4/src/bin/dac.rs
+++ b/examples/stm32f4/src/bin/dac.rs
@@ -4,7 +4,8 @@
use defmt::*;
use embassy_executor::Spawner;
-use embassy_stm32::dac::{Channel, Dac, Value};
+use embassy_stm32::dac::{DacCh1, DacChannel, Value};
+use embassy_stm32::dma::NoDma;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,12 +13,12 @@ async fn main(_spawner: Spawner) -> ! {
let p = embassy_stm32::init(Default::default());
info!("Hello World, dude!");
- let mut dac = Dac::new_1ch(p.DAC, p.PA4);
+ let mut dac = DacCh1::new(p.DAC, NoDma, p.PA4);
loop {
for v in 0..=255 {
- unwrap!(dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v))));
- unwrap!(dac.trigger(Channel::Ch1));
+ unwrap!(dac.set(Value::Bit8(to_sine_wave(v))));
+ dac.trigger();
}
}
}
diff --git a/examples/stm32h7/src/bin/dac.rs b/examples/stm32h7/src/bin/dac.rs
index f12716370..586b4154b 100644
--- a/examples/stm32h7/src/bin/dac.rs
+++ b/examples/stm32h7/src/bin/dac.rs
@@ -4,7 +4,8 @@
use cortex_m_rt::entry;
use defmt::*;
-use embassy_stm32::dac::{Channel, Dac, Value};
+use embassy_stm32::dac::{DacCh1, DacChannel, Value};
+use embassy_stm32::dma::NoDma;
use embassy_stm32::time::mhz;
use embassy_stm32::Config;
use {defmt_rtt as _, panic_probe as _};
@@ -19,12 +20,12 @@ fn main() -> ! {
config.rcc.pll1.q_ck = Some(mhz(100));
let p = embassy_stm32::init(config);
- let mut dac = Dac::new_1ch(p.DAC1, p.PA4);
+ let mut dac = DacCh1::new(p.DAC1, NoDma, p.PA4);
loop {
for v in 0..=255 {
- unwrap!(dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v))));
- unwrap!(dac.trigger(Channel::Ch1));
+ unwrap!(dac.set(Value::Bit8(to_sine_wave(v))));
+ dac.trigger();
}
}
}
diff --git a/examples/stm32l4/Cargo.toml b/examples/stm32l4/Cargo.toml
index 3bb473ef5..d2d228282 100644
--- a/examples/stm32l4/Cargo.toml
+++ b/examples/stm32l4/Cargo.toml
@@ -25,3 +25,5 @@ futures = { version = "0.3.17", default-features = false, features = ["async-awa
heapless = { version = "0.7.5", default-features = false }
micromath = "2.0.0"
+
+static_cell = "1.0.0"
diff --git a/examples/stm32l4/src/bin/dac.rs b/examples/stm32l4/src/bin/dac.rs
index a36ed5d90..8aad27646 100644
--- a/examples/stm32l4/src/bin/dac.rs
+++ b/examples/stm32l4/src/bin/dac.rs
@@ -3,26 +3,22 @@
#![feature(type_alias_impl_trait)]
use defmt::*;
-use embassy_stm32::dac::{Channel, Dac, Value};
+use embassy_stm32::dac::{DacCh1, DacChannel, Value};
+use embassy_stm32::dma::NoDma;
use embassy_stm32::pac;
use {defmt_rtt as _, panic_probe as _};
#[cortex_m_rt::entry]
fn main() -> ! {
+ let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- pac::RCC.apb1enr1().modify(|w| {
- w.set_dac1en(true);
- });
-
- let p = embassy_stm32::init(Default::default());
-
- let mut dac = Dac::new_1ch(p.DAC1, p.PA4);
+ let mut dac = DacCh1::new(p.DAC1, NoDma, p.PA4);
loop {
for v in 0..=255 {
- unwrap!(dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v))));
- unwrap!(dac.trigger(Channel::Ch1));
+ unwrap!(dac.set(Value::Bit8(to_sine_wave(v))));
+ dac.trigger();
}
}
}
diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs
new file mode 100644
index 000000000..81e6a58e4
--- /dev/null
+++ b/examples/stm32l4/src/bin/dac_dma.rs
@@ -0,0 +1,148 @@
+#![no_std]
+#![no_main]
+#![feature(type_alias_impl_trait)]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::dac::{DacChannel, ValueArray};
+use embassy_stm32::pac::timer::vals::{Mms, Opm};
+use embassy_stm32::peripherals::{TIM6, TIM7};
+use embassy_stm32::rcc::low_level::RccPeripheral;
+use embassy_stm32::time::Hertz;
+use embassy_stm32::timer::low_level::Basic16bitInstance;
+use micromath::F32Ext;
+use static_cell::StaticCell;
+use {defmt_rtt as _, panic_probe as _};
+
+pub type Dac1Type<'d> =
+ embassy_stm32::dac::DacCh1<'d, embassy_stm32::peripherals::DAC1, embassy_stm32::peripherals::DMA1_CH3>;
+
+pub type Dac2Type<'d> =
+ embassy_stm32::dac::DacCh2<'d, embassy_stm32::peripherals::DAC1, embassy_stm32::peripherals::DMA1_CH4>;
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+ let config = embassy_stm32::Config::default();
+
+ // Initialize the board and obtain a Peripherals instance
+ let p: embassy_stm32::Peripherals = embassy_stm32::init(config);
+
+ // Obtain two independent channels (p.DAC1 can only be consumed once, though!)
+ let (dac_ch1, dac_ch2) = embassy_stm32::dac::Dac::new(p.DAC1, p.DMA1_CH3, p.DMA1_CH4, p.PA4, p.PA5).split();
+
+ let dac1 = {
+ type T = impl Sized;
+ static STATIC_CELL: StaticCell = StaticCell::new();
+ STATIC_CELL.init(dac_ch1)
+ };
+
+ let dac2 = {
+ type T = impl Sized;
+ static STATIC_CELL: StaticCell = StaticCell::new();
+ STATIC_CELL.init(dac_ch2)
+ };
+
+ spawner.spawn(dac_task1(dac1)).ok();
+ spawner.spawn(dac_task2(dac2)).ok();
+}
+
+#[embassy_executor::task]
+async fn dac_task1(dac: &'static mut Dac1Type<'static>) {
+ let data: &[u8; 256] = &calculate_array::<256>();
+
+ info!("TIM6 frequency is {}", TIM6::frequency());
+ const FREQUENCY: Hertz = Hertz::hz(200);
+ let reload: u32 = (TIM6::frequency().0 / FREQUENCY.0) / data.len() as u32;
+
+ // Depends on your clock and on the specific chip used, you may need higher or lower values here
+ if reload < 10 {
+ error!("Reload value {} below threshold!", reload);
+ }
+
+ dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap();
+ dac.enable_channel().unwrap();
+
+ TIM6::enable();
+ TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
+ TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
+ TIM6::regs().cr1().modify(|w| {
+ w.set_opm(Opm::DISABLED);
+ w.set_cen(true);
+ });
+
+ debug!(
+ "TIM6 Frequency {}, Target Frequency {}, Reload {}, Reload as u16 {}, Samples {}",
+ TIM6::frequency(),
+ FREQUENCY,
+ reload,
+ reload as u16,
+ data.len()
+ );
+
+ // Loop technically not necessary if DMA circular mode is enabled
+ loop {
+ info!("Loop DAC1");
+ if let Err(e) = dac.write(ValueArray::Bit8(data), true).await {
+ error!("Could not write to dac: {}", e);
+ }
+ }
+}
+
+#[embassy_executor::task]
+async fn dac_task2(dac: &'static mut Dac2Type<'static>) {
+ let data: &[u8; 256] = &calculate_array::<256>();
+
+ info!("TIM7 frequency is {}", TIM7::frequency());
+
+ const FREQUENCY: Hertz = Hertz::hz(600);
+ let reload: u32 = (TIM7::frequency().0 / FREQUENCY.0) / data.len() as u32;
+
+ if reload < 10 {
+ error!("Reload value {} below threshold!", reload);
+ }
+
+ TIM7::enable();
+ TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
+ TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
+ TIM7::regs().cr1().modify(|w| {
+ w.set_opm(Opm::DISABLED);
+ w.set_cen(true);
+ });
+
+ dac.select_trigger(embassy_stm32::dac::Ch2Trigger::Tim7).unwrap();
+
+ debug!(
+ "TIM7 Frequency {}, Target Frequency {}, Reload {}, Reload as u16 {}, Samples {}",
+ TIM7::frequency(),
+ FREQUENCY,
+ reload,
+ reload as u16,
+ data.len()
+ );
+
+ if let Err(e) = dac.write(ValueArray::Bit8(data), true).await {
+ error!("Could not write to dac: {}", e);
+ }
+}
+
+fn to_sine_wave(v: u8) -> u8 {
+ if v >= 128 {
+ // top half
+ let r = 3.14 * ((v - 128) as f32 / 128.0);
+ (r.sin() * 128.0 + 127.0) as u8
+ } else {
+ // bottom half
+ let r = 3.14 + 3.14 * (v as f32 / 128.0);
+ (r.sin() * 128.0 + 127.0) as u8
+ }
+}
+
+fn calculate_array() -> [u8; N] {
+ let mut res = [0; N];
+ let mut i = 0;
+ while i < N {
+ res[i] = to_sine_wave(i as u8);
+ i += 1;
+ }
+ res
+}
From 59f829c6cce3427f95b7c5b137f62f8af0c3c40f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?D=C3=A1niel=20Buga?=
Date: Wed, 28 Jun 2023 15:03:57 +0200
Subject: [PATCH 30/48] Make StackResources::new() const
---
embassy-net/src/lib.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-net/src/lib.rs b/embassy-net/src/lib.rs
index 3e83da7aa..17a7a22a2 100644
--- a/embassy-net/src/lib.rs
+++ b/embassy-net/src/lib.rs
@@ -57,7 +57,7 @@ pub struct StackResources {
impl StackResources {
/// Create a new set of stack resources.
- pub fn new() -> Self {
+ pub const fn new() -> Self {
#[cfg(feature = "dns")]
const INIT: Option = None;
Self {
From 27a89019adaebfd1916d3b71dde1db3a6a768883 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Wed, 28 Jun 2023 15:21:24 +0200
Subject: [PATCH 31/48] add doc
---
examples/stm32l4/src/bin/dac_dma.rs | 2 ++
1 file changed, 2 insertions(+)
diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs
index 81e6a58e4..aefc8412f 100644
--- a/examples/stm32l4/src/bin/dac_dma.rs
+++ b/examples/stm32l4/src/bin/dac_dma.rs
@@ -52,6 +52,8 @@ async fn dac_task1(dac: &'static mut Dac1Type<'static>) {
info!("TIM6 frequency is {}", TIM6::frequency());
const FREQUENCY: Hertz = Hertz::hz(200);
+
+ // Compute the reload value such that we obtain the FREQUENCY for the sine
let reload: u32 = (TIM6::frequency().0 / FREQUENCY.0) / data.len() as u32;
// Depends on your clock and on the specific chip used, you may need higher or lower values here
From f2e7a23148f0c1f663744bfe47fbbb37d9552080 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Wed, 28 Jun 2023 15:25:57 +0200
Subject: [PATCH 32/48] attempt at fixing ci
---
examples/stm32l4/.cargo/config.toml | 3 ++-
examples/stm32l4/memory.x | 8 ++++----
examples/stm32l4/src/bin/dac_dma.rs | 2 +-
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/examples/stm32l4/.cargo/config.toml b/examples/stm32l4/.cargo/config.toml
index abf55eb2e..4ccdf121e 100644
--- a/examples/stm32l4/.cargo/config.toml
+++ b/examples/stm32l4/.cargo/config.toml
@@ -2,7 +2,8 @@
# replace STM32F429ZITx with your chip as listed in `probe-rs-cli chip list`
#runner = "probe-rs-cli run --chip STM32L475VGT6"
#runner = "probe-rs-cli run --chip STM32L475VG"
-runner = "probe-rs-cli run --chip STM32L4S5VI"
+#runner = "probe-rs-cli run --chip STM32L4S5VI"
+runner = "probe-run --chip STM32L432KCUx"
[build]
target = "thumbv7em-none-eabi"
diff --git a/examples/stm32l4/memory.x b/examples/stm32l4/memory.x
index eb87d1b54..0cef526ae 100644
--- a/examples/stm32l4/memory.x
+++ b/examples/stm32l4/memory.x
@@ -1,7 +1,7 @@
MEMORY
{
- /* NOTE 1 K = 1 KiBi = 1024 bytes */
- /* These values correspond to the STM32L4S5 */
- FLASH : ORIGIN = 0x08000000, LENGTH = 1024K
- RAM : ORIGIN = 0x20000000, LENGTH = 128K
+ /* NOTE K = KiBi = 1024 bytes */
+ /* TODO Adjust these memory regions to match your device memory layout */
+ FLASH : ORIGIN = 0x8000000, LENGTH = 256K
+ RAM : ORIGIN = 0x20000000, LENGTH = 64K
}
diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs
index aefc8412f..7c0df835b 100644
--- a/examples/stm32l4/src/bin/dac_dma.rs
+++ b/examples/stm32l4/src/bin/dac_dma.rs
@@ -93,7 +93,7 @@ async fn dac_task1(dac: &'static mut Dac1Type<'static>) {
#[embassy_executor::task]
async fn dac_task2(dac: &'static mut Dac2Type<'static>) {
let data: &[u8; 256] = &calculate_array::<256>();
-
+
info!("TIM7 frequency is {}", TIM7::frequency());
const FREQUENCY: Hertz = Hertz::hz(600);
From 02f367f733591c9423731a86ea7726772a88dac0 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Wed, 28 Jun 2023 15:28:10 +0200
Subject: [PATCH 33/48] attempt at fixing ci
---
examples/stm32l4/src/bin/dac.rs | 1 -
1 file changed, 1 deletion(-)
diff --git a/examples/stm32l4/src/bin/dac.rs b/examples/stm32l4/src/bin/dac.rs
index 8aad27646..ade43eb35 100644
--- a/examples/stm32l4/src/bin/dac.rs
+++ b/examples/stm32l4/src/bin/dac.rs
@@ -5,7 +5,6 @@
use defmt::*;
use embassy_stm32::dac::{DacCh1, DacChannel, Value};
use embassy_stm32::dma::NoDma;
-use embassy_stm32::pac;
use {defmt_rtt as _, panic_probe as _};
#[cortex_m_rt::entry]
From bf7e24e9d7abc5d31b75ef97418577920bd4600c Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Wed, 28 Jun 2023 15:37:29 +0200
Subject: [PATCH 34/48] revert to STM32L4S5VI
---
examples/stm32l4/.cargo/config.toml | 3 +--
examples/stm32l4/memory.x | 8 ++++----
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/examples/stm32l4/.cargo/config.toml b/examples/stm32l4/.cargo/config.toml
index 4ccdf121e..abf55eb2e 100644
--- a/examples/stm32l4/.cargo/config.toml
+++ b/examples/stm32l4/.cargo/config.toml
@@ -2,8 +2,7 @@
# replace STM32F429ZITx with your chip as listed in `probe-rs-cli chip list`
#runner = "probe-rs-cli run --chip STM32L475VGT6"
#runner = "probe-rs-cli run --chip STM32L475VG"
-#runner = "probe-rs-cli run --chip STM32L4S5VI"
-runner = "probe-run --chip STM32L432KCUx"
+runner = "probe-rs-cli run --chip STM32L4S5VI"
[build]
target = "thumbv7em-none-eabi"
diff --git a/examples/stm32l4/memory.x b/examples/stm32l4/memory.x
index 0cef526ae..eb87d1b54 100644
--- a/examples/stm32l4/memory.x
+++ b/examples/stm32l4/memory.x
@@ -1,7 +1,7 @@
MEMORY
{
- /* NOTE K = KiBi = 1024 bytes */
- /* TODO Adjust these memory regions to match your device memory layout */
- FLASH : ORIGIN = 0x8000000, LENGTH = 256K
- RAM : ORIGIN = 0x20000000, LENGTH = 64K
+ /* NOTE 1 K = 1 KiBi = 1024 bytes */
+ /* These values correspond to the STM32L4S5 */
+ FLASH : ORIGIN = 0x08000000, LENGTH = 1024K
+ RAM : ORIGIN = 0x20000000, LENGTH = 128K
}
From daedfbbd8756e921cc6343ad531401d309966eaa Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Wed, 28 Jun 2023 15:39:36 +0200
Subject: [PATCH 35/48] add dma is_running change doc
---
embassy-stm32/src/dma/dma.rs | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
index 0b7b60789..9c03599eb 100644
--- a/embassy-stm32/src/dma/dma.rs
+++ b/embassy-stm32/src/dma/dma.rs
@@ -404,11 +404,9 @@ impl<'a, C: Channel> Transfer<'a, C> {
}
pub fn is_running(&mut self) -> bool {
- //let ch = self.channel.regs().st(self.channel.num());
- //ch.cr().read().en()
-
let ch = self.channel.regs().st(self.channel.num());
let en = ch.cr().read().en();
+ // Check if circular mode is enabled, if so it will still be running even if tcif == 1
let circular = ch.cr().read().circ() == vals::Circ::ENABLED;
let tcif = STATE.complete_count[self.channel.index()].load(Ordering::Acquire) != 0;
en && (circular || !tcif)
From d5898c11ebef63fa0ec6dba8381484f4cfabd65c Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Wed, 28 Jun 2023 16:40:50 +0200
Subject: [PATCH 36/48] remove need for StaticCell in dac_dma example for
stm32l4
---
examples/stm32l4/Cargo.toml | 2 --
examples/stm32l4/src/bin/dac_dma.rs | 29 ++++++++---------------------
2 files changed, 8 insertions(+), 23 deletions(-)
diff --git a/examples/stm32l4/Cargo.toml b/examples/stm32l4/Cargo.toml
index d2d228282..3bb473ef5 100644
--- a/examples/stm32l4/Cargo.toml
+++ b/examples/stm32l4/Cargo.toml
@@ -25,5 +25,3 @@ futures = { version = "0.3.17", default-features = false, features = ["async-awa
heapless = { version = "0.7.5", default-features = false }
micromath = "2.0.0"
-
-static_cell = "1.0.0"
diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs
index 7c0df835b..c27cc03e1 100644
--- a/examples/stm32l4/src/bin/dac_dma.rs
+++ b/examples/stm32l4/src/bin/dac_dma.rs
@@ -11,14 +11,13 @@ use embassy_stm32::rcc::low_level::RccPeripheral;
use embassy_stm32::time::Hertz;
use embassy_stm32::timer::low_level::Basic16bitInstance;
use micromath::F32Ext;
-use static_cell::StaticCell;
use {defmt_rtt as _, panic_probe as _};
-pub type Dac1Type<'d> =
- embassy_stm32::dac::DacCh1<'d, embassy_stm32::peripherals::DAC1, embassy_stm32::peripherals::DMA1_CH3>;
+pub type Dac1Type =
+ embassy_stm32::dac::DacCh1<'static, embassy_stm32::peripherals::DAC1, embassy_stm32::peripherals::DMA1_CH3>;
-pub type Dac2Type<'d> =
- embassy_stm32::dac::DacCh2<'d, embassy_stm32::peripherals::DAC1, embassy_stm32::peripherals::DMA1_CH4>;
+pub type Dac2Type =
+ embassy_stm32::dac::DacCh2<'static, embassy_stm32::peripherals::DAC1, embassy_stm32::peripherals::DMA1_CH4>;
#[embassy_executor::main]
async fn main(spawner: Spawner) {
@@ -30,24 +29,12 @@ async fn main(spawner: Spawner) {
// Obtain two independent channels (p.DAC1 can only be consumed once, though!)
let (dac_ch1, dac_ch2) = embassy_stm32::dac::Dac::new(p.DAC1, p.DMA1_CH3, p.DMA1_CH4, p.PA4, p.PA5).split();
- let dac1 = {
- type T = impl Sized;
- static STATIC_CELL: StaticCell = StaticCell::new();
- STATIC_CELL.init(dac_ch1)
- };
-
- let dac2 = {
- type T = impl Sized;
- static STATIC_CELL: StaticCell = StaticCell::new();
- STATIC_CELL.init(dac_ch2)
- };
-
- spawner.spawn(dac_task1(dac1)).ok();
- spawner.spawn(dac_task2(dac2)).ok();
+ spawner.spawn(dac_task1(dac_ch1)).ok();
+ spawner.spawn(dac_task2(dac_ch2)).ok();
}
#[embassy_executor::task]
-async fn dac_task1(dac: &'static mut Dac1Type<'static>) {
+async fn dac_task1(mut dac: Dac1Type) {
let data: &[u8; 256] = &calculate_array::<256>();
info!("TIM6 frequency is {}", TIM6::frequency());
@@ -91,7 +78,7 @@ async fn dac_task1(dac: &'static mut Dac1Type<'static>) {
}
#[embassy_executor::task]
-async fn dac_task2(dac: &'static mut Dac2Type<'static>) {
+async fn dac_task2(mut dac: Dac2Type) {
let data: &[u8; 256] = &calculate_array::<256>();
info!("TIM7 frequency is {}", TIM7::frequency());
From 5666c569033d59fc894230ed4161e6c686733b2d Mon Sep 17 00:00:00 2001
From: Kevin Lannen
Date: Wed, 28 Jun 2023 13:05:39 -0600
Subject: [PATCH 37/48] STM32G4: Add CRS support to RCC
Create working CRS USB Example
---
embassy-stm32/src/rcc/g4.rs | 77 +++++++++++++++++++++++++-
examples/stm32g4/src/bin/usb_serial.rs | 30 ++++++----
2 files changed, 96 insertions(+), 11 deletions(-)
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 9401af4c3..ff8f97541 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -3,6 +3,7 @@ use stm32_metapac::rcc::vals::{Hpre, Pllsrc, Ppre, Sw};
use stm32_metapac::FLASH;
use crate::pac::{PWR, RCC};
+use crate::rcc::sealed::RccPeripheral;
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@@ -316,6 +317,27 @@ impl Into for AHBPrescaler {
}
}
+/// Sets the source for the 48MHz clock to the USB and RNG peripherals.
+pub enum Clock48MhzSrc {
+ /// Use the High Speed Internal Oscillator. For USB usage, the CRS must be used to calibrate the
+ /// oscillator to comply with the USB specification for oscillator tolerance.
+ Hsi48(Option),
+ /// Use the PLLQ output. The PLL must be configured to output a 48MHz clock. For USB usage the
+ /// PLL needs to be using the HSE source to comply with the USB specification for oscillator
+ /// tolerance.
+ PllQ,
+}
+
+/// Sets the sync source for the Clock Recovery System (CRS).
+pub enum CrsSyncSource {
+ /// Use an external GPIO to sync the CRS.
+ Gpio,
+ /// Use the Low Speed External oscillator to sync the CRS.
+ Lse,
+ /// Use the USB SOF to sync the CRS.
+ Usb,
+}
+
/// Clocks configutation
pub struct Config {
pub mux: ClockSrc,
@@ -326,6 +348,14 @@ pub struct Config {
/// Iff PLL is requested as the main clock source in the `mux` field then the PLL configuration
/// MUST turn on the PLLR output.
pub pll: Option,
+ /// Sets the clock source for the 48MHz clock used by the USB and RNG peripherals.
+ pub clock_48mhz_src: Option,
+}
+
+/// Configuration for the Clock Recovery System (CRS) used to trim the HSI48 oscillator.
+pub struct CrsConfig {
+ /// Sync source for the CRS.
+ pub sync_src: CrsSyncSource,
}
impl Default for Config {
@@ -338,6 +368,7 @@ impl Default for Config {
apb2_pre: APBPrescaler::NotDivided,
low_power_run: false,
pll: None,
+ clock_48mhz_src: None,
}
}
}
@@ -430,7 +461,7 @@ pub(crate) unsafe fn init(config: Config) {
assert!(pll_freq.is_some());
assert!(pll_freq.as_ref().unwrap().pll_r.is_some());
- let freq = pll_freq.unwrap().pll_r.unwrap().0;
+ let freq = pll_freq.as_ref().unwrap().pll_r.unwrap().0;
assert!(freq <= 170_000_000);
@@ -497,6 +528,50 @@ pub(crate) unsafe fn init(config: Config) {
}
};
+ // Setup the 48 MHz clock if needed
+ if let Some(clock_48mhz_src) = config.clock_48mhz_src {
+ let source = match clock_48mhz_src {
+ Clock48MhzSrc::PllQ => {
+ // Make sure the PLLQ is enabled and running at 48Mhz
+ let pllq_freq = pll_freq.as_ref().and_then(|f| f.pll_q);
+ assert!(pllq_freq.is_some() && pllq_freq.unwrap().0 == 48_000_000);
+
+ crate::pac::rcc::vals::Clk48sel::PLLQCLK
+ }
+ Clock48MhzSrc::Hsi48(crs_config) => {
+ // Enable HSI48
+ RCC.crrcr().modify(|w| w.set_hsi48on(true));
+ // Wait for HSI48 to turn on
+ while RCC.crrcr().read().hsi48rdy() == false {}
+
+ // Enable and setup CRS if needed
+ if let Some(crs_config) = crs_config {
+ crate::peripherals::CRS::enable();
+
+ let sync_src = match crs_config.sync_src {
+ CrsSyncSource::Gpio => crate::pac::crs::vals::Syncsrc::GPIO,
+ CrsSyncSource::Lse => crate::pac::crs::vals::Syncsrc::LSE,
+ CrsSyncSource::Usb => crate::pac::crs::vals::Syncsrc::USB,
+ };
+
+ crate::pac::CRS.cfgr().modify(|w| {
+ w.set_syncsrc(sync_src);
+ });
+
+ // These are the correct settings for standard USB operation. If other settings
+ // are needed there will need to be additional config options for the CRS.
+ crate::pac::CRS.cr().modify(|w| {
+ w.set_autotrimen(true);
+ w.set_cen(true);
+ });
+ }
+ crate::pac::rcc::vals::Clk48sel::HSI48
+ }
+ };
+
+ RCC.ccipr().modify(|w| w.set_clk48sel(source));
+ }
+
if config.low_power_run {
assert!(sys_clk <= 2_000_000);
PWR.cr1().modify(|w| w.set_lpr(true));
diff --git a/examples/stm32g4/src/bin/usb_serial.rs b/examples/stm32g4/src/bin/usb_serial.rs
index 289d0ed86..77cfa67d3 100644
--- a/examples/stm32g4/src/bin/usb_serial.rs
+++ b/examples/stm32g4/src/bin/usb_serial.rs
@@ -4,10 +4,10 @@
use defmt::{panic, *};
use embassy_executor::Spawner;
-use embassy_stm32::rcc::{ClockSrc, Pll, PllM, PllN, PllQ, PllR, PllSrc};
+use embassy_stm32::rcc::{Clock48MhzSrc, ClockSrc, CrsConfig, CrsSyncSource, Pll, PllM, PllN, PllQ, PllR, PllSrc};
use embassy_stm32::time::Hertz;
use embassy_stm32::usb::{self, Driver, Instance};
-use embassy_stm32::{bind_interrupts, pac, peripherals, Config};
+use embassy_stm32::{bind_interrupts, peripherals, Config};
use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
use embassy_usb::driver::EndpointError;
use embassy_usb::Builder;
@@ -22,25 +22,35 @@ bind_interrupts!(struct Irqs {
async fn main(_spawner: Spawner) {
let mut config = Config::default();
+ // Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE.
+ const USE_HSI48: bool = true;
+
+ let pllq_div = if USE_HSI48 { None } else { Some(PllQ::Div6) };
+
config.rcc.pll = Some(Pll {
- source: PllSrc::HSE(Hertz(8000000)),
+ source: PllSrc::HSE(Hertz(8_000_000)),
prediv_m: PllM::Div2,
mul_n: PllN::Mul72,
div_p: None,
- // USB and CAN at 48 MHz
- div_q: Some(PllQ::Div6),
+ div_q: pllq_div,
// Main system clock at 144 MHz
div_r: Some(PllR::Div2),
});
config.rcc.mux = ClockSrc::PLL;
- let p = embassy_stm32::init(config);
- info!("Hello World!");
+ if USE_HSI48 {
+ // Sets up the Clock Recovery System (CRS) to use the USB SOF to trim the HSI48 oscillator.
+ config.rcc.clock_48mhz_src = Some(Clock48MhzSrc::Hsi48(Some(CrsConfig {
+ sync_src: CrsSyncSource::Usb,
+ })));
+ } else {
+ config.rcc.clock_48mhz_src = Some(Clock48MhzSrc::PllQ);
+ }
- pac::RCC.ccipr().write(|w| {
- w.set_clk48sel(pac::rcc::vals::Clk48sel::PLLQCLK);
- });
+ let p = embassy_stm32::init(config);
+
+ info!("Hello World!");
let driver = Driver::new(p.USB, Irqs, p.PA12, p.PA11);
From e892014b6572e74b58ea653cfed06614c496e6a5 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Thu, 29 Jun 2023 01:51:19 +0200
Subject: [PATCH 38/48] Update stm32-metapac, includes chiptool changes to use
real Rust enums now.
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/src/adc/v3.rs | 8 ++--
embassy-stm32/src/can/bxcan.rs | 8 ++--
embassy-stm32/src/eth/v1/rx_desc.rs | 2 +-
embassy-stm32/src/pwm/complementary_pwm.rs | 2 +-
embassy-stm32/src/rcc/c0.rs | 10 ++--
embassy-stm32/src/rcc/f0.rs | 23 +++++----
embassy-stm32/src/rcc/f1.rs | 36 +++++++-------
embassy-stm32/src/rcc/f2.rs | 2 +-
embassy-stm32/src/rcc/f4.rs | 12 ++---
embassy-stm32/src/rcc/f7.rs | 12 ++---
embassy-stm32/src/rcc/g0.rs | 10 ++--
embassy-stm32/src/rcc/h7.rs | 17 +++----
embassy-stm32/src/rcc/l0.rs | 6 +--
embassy-stm32/src/rcc/l1.rs | 6 +--
embassy-stm32/src/rcc/l4.rs | 6 +--
embassy-stm32/src/rcc/l5.rs | 6 +--
embassy-stm32/src/rcc/u5.rs | 2 +-
embassy-stm32/src/rtc/v2.rs | 4 +-
embassy-stm32/src/rtc/v3.rs | 2 +-
embassy-stm32/src/spi/mod.rs | 4 +-
embassy-stm32/src/usart/mod.rs | 2 +-
embassy-stm32/src/usb/usb.rs | 56 +++++++++++-----------
embassy-stm32/src/usb_otg/usb.rs | 4 +-
embassy-stm32/src/wdg/mod.rs | 2 +-
25 files changed, 121 insertions(+), 125 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index f15c6d0b7..b3fe9c1f5 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -57,7 +57,7 @@ sdio-host = "0.5.0"
embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
critical-section = "1.1"
atomic-polyfill = "1.0.1"
-stm32-metapac = "11"
+stm32-metapac = "12"
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -74,7 +74,7 @@ critical-section = { version = "1.1", features = ["std"] }
[build-dependencies]
proc-macro2 = "1.0.36"
quote = "1.0.15"
-stm32-metapac = { version = "11", default-features = false, features = ["metadata"]}
+stm32-metapac = { version = "12", default-features = false, features = ["metadata"]}
[features]
default = ["rt"]
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 94cdc86cd..3a6e58cf6 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -211,10 +211,8 @@ impl<'d, T: Instance> Adc<'d, T> {
#[cfg(not(stm32g0))]
fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
let sample_time = sample_time.into();
- if ch <= 9 {
- T::regs().smpr1().modify(|reg| reg.set_smp(ch as _, sample_time));
- } else {
- T::regs().smpr2().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
- }
+ T::regs()
+ .smpr(ch as usize / 10)
+ .modify(|reg| reg.set_smp(ch as usize % 10, sample_time));
}
}
diff --git a/embassy-stm32/src/can/bxcan.rs b/embassy-stm32/src/can/bxcan.rs
index 88eef528f..73861776a 100644
--- a/embassy-stm32/src/can/bxcan.rs
+++ b/embassy-stm32/src/can/bxcan.rs
@@ -116,10 +116,10 @@ impl<'d, T: Instance> Can<'d, T> {
T::regs().ier().write(|w| {
// TODO: fix metapac
- w.set_errie(Errie(1));
- w.set_fmpie(0, Fmpie(1));
- w.set_fmpie(1, Fmpie(1));
- w.set_tmeie(Tmeie(1));
+ w.set_errie(Errie::from_bits(1));
+ w.set_fmpie(0, Fmpie::from_bits(1));
+ w.set_fmpie(1, Fmpie::from_bits(1));
+ w.set_tmeie(Tmeie::from_bits(1));
});
T::regs().mcr().write(|w| {
diff --git a/embassy-stm32/src/eth/v1/rx_desc.rs b/embassy-stm32/src/eth/v1/rx_desc.rs
index 01a073bb9..668378bea 100644
--- a/embassy-stm32/src/eth/v1/rx_desc.rs
+++ b/embassy-stm32/src/eth/v1/rx_desc.rs
@@ -174,7 +174,7 @@ impl<'a> RDesRing<'a> {
// Receive descriptor unavailable
Rps::SUSPENDED => RunningState::Stopped,
// Closing receive descriptor
- Rps(0b101) => RunningState::Running,
+ Rps::_RESERVED_5 => RunningState::Running,
// Transferring the receive packet data from receive buffer to host memory
Rps::RUNNINGWRITING => RunningState::Running,
_ => RunningState::Unknown,
diff --git a/embassy-stm32/src/pwm/complementary_pwm.rs b/embassy-stm32/src/pwm/complementary_pwm.rs
index 0e153202e..4d64d005c 100644
--- a/embassy-stm32/src/pwm/complementary_pwm.rs
+++ b/embassy-stm32/src/pwm/complementary_pwm.rs
@@ -243,7 +243,7 @@ mod tests {
for test_run in fn_results {
let (ckd, bits) = compute_dead_time_value(test_run.value);
- assert_eq!(ckd.0, test_run.ckd.0);
+ assert_eq!(ckd.to_bits(), test_run.ckd.to_bits());
assert_eq!(bits, test_run.bits);
}
}
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index 6c7b36647..df6e9047c 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -126,7 +126,7 @@ pub(crate) unsafe fn init(config: Config) {
});
while !RCC.cr().read().hsirdy() {}
- (HSI_FREQ.0 >> div.0, Sw::HSI)
+ (HSI_FREQ.0 >> div.to_bits(), Sw::HSI)
}
ClockSrc::HSE(freq) => {
// Enable HSE
@@ -157,7 +157,7 @@ pub(crate) unsafe fn init(config: Config) {
let mut set_flash_latency_after = false;
FLASH.acr().modify(|w| {
// Is the current flash latency less than what we need at the new SYSCLK?
- if w.latency().0 <= target_flash_latency.0 {
+ if w.latency().to_bits() <= target_flash_latency.to_bits() {
// We must increase the number of wait states now
w.set_latency(target_flash_latency)
} else {
@@ -171,12 +171,12 @@ pub(crate) unsafe fn init(config: Config) {
// > Flash memory.
//
// Enable flash prefetching if we have at least one wait state, and disable it otherwise.
- w.set_prften(target_flash_latency.0 > 0);
+ w.set_prften(target_flash_latency.to_bits() > 0);
});
if !set_flash_latency_after {
// Spin until the effective flash latency is compatible with the clock change
- while FLASH.acr().read().latency().0 < target_flash_latency.0 {}
+ while FLASH.acr().read().latency().to_bits() < target_flash_latency.to_bits() {}
}
// Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once
@@ -218,7 +218,7 @@ pub(crate) unsafe fn init(config: Config) {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
- let pre: u8 = 1 << (pre.0 - 3);
+ let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
diff --git a/embassy-stm32/src/rcc/f0.rs b/embassy-stm32/src/rcc/f0.rs
index eb62ab661..ca6eed284 100644
--- a/embassy-stm32/src/rcc/f0.rs
+++ b/embassy-stm32/src/rcc/f0.rs
@@ -1,3 +1,5 @@
+use stm32_metapac::flash::vals::Latency;
+
use super::{set_freqs, Clocks};
use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw};
use crate::pac::{FLASH, RCC};
@@ -85,14 +87,11 @@ pub(crate) unsafe fn init(config: Config) {
let timer_mul = if ppre == 1 { 1 } else { 2 };
FLASH.acr().write(|w| {
- let latency = if real_sysclk <= 24_000_000 {
- 0
- } else if real_sysclk <= 48_000_000 {
- 1
+ w.set_latency(if real_sysclk <= 24_000_000 {
+ Latency::WS0
} else {
- 2
- };
- w.latency().0 = latency;
+ Latency::WS1
+ });
});
match (config.hse.is_some(), use_hsi48) {
@@ -134,20 +133,20 @@ pub(crate) unsafe fn init(config: Config) {
// TODO: Option to use CRS (Clock Recovery)
if let Some(pllmul_bits) = pllmul_bits {
- RCC.cfgr().modify(|w| w.set_pllmul(Pllmul(pllmul_bits)));
+ RCC.cfgr().modify(|w| w.set_pllmul(Pllmul::from_bits(pllmul_bits)));
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
RCC.cfgr().modify(|w| {
- w.set_ppre(Ppre(ppre_bits));
- w.set_hpre(Hpre(hpre_bits));
+ w.set_ppre(Ppre::from_bits(ppre_bits));
+ w.set_hpre(Hpre::from_bits(hpre_bits));
w.set_sw(Sw::PLL)
});
} else {
RCC.cfgr().modify(|w| {
- w.set_ppre(Ppre(ppre_bits));
- w.set_hpre(Hpre(hpre_bits));
+ w.set_ppre(Ppre::from_bits(ppre_bits));
+ w.set_hpre(Hpre::from_bits(hpre_bits));
if config.hse.is_some() {
w.set_sw(Sw::HSE);
diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs
index 4769b7059..b6200231e 100644
--- a/embassy-stm32/src/rcc/f1.rs
+++ b/embassy-stm32/src/rcc/f1.rs
@@ -106,11 +106,11 @@ pub(crate) unsafe fn init(config: Config) {
// Only needed for stm32f103?
FLASH.acr().write(|w| {
w.set_latency(if real_sysclk <= 24_000_000 {
- Latency(0b000)
+ Latency::WS0
} else if real_sysclk <= 48_000_000 {
- Latency(0b001)
+ Latency::WS1
} else {
- Latency(0b010)
+ Latency::WS2
});
});
@@ -147,12 +147,13 @@ pub(crate) unsafe fn init(config: Config) {
if let Some(pllmul_bits) = pllmul_bits {
let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 };
- RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(pllctpre_flag)));
+ RCC.cfgr()
+ .modify(|w| w.set_pllxtpre(Pllxtpre::from_bits(pllctpre_flag)));
// enable PLL and wait for it to be ready
RCC.cfgr().modify(|w| {
- w.set_pllmul(Pllmul(pllmul_bits));
- w.set_pllsrc(Pllsrc(config.hse.is_some() as u8));
+ w.set_pllmul(Pllmul::from_bits(pllmul_bits));
+ w.set_pllsrc(Pllsrc::from_bits(config.hse.is_some() as u8));
});
RCC.cr().modify(|w| w.set_pllon(true));
@@ -161,22 +162,19 @@ pub(crate) unsafe fn init(config: Config) {
// Only needed for stm32f103?
RCC.cfgr().modify(|w| {
- w.set_adcpre(Adcpre(apre_bits));
- w.set_ppre2(Ppre1(ppre2_bits));
- w.set_ppre1(Ppre1(ppre1_bits));
- w.set_hpre(Hpre(hpre_bits));
+ w.set_adcpre(Adcpre::from_bits(apre_bits));
+ w.set_ppre2(Ppre1::from_bits(ppre2_bits));
+ w.set_ppre1(Ppre1::from_bits(ppre1_bits));
+ w.set_hpre(Hpre::from_bits(hpre_bits));
#[cfg(not(rcc_f100))]
- w.set_usbpre(Usbpre(usbpre as u8));
- w.set_sw(Sw(if pllmul_bits.is_some() {
- // PLL
- 0b10
+ w.set_usbpre(Usbpre::from_bits(usbpre as u8));
+ w.set_sw(if pllmul_bits.is_some() {
+ Sw::PLL
} else if config.hse.is_some() {
- // HSE
- 0b1
+ Sw::HSE
} else {
- // HSI
- 0b0
- }));
+ Sw::HSI
+ });
});
set_freqs(Clocks {
diff --git a/embassy-stm32/src/rcc/f2.rs b/embassy-stm32/src/rcc/f2.rs
index bcae64d0f..1525cc3c3 100644
--- a/embassy-stm32/src/rcc/f2.rs
+++ b/embassy-stm32/src/rcc/f2.rs
@@ -485,7 +485,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
});
- while RCC.cfgr().read().sws() != sw.0 {}
+ while RCC.cfgr().read().sws().to_bits() != sw.to_bits() {}
// Turn off HSI to save power if we don't need it
if !config.hsi {
diff --git a/embassy-stm32/src/rcc/f4.rs b/embassy-stm32/src/rcc/f4.rs
index bc430afb2..b84470440 100644
--- a/embassy-stm32/src/rcc/f4.rs
+++ b/embassy-stm32/src/rcc/f4.rs
@@ -87,7 +87,7 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option, plli2s: Opti
let sysclk = pllsysclk.unwrap_or(pllsrcclk);
if pllsysclk.is_none() && !pll48clk {
- RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
+ RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc::from_bits(use_hse as u8)));
return PllResults {
use_pll: false,
@@ -141,9 +141,9 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option, plli2s: Opti
RCC.pllcfgr().modify(|w| {
w.set_pllm(pllm as u8);
w.set_plln(plln as u16);
- w.set_pllp(Pllp(pllp as u8));
+ w.set_pllp(Pllp::from_bits(pllp as u8));
w.set_pllq(pllq as u8);
- w.set_pllsrc(Pllsrc(use_hse as u8));
+ w.set_pllsrc(Pllsrc::from_bits(use_hse as u8));
});
let real_pllsysclk = vco_in * plln / sysclk_div;
@@ -323,7 +323,7 @@ fn flash_setup(sysclk: u32) {
critical_section::with(|_| {
FLASH
.acr()
- .modify(|w| w.set_latency(Latency(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
+ .modify(|w| w.set_latency(Latency::from_bits(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
});
}
@@ -440,8 +440,8 @@ pub(crate) unsafe fn init(config: Config) {
}
RCC.cfgr().modify(|w| {
- w.set_ppre2(Ppre(ppre2_bits));
- w.set_ppre1(Ppre(ppre1_bits));
+ w.set_ppre2(Ppre::from_bits(ppre2_bits));
+ w.set_ppre1(Ppre::from_bits(ppre1_bits));
w.set_hpre(hpre_bits);
});
diff --git a/embassy-stm32/src/rcc/f7.rs b/embassy-stm32/src/rcc/f7.rs
index 71215cac5..85cb9c661 100644
--- a/embassy-stm32/src/rcc/f7.rs
+++ b/embassy-stm32/src/rcc/f7.rs
@@ -30,7 +30,7 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option, pll48clk: bo
let sysclk = pllsysclk.unwrap_or(pllsrcclk);
if pllsysclk.is_none() && !pll48clk {
- RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
+ RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc::from_bits(use_hse as u8)));
return PllResults {
use_pll: false,
@@ -83,9 +83,9 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option, pll48clk: bo
RCC.pllcfgr().modify(|w| {
w.set_pllm(pllm as u8);
w.set_plln(plln as u16);
- w.set_pllp(Pllp(pllp as u8));
+ w.set_pllp(Pllp::from_bits(pllp as u8));
w.set_pllq(pllq as u8);
- w.set_pllsrc(Pllsrc(use_hse as u8));
+ w.set_pllsrc(Pllsrc::from_bits(use_hse as u8));
});
let real_pllsysclk = vco_in * plln / sysclk_div;
@@ -106,7 +106,7 @@ fn flash_setup(sysclk: u32) {
critical_section::with(|_| {
FLASH
.acr()
- .modify(|w| w.set_latency(Latency(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
+ .modify(|w| w.set_latency(Latency::from_bits(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
});
}
@@ -246,8 +246,8 @@ pub(crate) unsafe fn init(config: Config) {
}
RCC.cfgr().modify(|w| {
- w.set_ppre2(Ppre(ppre2_bits));
- w.set_ppre1(Ppre(ppre1_bits));
+ w.set_ppre2(Ppre::from_bits(ppre2_bits));
+ w.set_ppre1(Ppre::from_bits(ppre1_bits));
w.set_hpre(hpre_bits);
});
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index 17c73c36b..5e3a7911a 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -344,7 +344,7 @@ pub(crate) unsafe fn init(config: Config) {
});
while !RCC.cr().read().hsirdy() {}
- (HSI_FREQ.0 >> div.0, Sw::HSI)
+ (HSI_FREQ.0 >> div.to_bits(), Sw::HSI)
}
ClockSrc::HSE(freq) => {
// Enable HSE
@@ -381,7 +381,7 @@ pub(crate) unsafe fn init(config: Config) {
let mut set_flash_latency_after = false;
FLASH.acr().modify(|w| {
// Is the current flash latency less than what we need at the new SYSCLK?
- if w.latency().0 <= target_flash_latency.0 {
+ if w.latency().to_bits() <= target_flash_latency.to_bits() {
// We must increase the number of wait states now
w.set_latency(target_flash_latency)
} else {
@@ -395,12 +395,12 @@ pub(crate) unsafe fn init(config: Config) {
// > Flash memory.
//
// Enable flash prefetching if we have at least one wait state, and disable it otherwise.
- w.set_prften(target_flash_latency.0 > 0);
+ w.set_prften(target_flash_latency.to_bits() > 0);
});
if !set_flash_latency_after {
// Spin until the effective flash latency is compatible with the clock change
- while FLASH.acr().read().latency().0 < target_flash_latency.0 {}
+ while FLASH.acr().read().latency().to_bits() < target_flash_latency.to_bits() {}
}
// Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once
@@ -442,7 +442,7 @@ pub(crate) unsafe fn init(config: Config) {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
- let pre: u8 = 1 << (pre.0 - 3);
+ let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
diff --git a/embassy-stm32/src/rcc/h7.rs b/embassy-stm32/src/rcc/h7.rs
index daa1cd61f..f3a98c794 100644
--- a/embassy-stm32/src/rcc/h7.rs
+++ b/embassy-stm32/src/rcc/h7.rs
@@ -601,22 +601,22 @@ pub(crate) unsafe fn init(mut config: Config) {
// Core Prescaler / AHB Prescaler / APB3 Prescaler
RCC.d1cfgr().modify(|w| {
- w.set_d1cpre(Hpre(d1cpre_bits));
- w.set_d1ppre(Dppre(ppre3_bits));
+ w.set_d1cpre(Hpre::from_bits(d1cpre_bits));
+ w.set_d1ppre(Dppre::from_bits(ppre3_bits));
w.set_hpre(hpre_bits)
});
// Ensure core prescaler value is valid before future lower
// core voltage
- while RCC.d1cfgr().read().d1cpre().0 != d1cpre_bits {}
+ while RCC.d1cfgr().read().d1cpre().to_bits() != d1cpre_bits {}
// APB1 / APB2 Prescaler
RCC.d2cfgr().modify(|w| {
- w.set_d2ppre1(Dppre(ppre1_bits));
- w.set_d2ppre2(Dppre(ppre2_bits));
+ w.set_d2ppre1(Dppre::from_bits(ppre1_bits));
+ w.set_d2ppre2(Dppre::from_bits(ppre2_bits));
});
// APB4 Prescaler
- RCC.d3cfgr().modify(|w| w.set_d3ppre(Dppre(ppre4_bits)));
+ RCC.d3cfgr().modify(|w| w.set_d3ppre(Dppre::from_bits(ppre4_bits)));
// Peripheral Clock (per_ck)
RCC.d1ccipr().modify(|w| w.set_ckpersel(ckpersel));
@@ -640,7 +640,7 @@ pub(crate) unsafe fn init(mut config: Config) {
_ => Sw::HSI,
};
RCC.cfgr().modify(|w| w.set_sw(sw));
- while RCC.cfgr().read().sws() != sw.0 {}
+ while RCC.cfgr().read().sws().to_bits() != sw.to_bits() {}
// IO compensation cell - Requires CSI clock and SYSCFG
assert!(RCC.cr().read().csirdy());
@@ -806,7 +806,8 @@ mod pll {
RCC.pllcfgr().modify(|w| w.set_pllfracen(plln, false));
let vco_ck = ref_x_ck * pll_x_n;
- RCC.plldivr(plln).modify(|w| w.set_divp1(Divp((pll_x_p - 1) as u8)));
+ RCC.plldivr(plln)
+ .modify(|w| w.set_divp1(Divp::from_bits((pll_x_p - 1) as u8)));
RCC.pllcfgr().modify(|w| w.set_divpen(plln, true));
// Calulate additional output dividers
diff --git a/embassy-stm32/src/rcc/l0.rs b/embassy-stm32/src/rcc/l0.rs
index d53b61069..46a528e31 100644
--- a/embassy-stm32/src/rcc/l0.rs
+++ b/embassy-stm32/src/rcc/l0.rs
@@ -293,7 +293,7 @@ pub(crate) unsafe fn init(config: Config) {
AHBPrescaler::NotDivided => sys_clk,
pre => {
let pre: Hpre = pre.into();
- let pre = 1 << (pre.0 as u32 - 7);
+ let pre = 1 << (pre.to_bits() as u32 - 7);
sys_clk / pre
}
};
@@ -302,7 +302,7 @@ pub(crate) unsafe fn init(config: Config) {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
- let pre: u8 = 1 << (pre.0 - 3);
+ let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
@@ -312,7 +312,7 @@ pub(crate) unsafe fn init(config: Config) {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
- let pre: u8 = 1 << (pre.0 - 3);
+ let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
diff --git a/embassy-stm32/src/rcc/l1.rs b/embassy-stm32/src/rcc/l1.rs
index c907fa88a..59a6eac8f 100644
--- a/embassy-stm32/src/rcc/l1.rs
+++ b/embassy-stm32/src/rcc/l1.rs
@@ -294,7 +294,7 @@ pub(crate) unsafe fn init(config: Config) {
AHBPrescaler::NotDivided => sys_clk,
pre => {
let pre: Hpre = pre.into();
- let pre = 1 << (pre.0 as u32 - 7);
+ let pre = 1 << (pre.to_bits() as u32 - 7);
sys_clk / pre
}
};
@@ -303,7 +303,7 @@ pub(crate) unsafe fn init(config: Config) {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
- let pre: u8 = 1 << (pre.0 - 3);
+ let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
@@ -313,7 +313,7 @@ pub(crate) unsafe fn init(config: Config) {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
- let pre: u8 = 1 << (pre.0 - 3);
+ let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
diff --git a/embassy-stm32/src/rcc/l4.rs b/embassy-stm32/src/rcc/l4.rs
index f8c1a6e06..20cb8c91c 100644
--- a/embassy-stm32/src/rcc/l4.rs
+++ b/embassy-stm32/src/rcc/l4.rs
@@ -635,7 +635,7 @@ pub(crate) unsafe fn init(config: Config) {
AHBPrescaler::NotDivided => sys_clk,
pre => {
let pre: Hpre = pre.into();
- let pre = 1 << (pre.0 as u32 - 7);
+ let pre = 1 << (pre.to_bits() as u32 - 7);
sys_clk / pre
}
};
@@ -644,7 +644,7 @@ pub(crate) unsafe fn init(config: Config) {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
- let pre: u8 = 1 << (pre.0 - 3);
+ let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
@@ -654,7 +654,7 @@ pub(crate) unsafe fn init(config: Config) {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
- let pre: u8 = 1 << (pre.0 - 3);
+ let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
diff --git a/embassy-stm32/src/rcc/l5.rs b/embassy-stm32/src/rcc/l5.rs
index f56fce365..16da65d5e 100644
--- a/embassy-stm32/src/rcc/l5.rs
+++ b/embassy-stm32/src/rcc/l5.rs
@@ -461,7 +461,7 @@ pub(crate) unsafe fn init(config: Config) {
AHBPrescaler::NotDivided => sys_clk,
pre => {
let pre: Hpre = pre.into();
- let pre = 1 << (pre.0 as u32 - 7);
+ let pre = 1 << (pre.to_bits() as u32 - 7);
sys_clk / pre
}
};
@@ -470,7 +470,7 @@ pub(crate) unsafe fn init(config: Config) {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
- let pre: u8 = 1 << (pre.0 - 3);
+ let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
@@ -480,7 +480,7 @@ pub(crate) unsafe fn init(config: Config) {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
- let pre: u8 = 1 << (pre.0 - 3);
+ let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 81507a4d6..cfc07f069 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -126,7 +126,7 @@ pub enum PllM {
impl Into for PllM {
fn into(self) -> Pllm {
- Pllm(self as u8)
+ Pllm::from_bits(self as u8)
}
}
diff --git a/embassy-stm32/src/rtc/v2.rs b/embassy-stm32/src/rtc/v2.rs
index e1615b34c..a2eace6d3 100644
--- a/embassy-stm32/src/rtc/v2.rs
+++ b/embassy-stm32/src/rtc/v2.rs
@@ -36,7 +36,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
#[cfg(rtc_v2wb)]
let rtcsel = reg.rtcsel();
#[cfg(not(rtc_v2wb))]
- let rtcsel = reg.rtcsel().0;
+ let rtcsel = reg.rtcsel().to_bits();
if !reg.rtcen() || rtcsel != clock_config {
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
@@ -54,7 +54,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
// Select RTC source
#[cfg(not(rtc_v2wb))]
- w.set_rtcsel(Rtcsel(clock_config));
+ w.set_rtcsel(Rtcsel::from_bits(clock_config));
#[cfg(rtc_v2wb)]
w.set_rtcsel(clock_config);
w.set_rtcen(true);
diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs
index 7c91046a2..7e5c64d90 100644
--- a/embassy-stm32/src/rtc/v3.rs
+++ b/embassy-stm32/src/rtc/v3.rs
@@ -26,7 +26,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
let config_rtcsel = rtc_config.clock_config as u8;
#[cfg(not(any(rcc_wl5, rcc_wle)))]
- let config_rtcsel = crate::pac::rcc::vals::Rtcsel(config_rtcsel);
+ let config_rtcsel = crate::pac::rcc::vals::Rtcsel::from_bits(config_rtcsel);
if !reg.rtcen() || reg.rtcsel() != config_rtcsel {
crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 1cddac992..c3224073d 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -650,7 +650,7 @@ fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> Br {
_ => 0b111,
};
- Br(val)
+ Br::from_bits(val)
}
trait RegsExt {
@@ -772,7 +772,7 @@ fn set_rxdmaen(regs: Regs, val: bool) {
fn finish_dma(regs: Regs) {
#[cfg(spi_v2)]
- while regs.sr().read().ftlvl() > 0 {}
+ while regs.sr().read().ftlvl().to_bits() > 0 {}
#[cfg(any(spi_v3, spi_v4, spi_v5))]
while !regs.sr().read().txc() {}
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 47a79c187..c97efbf0a 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -869,7 +869,7 @@ fn configure(r: Regs, config: &Config, pclk_freq: Hertz, kind: Kind, enable_rx:
_ => vals::Ps::EVEN,
});
#[cfg(not(usart_v1))]
- w.set_over8(vals::Over8(over8 as _));
+ w.set_over8(vals::Over8::from_bits(over8 as _));
});
#[cfg(not(usart_v1))]
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 01b158b17..ecdd1d0b8 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -97,8 +97,8 @@ impl interrupt::typelevel::Handler for InterruptHandl
}
epr.set_dtog_rx(false);
epr.set_dtog_tx(false);
- epr.set_stat_rx(Stat(0));
- epr.set_stat_tx(Stat(0));
+ epr.set_stat_rx(Stat::from_bits(0));
+ epr.set_stat_tx(Stat::from_bits(0));
epr.set_ctr_rx(!epr.ctr_rx());
epr.set_ctr_tx(!epr.ctr_tx());
regs.epr(index).write_value(epr);
@@ -143,8 +143,8 @@ fn invariant(mut r: regs::Epr) -> regs::Epr {
r.set_ctr_tx(true); // don't clear
r.set_dtog_rx(false); // don't toggle
r.set_dtog_tx(false); // don't toggle
- r.set_stat_rx(Stat(0));
- r.set_stat_tx(Stat(0));
+ r.set_stat_rx(Stat::from_bits(0));
+ r.set_stat_tx(Stat::from_bits(0));
r
}
@@ -551,7 +551,7 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
true => Stat::STALL,
};
let mut w = invariant(r);
- w.set_stat_tx(Stat(r.stat_tx().0 ^ want_stat.0));
+ w.set_stat_tx(Stat::from_bits(r.stat_tx().to_bits() ^ want_stat.to_bits()));
reg.write_value(w);
}
}
@@ -570,7 +570,7 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
true => Stat::STALL,
};
let mut w = invariant(r);
- w.set_stat_rx(Stat(r.stat_rx().0 ^ want_stat.0));
+ w.set_stat_rx(Stat::from_bits(r.stat_rx().to_bits() ^ want_stat.to_bits()));
reg.write_value(w);
}
}
@@ -606,7 +606,7 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
break;
}
let mut w = invariant(r);
- w.set_stat_tx(Stat(r.stat_tx().0 ^ want_stat.0));
+ w.set_stat_tx(Stat::from_bits(r.stat_tx().to_bits() ^ want_stat.to_bits()));
reg.write_value(w);
}
EP_IN_WAKERS[ep_addr.index()].wake();
@@ -622,7 +622,7 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
break;
}
let mut w = invariant(r);
- w.set_stat_rx(Stat(r.stat_rx().0 ^ want_stat.0));
+ w.set_stat_rx(Stat::from_bits(r.stat_rx().to_bits() ^ want_stat.to_bits()));
reg.write_value(w);
}
EP_OUT_WAKERS[ep_addr.index()].wake();
@@ -763,8 +763,8 @@ impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
regs.epr(index).write(|w| {
w.set_ep_type(convert_type(self.info.ep_type));
w.set_ea(self.info.addr.index() as _);
- w.set_stat_rx(Stat(Stat::NAK.0 ^ Stat::VALID.0));
- w.set_stat_tx(Stat(0));
+ w.set_stat_rx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits()));
+ w.set_stat_tx(Stat::from_bits(0));
w.set_ctr_rx(true); // don't clear
w.set_ctr_tx(true); // don't clear
});
@@ -805,8 +805,8 @@ impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> {
regs.epr(index).write(|w| {
w.set_ep_type(convert_type(self.info.ep_type));
w.set_ea(self.info.addr.index() as _);
- w.set_stat_tx(Stat(Stat::NAK.0 ^ Stat::VALID.0));
- w.set_stat_rx(Stat(0));
+ w.set_stat_tx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits()));
+ w.set_stat_rx(Stat::from_bits(0));
w.set_ctr_rx(true); // don't clear
w.set_ctr_tx(true); // don't clear
});
@@ -869,19 +869,19 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
let mut stat_tx = 0;
if first {
// change NAK -> VALID
- stat_rx ^= Stat::NAK.0 ^ Stat::VALID.0;
- stat_tx ^= Stat::NAK.0 ^ Stat::STALL.0;
+ stat_rx ^= Stat::NAK.to_bits() ^ Stat::VALID.to_bits();
+ stat_tx ^= Stat::NAK.to_bits() ^ Stat::STALL.to_bits();
}
if last {
// change STALL -> VALID
- stat_tx ^= Stat::STALL.0 ^ Stat::NAK.0;
+ stat_tx ^= Stat::STALL.to_bits() ^ Stat::NAK.to_bits();
}
// Note: if this is the first AND last transfer, the above effectively
// changes stat_tx like NAK -> NAK, so noop.
regs.epr(0).write(|w| {
w.set_ep_type(EpType::CONTROL);
- w.set_stat_rx(Stat(stat_rx));
- w.set_stat_tx(Stat(stat_tx));
+ w.set_stat_rx(Stat::from_bits(stat_rx));
+ w.set_stat_tx(Stat::from_bits(stat_tx));
w.set_ctr_rx(true); // don't clear
w.set_ctr_tx(true); // don't clear
});
@@ -908,11 +908,11 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
regs.epr(0).write(|w| {
w.set_ep_type(EpType::CONTROL);
- w.set_stat_rx(Stat(match last {
+ w.set_stat_rx(Stat::from_bits(match last {
// If last, set STAT_RX=STALL.
- true => Stat::NAK.0 ^ Stat::STALL.0,
+ true => Stat::NAK.to_bits() ^ Stat::STALL.to_bits(),
// Otherwise, set STAT_RX=VALID, to allow the host to send the next packet.
- false => Stat::NAK.0 ^ Stat::VALID.0,
+ false => Stat::NAK.to_bits() ^ Stat::VALID.to_bits(),
}));
w.set_ctr_rx(true); // don't clear
w.set_ctr_tx(true); // don't clear
@@ -937,17 +937,17 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
let mut stat_rx = 0;
if first {
// change NAK -> STALL
- stat_rx ^= Stat::NAK.0 ^ Stat::STALL.0;
+ stat_rx ^= Stat::NAK.to_bits() ^ Stat::STALL.to_bits();
}
if last {
// change STALL -> VALID
- stat_rx ^= Stat::STALL.0 ^ Stat::VALID.0;
+ stat_rx ^= Stat::STALL.to_bits() ^ Stat::VALID.to_bits();
}
// Note: if this is the first AND last transfer, the above effectively
// does a change of NAK -> VALID.
regs.epr(0).write(|w| {
w.set_ep_type(EpType::CONTROL);
- w.set_stat_rx(Stat(stat_rx));
+ w.set_stat_rx(Stat::from_bits(stat_rx));
w.set_ep_kind(last); // set OUT_STATUS if last.
w.set_ctr_rx(true); // don't clear
w.set_ctr_tx(true); // don't clear
@@ -977,7 +977,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
let regs = T::regs();
regs.epr(0).write(|w| {
w.set_ep_type(EpType::CONTROL);
- w.set_stat_tx(Stat(Stat::NAK.0 ^ Stat::VALID.0));
+ w.set_stat_tx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits()));
w.set_ep_kind(last); // set OUT_STATUS if last.
w.set_ctr_rx(true); // don't clear
w.set_ctr_tx(true); // don't clear
@@ -998,8 +998,8 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
let epr = regs.epr(0).read();
regs.epr(0).write(|w| {
w.set_ep_type(EpType::CONTROL);
- w.set_stat_rx(Stat(epr.stat_rx().0 ^ Stat::STALL.0));
- w.set_stat_tx(Stat(epr.stat_tx().0 ^ Stat::VALID.0));
+ w.set_stat_rx(Stat::from_bits(epr.stat_rx().to_bits() ^ Stat::STALL.to_bits()));
+ w.set_stat_tx(Stat::from_bits(epr.stat_tx().to_bits() ^ Stat::VALID.to_bits()));
w.set_ctr_rx(true); // don't clear
w.set_ctr_tx(true); // don't clear
});
@@ -1029,8 +1029,8 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
let epr = regs.epr(0).read();
regs.epr(0).write(|w| {
w.set_ep_type(EpType::CONTROL);
- w.set_stat_rx(Stat(epr.stat_rx().0 ^ Stat::STALL.0));
- w.set_stat_tx(Stat(epr.stat_tx().0 ^ Stat::STALL.0));
+ w.set_stat_rx(Stat::from_bits(epr.stat_rx().to_bits() ^ Stat::STALL.to_bits()));
+ w.set_stat_tx(Stat::from_bits(epr.stat_tx().to_bits() ^ Stat::STALL.to_bits()));
w.set_ctr_rx(true); // don't clear
w.set_ctr_tx(true); // don't clear
});
diff --git a/embassy-stm32/src/usb_otg/usb.rs b/embassy-stm32/src/usb_otg/usb.rs
index 6c00c93d6..6783db28d 100644
--- a/embassy-stm32/src/usb_otg/usb.rs
+++ b/embassy-stm32/src/usb_otg/usb.rs
@@ -97,7 +97,7 @@ impl interrupt::typelevel::Handler for InterruptHandl
vals::Pktstsd::SETUP_DATA_DONE => {
trace!("SETUP_DATA_DONE ep={}", ep_num);
}
- x => trace!("unknown PKTSTS: {}", x.0),
+ x => trace!("unknown PKTSTS: {}", x.to_bits()),
}
}
@@ -920,7 +920,7 @@ impl<'d, T: Instance> embassy_usb_driver::Bus for Bus<'d, T> {
trace!("enumdne");
let speed = r.dsts().read().enumspd();
- trace!(" speed={}", speed.0);
+ trace!(" speed={}", speed.to_bits());
r.gusbcfg().modify(|w| {
w.set_trdt(calculate_trdt(speed, T::frequency()));
diff --git a/embassy-stm32/src/wdg/mod.rs b/embassy-stm32/src/wdg/mod.rs
index 5907a4e54..b03e81d6e 100644
--- a/embassy-stm32/src/wdg/mod.rs
+++ b/embassy-stm32/src/wdg/mod.rs
@@ -49,7 +49,7 @@ impl<'d, T: Instance> IndependentWatchdog<'d, T> {
let wdg = T::regs();
wdg.kr().write(|w| w.set_key(Key::ENABLE));
- wdg.pr().write(|w| w.set_pr(Pr(pr)));
+ wdg.pr().write(|w| w.set_pr(Pr::from_bits(pr)));
wdg.rlr().write(|w| w.set_rl(rl));
trace!(
From ce889900d63f9f32f1a6b7540834d6f9558239e4 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Thu, 29 Jun 2023 02:08:55 +0200
Subject: [PATCH 39/48] Update rp-pac.
---
embassy-rp/Cargo.toml | 2 +-
embassy-rp/src/clocks.rs | 92 ++++++++++++++++++++--------------------
embassy-rp/src/gpio.rs | 4 +-
embassy-rp/src/pio.rs | 4 +-
4 files changed, 51 insertions(+), 51 deletions(-)
diff --git a/embassy-rp/Cargo.toml b/embassy-rp/Cargo.toml
index 49aa6a4d5..66823771a 100644
--- a/embassy-rp/Cargo.toml
+++ b/embassy-rp/Cargo.toml
@@ -76,7 +76,7 @@ embedded-storage = { version = "0.3" }
rand_core = "0.6.4"
fixed = "1.23.1"
-rp-pac = { version = "5" }
+rp-pac = { version = "6" }
embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10", optional = true}
diff --git a/embassy-rp/src/clocks.rs b/embassy-rp/src/clocks.rs
index 4c6223107..ddd61d224 100644
--- a/embassy-rp/src/clocks.rs
+++ b/embassy-rp/src/clocks.rs
@@ -46,13 +46,13 @@ static CLOCKS: Clocks = Clocks {
#[non_exhaustive]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PeriClkSrc {
- Sys = ClkPeriCtrlAuxsrc::CLK_SYS.0,
- PllSys = ClkPeriCtrlAuxsrc::CLKSRC_PLL_SYS.0,
- PllUsb = ClkPeriCtrlAuxsrc::CLKSRC_PLL_USB.0,
- Rosc = ClkPeriCtrlAuxsrc::ROSC_CLKSRC_PH.0,
- Xosc = ClkPeriCtrlAuxsrc::XOSC_CLKSRC.0,
- // Gpin0 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN0.0,
- // Gpin1 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN1.0,
+ Sys = ClkPeriCtrlAuxsrc::CLK_SYS as _,
+ PllSys = ClkPeriCtrlAuxsrc::CLKSRC_PLL_SYS as _,
+ PllUsb = ClkPeriCtrlAuxsrc::CLKSRC_PLL_USB as _,
+ Rosc = ClkPeriCtrlAuxsrc::ROSC_CLKSRC_PH as _,
+ Xosc = ClkPeriCtrlAuxsrc::XOSC_CLKSRC as _,
+ // Gpin0 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN0 as _ ,
+ // Gpin1 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN1 as _ ,
}
#[non_exhaustive]
@@ -251,12 +251,12 @@ pub struct SysClkConfig {
#[non_exhaustive]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum UsbClkSrc {
- PllUsb = ClkUsbCtrlAuxsrc::CLKSRC_PLL_USB.0,
- PllSys = ClkUsbCtrlAuxsrc::CLKSRC_PLL_SYS.0,
- Rosc = ClkUsbCtrlAuxsrc::ROSC_CLKSRC_PH.0,
- Xosc = ClkUsbCtrlAuxsrc::XOSC_CLKSRC.0,
- // Gpin0 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN0.0,
- // Gpin1 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN1.0,
+ PllUsb = ClkUsbCtrlAuxsrc::CLKSRC_PLL_USB as _,
+ PllSys = ClkUsbCtrlAuxsrc::CLKSRC_PLL_SYS as _,
+ Rosc = ClkUsbCtrlAuxsrc::ROSC_CLKSRC_PH as _,
+ Xosc = ClkUsbCtrlAuxsrc::XOSC_CLKSRC as _,
+ // Gpin0 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN0 as _ ,
+ // Gpin1 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN1 as _ ,
}
pub struct UsbClkConfig {
@@ -269,12 +269,12 @@ pub struct UsbClkConfig {
#[non_exhaustive]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum AdcClkSrc {
- PllUsb = ClkAdcCtrlAuxsrc::CLKSRC_PLL_USB.0,
- PllSys = ClkAdcCtrlAuxsrc::CLKSRC_PLL_SYS.0,
- Rosc = ClkAdcCtrlAuxsrc::ROSC_CLKSRC_PH.0,
- Xosc = ClkAdcCtrlAuxsrc::XOSC_CLKSRC.0,
- // Gpin0 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN0.0,
- // Gpin1 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN1.0,
+ PllUsb = ClkAdcCtrlAuxsrc::CLKSRC_PLL_USB as _,
+ PllSys = ClkAdcCtrlAuxsrc::CLKSRC_PLL_SYS as _,
+ Rosc = ClkAdcCtrlAuxsrc::ROSC_CLKSRC_PH as _,
+ Xosc = ClkAdcCtrlAuxsrc::XOSC_CLKSRC as _,
+ // Gpin0 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN0 as _ ,
+ // Gpin1 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN1 as _ ,
}
pub struct AdcClkConfig {
@@ -287,12 +287,12 @@ pub struct AdcClkConfig {
#[non_exhaustive]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RtcClkSrc {
- PllUsb = ClkRtcCtrlAuxsrc::CLKSRC_PLL_USB.0,
- PllSys = ClkRtcCtrlAuxsrc::CLKSRC_PLL_SYS.0,
- Rosc = ClkRtcCtrlAuxsrc::ROSC_CLKSRC_PH.0,
- Xosc = ClkRtcCtrlAuxsrc::XOSC_CLKSRC.0,
- // Gpin0 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN0.0,
- // Gpin1 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN1.0,
+ PllUsb = ClkRtcCtrlAuxsrc::CLKSRC_PLL_USB as _,
+ PllSys = ClkRtcCtrlAuxsrc::CLKSRC_PLL_SYS as _,
+ Rosc = ClkRtcCtrlAuxsrc::ROSC_CLKSRC_PH as _,
+ Xosc = ClkRtcCtrlAuxsrc::XOSC_CLKSRC as _,
+ // Gpin0 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN0 as _ ,
+ // Gpin1 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN1 as _ ,
}
pub struct RtcClkConfig {
@@ -396,7 +396,7 @@ pub(crate) unsafe fn init(config: ClockConfig) {
w.set_src(ref_src);
w.set_auxsrc(ref_aux);
});
- while c.clk_ref_selected().read() != 1 << ref_src.0 {}
+ while c.clk_ref_selected().read() != 1 << ref_src as u32 {}
c.clk_ref_div().write(|w| {
w.set_int(config.ref_clk.div);
});
@@ -425,13 +425,13 @@ pub(crate) unsafe fn init(config: ClockConfig) {
CLOCKS.sys.store(clk_sys_freq, Ordering::Relaxed);
if sys_src != ClkSysCtrlSrc::CLK_REF {
c.clk_sys_ctrl().write(|w| w.set_src(ClkSysCtrlSrc::CLK_REF));
- while c.clk_sys_selected().read() != 1 << ClkSysCtrlSrc::CLK_REF.0 {}
+ while c.clk_sys_selected().read() != 1 << ClkSysCtrlSrc::CLK_REF as u32 {}
}
c.clk_sys_ctrl().write(|w| {
w.set_auxsrc(sys_aux);
w.set_src(sys_src);
});
- while c.clk_sys_selected().read() != 1 << sys_src.0 {}
+ while c.clk_sys_selected().read() != 1 << sys_src as u32 {}
c.clk_sys_div().write(|w| {
w.set_int(config.sys_clk.div_int);
w.set_frac(config.sys_clk.div_frac);
@@ -442,7 +442,7 @@ pub(crate) unsafe fn init(config: ClockConfig) {
if let Some(src) = config.peri_clk_src {
c.clk_peri_ctrl().write(|w| {
w.set_enable(true);
- w.set_auxsrc(ClkPeriCtrlAuxsrc(src as _));
+ w.set_auxsrc(ClkPeriCtrlAuxsrc::from_bits(src as _));
});
let peri_freq = match src {
PeriClkSrc::Sys => clk_sys_freq,
@@ -468,7 +468,7 @@ pub(crate) unsafe fn init(config: ClockConfig) {
c.clk_usb_ctrl().write(|w| {
w.set_phase(conf.phase);
w.set_enable(true);
- w.set_auxsrc(ClkUsbCtrlAuxsrc(conf.src as _));
+ w.set_auxsrc(ClkUsbCtrlAuxsrc::from_bits(conf.src as _));
});
let usb_freq = match conf.src {
UsbClkSrc::PllUsb => pll_usb_freq,
@@ -491,7 +491,7 @@ pub(crate) unsafe fn init(config: ClockConfig) {
c.clk_adc_ctrl().write(|w| {
w.set_phase(conf.phase);
w.set_enable(true);
- w.set_auxsrc(ClkAdcCtrlAuxsrc(conf.src as _));
+ w.set_auxsrc(ClkAdcCtrlAuxsrc::from_bits(conf.src as _));
});
let adc_in_freq = match conf.src {
AdcClkSrc::PllUsb => pll_usb_freq,
@@ -517,7 +517,7 @@ pub(crate) unsafe fn init(config: ClockConfig) {
c.clk_rtc_ctrl().write(|w| {
w.set_phase(conf.phase);
w.set_enable(true);
- w.set_auxsrc(ClkRtcCtrlAuxsrc(conf.src as _));
+ w.set_auxsrc(ClkRtcCtrlAuxsrc::from_bits(conf.src as _));
});
let rtc_in_freq = match conf.src {
RtcClkSrc::PllUsb => pll_usb_freq,
@@ -718,7 +718,7 @@ impl<'d, T: Pin> Drop for Gpin<'d, T> {
self.gpin
.io()
.ctrl()
- .write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL.0));
+ .write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _));
}
}
@@ -743,17 +743,17 @@ impl_gpoutpin!(PIN_25, 3);
#[repr(u8)]
pub enum GpoutSrc {
- PllSys = ClkGpoutCtrlAuxsrc::CLKSRC_PLL_SYS.0,
- // Gpin0 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN0.0,
- // Gpin1 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN1.0,
- PllUsb = ClkGpoutCtrlAuxsrc::CLKSRC_PLL_USB.0,
- Rosc = ClkGpoutCtrlAuxsrc::ROSC_CLKSRC.0,
- Xosc = ClkGpoutCtrlAuxsrc::XOSC_CLKSRC.0,
- Sys = ClkGpoutCtrlAuxsrc::CLK_SYS.0,
- Usb = ClkGpoutCtrlAuxsrc::CLK_USB.0,
- Adc = ClkGpoutCtrlAuxsrc::CLK_ADC.0,
- Rtc = ClkGpoutCtrlAuxsrc::CLK_RTC.0,
- Ref = ClkGpoutCtrlAuxsrc::CLK_REF.0,
+ PllSys = ClkGpoutCtrlAuxsrc::CLKSRC_PLL_SYS as _,
+ // Gpin0 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN0 as _ ,
+ // Gpin1 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN1 as _ ,
+ PllUsb = ClkGpoutCtrlAuxsrc::CLKSRC_PLL_USB as _,
+ Rosc = ClkGpoutCtrlAuxsrc::ROSC_CLKSRC as _,
+ Xosc = ClkGpoutCtrlAuxsrc::XOSC_CLKSRC as _,
+ Sys = ClkGpoutCtrlAuxsrc::CLK_SYS as _,
+ Usb = ClkGpoutCtrlAuxsrc::CLK_USB as _,
+ Adc = ClkGpoutCtrlAuxsrc::CLK_ADC as _,
+ Rtc = ClkGpoutCtrlAuxsrc::CLK_RTC as _,
+ Ref = ClkGpoutCtrlAuxsrc::CLK_REF as _,
}
pub struct Gpout<'d, T: GpoutPin> {
@@ -780,7 +780,7 @@ impl<'d, T: GpoutPin> Gpout<'d, T> {
pub fn set_src(&self, src: GpoutSrc) {
let c = pac::CLOCKS;
c.clk_gpout_ctrl(self.gpout.number()).modify(|w| {
- w.set_auxsrc(ClkGpoutCtrlAuxsrc(src as _));
+ w.set_auxsrc(ClkGpoutCtrlAuxsrc::from_bits(src as _));
});
}
@@ -831,7 +831,7 @@ impl<'d, T: GpoutPin> Drop for Gpout<'d, T> {
self.gpout
.io()
.ctrl()
- .write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL.0));
+ .write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _));
}
}
diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs
index ce0d02557..f8048a4dd 100644
--- a/embassy-rp/src/gpio.rs
+++ b/embassy-rp/src/gpio.rs
@@ -452,7 +452,7 @@ impl<'d, T: Pin> Flex<'d, T> {
});
pin.io().ctrl().write(|w| {
- w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::SIO_0.0);
+ w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::SIO_0 as _);
});
Self { pin }
@@ -618,7 +618,7 @@ impl<'d, T: Pin> Drop for Flex<'d, T> {
fn drop(&mut self) {
self.pin.pad_ctrl().write(|_| {});
self.pin.io().ctrl().write(|w| {
- w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL.0);
+ w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _);
});
}
}
diff --git a/embassy-rp/src/pio.rs b/embassy-rp/src/pio.rs
index 1b36e0a54..30648e8ea 100644
--- a/embassy-rp/src/pio.rs
+++ b/embassy-rp/src/pio.rs
@@ -834,7 +834,7 @@ impl<'d, PIO: Instance> Common<'d, PIO> {
/// of [`Pio`] do not keep pin registrations alive.**
pub fn make_pio_pin(&mut self, pin: impl Peripheral + 'd) -> Pin<'d, PIO> {
into_ref!(pin);
- pin.io().ctrl().write(|w| w.set_funcsel(PIO::FUNCSEL.0));
+ pin.io().ctrl().write(|w| w.set_funcsel(PIO::FUNCSEL as _));
// we can be relaxed about this because we're &mut here and nothing is cached
PIO::state().used_pins.fetch_or(1 << pin.pin_bank(), Ordering::Relaxed);
Pin {
@@ -998,7 +998,7 @@ fn on_pio_drop() {
let state = PIO::state();
if state.users.fetch_sub(1, Ordering::AcqRel) == 1 {
let used_pins = state.used_pins.load(Ordering::Relaxed);
- let null = Gpio0ctrlFuncsel::NULL.0;
+ let null = Gpio0ctrlFuncsel::NULL as _;
// we only have 30 pins. don't test the other two since gpio() asserts.
for i in 0..30 {
if used_pins & (1 << i) != 0 {
From f7ec579c18b2ec925afcd4ab9a840719f4ce08cc Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Thu, 29 Jun 2023 02:39:28 +0200
Subject: [PATCH 40/48] Update probe-rs-cli -> probe-rs
---
.vscode/settings.json | 6 +++---
cyw43/README.md | 12 ++++++------
embassy-nrf/src/lib.rs | 6 +++---
examples/boot/application/nrf/.cargo/config.toml | 4 ++--
examples/boot/application/rp/.cargo/config.toml | 2 +-
examples/boot/application/stm32f3/.cargo/config.toml | 4 ++--
examples/boot/application/stm32f7/.cargo/config.toml | 4 ++--
examples/boot/application/stm32h7/.cargo/config.toml | 4 ++--
examples/boot/application/stm32h7/flash-boot.sh | 2 +-
examples/boot/application/stm32l0/.cargo/config.toml | 4 ++--
examples/boot/application/stm32l1/.cargo/config.toml | 4 ++--
examples/boot/application/stm32l4/.cargo/config.toml | 4 ++--
examples/boot/application/stm32wl/.cargo/config.toml | 4 ++--
examples/boot/bootloader/nrf/.cargo/config.toml | 2 +-
examples/boot/bootloader/rp/.cargo/config.toml | 2 +-
examples/nrf-rtos-trace/.cargo/config.toml | 4 ++--
examples/nrf52840-rtic/.cargo/config.toml | 4 ++--
examples/nrf52840/.cargo/config.toml | 4 ++--
examples/nrf52840/src/bin/nvmc.rs | 2 +-
examples/nrf52840/src/bin/wdt.rs | 2 +-
examples/nrf5340/.cargo/config.toml | 4 ++--
examples/rp/.cargo/config.toml | 2 +-
examples/rp/src/bin/wifi_ap_tcp_server.rs | 4 ++--
examples/rp/src/bin/wifi_blinky.rs | 4 ++--
examples/rp/src/bin/wifi_scan.rs | 4 ++--
examples/rp/src/bin/wifi_tcp_server.rs | 4 ++--
examples/stm32c0/.cargo/config.toml | 4 ++--
examples/stm32f0/.cargo/config.toml | 2 +-
examples/stm32f1/.cargo/config.toml | 4 ++--
examples/stm32f2/.cargo/config.toml | 4 ++--
examples/stm32f3/.cargo/config.toml | 4 ++--
examples/stm32f4/.cargo/config.toml | 4 ++--
examples/stm32f7/.cargo/config.toml | 4 ++--
examples/stm32g0/.cargo/config.toml | 4 ++--
examples/stm32g4/.cargo/config.toml | 4 ++--
examples/stm32h5/.cargo/config.toml | 2 +-
examples/stm32h7/.cargo/config.toml | 2 +-
examples/stm32l0/.cargo/config.toml | 4 ++--
examples/stm32l1/.cargo/config.toml | 4 ++--
examples/stm32l4/.cargo/config.toml | 8 ++++----
examples/stm32l5/.cargo/config.toml | 4 ++--
examples/stm32u5/.cargo/config.toml | 4 ++--
examples/stm32wb/.cargo/config.toml | 4 ++--
examples/stm32wl/.cargo/config.toml | 4 ++--
tests/rp/src/bin/cyw43-perf.rs | 4 ++--
45 files changed, 88 insertions(+), 88 deletions(-)
diff --git a/.vscode/settings.json b/.vscode/settings.json
index 9ef7fe1ce..725fb69d0 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -6,16 +6,16 @@
"rust-analyzer.check.allTargets": false,
"rust-analyzer.check.noDefaultFeatures": true,
"rust-analyzer.cargo.noDefaultFeatures": true,
- "rust-analyzer.cargo.target": "thumbv7em-none-eabi",
+ "rust-analyzer.cargo.target": "thumbv7m-none-eabi",
//"rust-analyzer.cargo.target": "thumbv8m.main-none-eabihf",
"rust-analyzer.cargo.features": [
- "nightly",
+ ///"nightly",
],
"rust-analyzer.linkedProjects": [
// Declare for the target you wish to develop
// "embassy-executor/Cargo.toml",
// "embassy-sync/Cargo.toml",
- "examples/nrf52840/Cargo.toml",
+ "examples/stm32wl/Cargo.toml",
// "examples/nrf5340/Cargo.toml",
// "examples/nrf-rtos-trace/Cargo.toml",
// "examples/rp/Cargo.toml",
diff --git a/cyw43/README.md b/cyw43/README.md
index defea489f..e4a81410d 100644
--- a/cyw43/README.md
+++ b/cyw43/README.md
@@ -1,6 +1,6 @@
# cyw43
-WIP driver for the CYW43439 wifi chip, used in the Raspberry Pi Pico W. Implementation based on [Infineon/wifi-host-driver](https://github.com/Infineon/wifi-host-driver).
+Rust driver for the CYW43439 wifi chip, used in the Raspberry Pi Pico W. Implementation based on [Infineon/wifi-host-driver](https://github.com/Infineon/wifi-host-driver).
## Current status
@@ -19,18 +19,18 @@ Working:
TODO:
- Setting a custom MAC address.
-- Bus sleep (unclear what the benefit is. Is it needed for IRQs? or is it just power consumption optimization?)
+- Bus sleep (for power consumption optimization)
## Running the examples
-- `cargo install probe-rs-cli`
-- `cd examples/rpi-pico-w`
+- `cargo install probe-rs --features cli`
+- `cd examples/rp`
### Example 1: Scan the wifi stations
- `cargo run --release --bin wifi_scan`
### Example 2: Create an access point (IP and credentials in the code)
-- `cargo run --release --bin tcp_server_ap`
+- `cargo run --release --bin wifi_ap_tcp_server`
### Example 3: Connect to an existing network and create a server
-- `WIFI_NETWORK=MyWifiNetwork WIFI_PASSWORD=MyWifiPassword cargo run --release`
+- `WIFI_NETWORK=MyWifiNetwork WIFI_PASSWORD=MyWifiPassword cargo run --release --bin wifi_tcp_server`
After a few seconds, you should see that DHCP picks up an IP address like this
```
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 691545662..d23759f9d 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -410,13 +410,13 @@ pub fn init(config: config::Config) -> Peripherals {
warn!(
"You have requested enabling chip reset functionality on the reset pin, by not enabling the Cargo feature `reset-pin-as-gpio`.\n\
However, UICR is already programmed to some other setting, and can't be changed without erasing it.\n\
- To fix this, erase UICR manually, for example using `probe-rs-cli erase` or `nrfjprog --eraseuicr`."
+ To fix this, erase UICR manually, for example using `probe-rs erase` or `nrfjprog --eraseuicr`."
);
#[cfg(feature = "reset-pin-as-gpio")]
warn!(
"You have requested using the reset pin as GPIO, by enabling the Cargo feature `reset-pin-as-gpio`.\n\
However, UICR is already programmed to some other setting, and can't be changed without erasing it.\n\
- To fix this, erase UICR manually, for example using `probe-rs-cli erase` or `nrfjprog --eraseuicr`."
+ To fix this, erase UICR manually, for example using `probe-rs erase` or `nrfjprog --eraseuicr`."
);
}
}
@@ -432,7 +432,7 @@ pub fn init(config: config::Config) -> Peripherals {
warn!(
"You have requested to use P0.09 and P0.10 pins for NFC, by not enabling the Cargo feature `nfc-pins-as-gpio`.\n\
However, UICR is already programmed to some other setting, and can't be changed without erasing it.\n\
- To fix this, erase UICR manually, for example using `probe-rs-cli erase` or `nrfjprog --eraseuicr`."
+ To fix this, erase UICR manually, for example using `probe-rs erase` or `nrfjprog --eraseuicr`."
);
}
}
diff --git a/examples/boot/application/nrf/.cargo/config.toml b/examples/boot/application/nrf/.cargo/config.toml
index 3872e7189..17616a054 100644
--- a/examples/boot/application/nrf/.cargo/config.toml
+++ b/examples/boot/application/nrf/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace nRF82840_xxAA with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip nRF52840_xxAA"
+# replace nRF82840_xxAA with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip nRF52840_xxAA"
[build]
target = "thumbv7em-none-eabi"
diff --git a/examples/boot/application/rp/.cargo/config.toml b/examples/boot/application/rp/.cargo/config.toml
index 278c24a57..cd8d1ef02 100644
--- a/examples/boot/application/rp/.cargo/config.toml
+++ b/examples/boot/application/rp/.cargo/config.toml
@@ -3,7 +3,7 @@ build-std = ["core"]
build-std-features = ["panic_immediate_abort"]
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-runner = "probe-rs-cli run --chip RP2040"
+runner = "probe-rs run --chip RP2040"
[build]
target = "thumbv6m-none-eabi"
diff --git a/examples/boot/application/stm32f3/.cargo/config.toml b/examples/boot/application/stm32f3/.cargo/config.toml
index 9fc2396e8..4a7ec0a5b 100644
--- a/examples/boot/application/stm32f3/.cargo/config.toml
+++ b/examples/boot/application/stm32f3/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32F429ZITx with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32F303VCTx"
+# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32F303VCTx"
[build]
target = "thumbv7em-none-eabihf"
diff --git a/examples/boot/application/stm32f7/.cargo/config.toml b/examples/boot/application/stm32f7/.cargo/config.toml
index 7d6c88a99..9088eea6e 100644
--- a/examples/boot/application/stm32f7/.cargo/config.toml
+++ b/examples/boot/application/stm32f7/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32F429ZITx with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32F767ZITx"
+# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32F767ZITx"
[build]
target = "thumbv7em-none-eabihf"
diff --git a/examples/boot/application/stm32h7/.cargo/config.toml b/examples/boot/application/stm32h7/.cargo/config.toml
index 067a5c89b..caa0d3a93 100644
--- a/examples/boot/application/stm32h7/.cargo/config.toml
+++ b/examples/boot/application/stm32h7/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32F429ZITx with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32H743ZITx"
+# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32H743ZITx"
[build]
target = "thumbv7em-none-eabihf"
diff --git a/examples/boot/application/stm32h7/flash-boot.sh b/examples/boot/application/stm32h7/flash-boot.sh
index a3003681a..4912a50b7 100755
--- a/examples/boot/application/stm32h7/flash-boot.sh
+++ b/examples/boot/application/stm32h7/flash-boot.sh
@@ -1,5 +1,5 @@
#!/bin/bash
-probe-rs-cli erase --chip STM32H743ZITx
+probe-rs erase --chip STM32H743ZITx
mv ../../bootloader/stm32/memory.x ../../bootloader/stm32/memory-old.x
cp memory-bl.x ../../bootloader/stm32/memory.x
diff --git a/examples/boot/application/stm32l0/.cargo/config.toml b/examples/boot/application/stm32l0/.cargo/config.toml
index ce0e460bd..6099f015c 100644
--- a/examples/boot/application/stm32l0/.cargo/config.toml
+++ b/examples/boot/application/stm32l0/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32L072CZTx"
+# replace your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32L072CZTx"
[build]
target = "thumbv6m-none-eabi"
diff --git a/examples/boot/application/stm32l1/.cargo/config.toml b/examples/boot/application/stm32l1/.cargo/config.toml
index 1401500a0..9cabd14ba 100644
--- a/examples/boot/application/stm32l1/.cargo/config.toml
+++ b/examples/boot/application/stm32l1/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32L151CBxxA"
+# replace your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32L151CBxxA"
[build]
target = "thumbv7m-none-eabi"
diff --git a/examples/boot/application/stm32l4/.cargo/config.toml b/examples/boot/application/stm32l4/.cargo/config.toml
index 48ff3734b..c803215f6 100644
--- a/examples/boot/application/stm32l4/.cargo/config.toml
+++ b/examples/boot/application/stm32l4/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32L475VG"
+# replace your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32L475VG"
[build]
target = "thumbv7em-none-eabihf"
diff --git a/examples/boot/application/stm32wl/.cargo/config.toml b/examples/boot/application/stm32wl/.cargo/config.toml
index b49b582e0..4f8094ff2 100644
--- a/examples/boot/application/stm32wl/.cargo/config.toml
+++ b/examples/boot/application/stm32wl/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32WLE5JCIx"
+# replace your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32WLE5JCIx"
[build]
target = "thumbv7em-none-eabihf"
diff --git a/examples/boot/bootloader/nrf/.cargo/config.toml b/examples/boot/bootloader/nrf/.cargo/config.toml
index d636b1d23..c292846aa 100644
--- a/examples/boot/bootloader/nrf/.cargo/config.toml
+++ b/examples/boot/bootloader/nrf/.cargo/config.toml
@@ -4,7 +4,7 @@ build-std-features = ["panic_immediate_abort"]
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
#runner = "./fruitrunner"
-runner = "probe-rs-cli run --chip nrf52840_xxAA"
+runner = "probe-rs run --chip nrf52840_xxAA"
rustflags = [
# Code-size optimizations.
diff --git a/examples/boot/bootloader/rp/.cargo/config.toml b/examples/boot/bootloader/rp/.cargo/config.toml
index 795ee043a..9d48ecdc9 100644
--- a/examples/boot/bootloader/rp/.cargo/config.toml
+++ b/examples/boot/bootloader/rp/.cargo/config.toml
@@ -1,5 +1,5 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-runner = "probe-rs-cli run --chip RP2040"
+runner = "probe-rs run --chip RP2040"
[build]
target = "thumbv6m-none-eabi"
diff --git a/examples/nrf-rtos-trace/.cargo/config.toml b/examples/nrf-rtos-trace/.cargo/config.toml
index 3872e7189..17616a054 100644
--- a/examples/nrf-rtos-trace/.cargo/config.toml
+++ b/examples/nrf-rtos-trace/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace nRF82840_xxAA with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip nRF52840_xxAA"
+# replace nRF82840_xxAA with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip nRF52840_xxAA"
[build]
target = "thumbv7em-none-eabi"
diff --git a/examples/nrf52840-rtic/.cargo/config.toml b/examples/nrf52840-rtic/.cargo/config.toml
index 3872e7189..17616a054 100644
--- a/examples/nrf52840-rtic/.cargo/config.toml
+++ b/examples/nrf52840-rtic/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace nRF82840_xxAA with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip nRF52840_xxAA"
+# replace nRF82840_xxAA with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip nRF52840_xxAA"
[build]
target = "thumbv7em-none-eabi"
diff --git a/examples/nrf52840/.cargo/config.toml b/examples/nrf52840/.cargo/config.toml
index 3872e7189..17616a054 100644
--- a/examples/nrf52840/.cargo/config.toml
+++ b/examples/nrf52840/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace nRF82840_xxAA with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip nRF52840_xxAA"
+# replace nRF82840_xxAA with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip nRF52840_xxAA"
[build]
target = "thumbv7em-none-eabi"
diff --git a/examples/nrf52840/src/bin/nvmc.rs b/examples/nrf52840/src/bin/nvmc.rs
index 33a44516d..31c6fe4b6 100644
--- a/examples/nrf52840/src/bin/nvmc.rs
+++ b/examples/nrf52840/src/bin/nvmc.rs
@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_nrf::init(Default::default());
info!("Hello NVMC!");
- // probe-rs-cli run breaks without this, I'm not sure why.
+ // probe-rs run breaks without this, I'm not sure why.
Timer::after(Duration::from_secs(1)).await;
let mut f = Nvmc::new(p.NVMC);
diff --git a/examples/nrf52840/src/bin/wdt.rs b/examples/nrf52840/src/bin/wdt.rs
index ccfd0e439..058746518 100644
--- a/examples/nrf52840/src/bin/wdt.rs
+++ b/examples/nrf52840/src/bin/wdt.rs
@@ -16,7 +16,7 @@ async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.timeout_ticks = 32768 * 3; // 3 seconds
- // This is needed for `probe-rs-cli run` to be able to catch the panic message
+ // This is needed for `probe-rs run` to be able to catch the panic message
// in the WDT interrupt. The core resets 2 ticks after firing the interrupt.
config.run_during_debug_halt = false;
diff --git a/examples/nrf5340/.cargo/config.toml b/examples/nrf5340/.cargo/config.toml
index d25355894..4c3cf3d32 100644
--- a/examples/nrf5340/.cargo/config.toml
+++ b/examples/nrf5340/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace nRF5340_xxAA with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip nRF5340_xxAA"
+# replace nRF5340_xxAA with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip nRF5340_xxAA"
[build]
target = "thumbv8m.main-none-eabihf"
diff --git a/examples/rp/.cargo/config.toml b/examples/rp/.cargo/config.toml
index 2ee6fcb00..3d7d61740 100644
--- a/examples/rp/.cargo/config.toml
+++ b/examples/rp/.cargo/config.toml
@@ -1,5 +1,5 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-runner = "probe-rs-cli run --chip RP2040"
+runner = "probe-rs run --chip RP2040"
[build]
target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
diff --git a/examples/rp/src/bin/wifi_ap_tcp_server.rs b/examples/rp/src/bin/wifi_ap_tcp_server.rs
index e8197390c..310e84d92 100644
--- a/examples/rp/src/bin/wifi_ap_tcp_server.rs
+++ b/examples/rp/src/bin/wifi_ap_tcp_server.rs
@@ -42,8 +42,8 @@ async fn main(spawner: Spawner) {
// To make flashing faster for development, you may want to flash the firmwares independently
// at hardcoded addresses, instead of baking them into the program with `include_bytes!`:
- // probe-rs-cli download 43439A0.bin --format bin --chip RP2040 --base-address 0x10100000
- // probe-rs-cli download 43439A0_clm.bin --format bin --chip RP2040 --base-address 0x10140000
+ // probe-rs download 43439A0.bin --format bin --chip RP2040 --base-address 0x10100000
+ // probe-rs download 43439A0_clm.bin --format bin --chip RP2040 --base-address 0x10140000
//let fw = unsafe { core::slice::from_raw_parts(0x10100000 as *const u8, 224190) };
//let clm = unsafe { core::slice::from_raw_parts(0x10140000 as *const u8, 4752) };
diff --git a/examples/rp/src/bin/wifi_blinky.rs b/examples/rp/src/bin/wifi_blinky.rs
index be965807b..bbcb1b5ec 100644
--- a/examples/rp/src/bin/wifi_blinky.rs
+++ b/examples/rp/src/bin/wifi_blinky.rs
@@ -27,8 +27,8 @@ async fn main(spawner: Spawner) {
// To make flashing faster for development, you may want to flash the firmwares independently
// at hardcoded addresses, instead of baking them into the program with `include_bytes!`:
- // probe-rs-cli download 43439A0.bin --format bin --chip RP2040 --base-address 0x10100000
- // probe-rs-cli download 43439A0_clm.bin --format bin --chip RP2040 --base-address 0x10140000
+ // probe-rs download 43439A0.bin --format bin --chip RP2040 --base-address 0x10100000
+ // probe-rs download 43439A0_clm.bin --format bin --chip RP2040 --base-address 0x10140000
//let fw = unsafe { core::slice::from_raw_parts(0x10100000 as *const u8, 224190) };
//let clm = unsafe { core::slice::from_raw_parts(0x10140000 as *const u8, 4752) };
diff --git a/examples/rp/src/bin/wifi_scan.rs b/examples/rp/src/bin/wifi_scan.rs
index 79534f229..391e12282 100644
--- a/examples/rp/src/bin/wifi_scan.rs
+++ b/examples/rp/src/bin/wifi_scan.rs
@@ -39,8 +39,8 @@ async fn main(spawner: Spawner) {
// To make flashing faster for development, you may want to flash the firmwares independently
// at hardcoded addresses, instead of baking them into the program with `include_bytes!`:
- // probe-rs-cli download 43439A0.bin --format bin --chip RP2040 --base-address 0x10100000
- // probe-rs-cli download 43439A0_clm.bin --format bin --chip RP2040 --base-address 0x10140000
+ // probe-rs download 43439A0.bin --format bin --chip RP2040 --base-address 0x10100000
+ // probe-rs download 43439A0_clm.bin --format bin --chip RP2040 --base-address 0x10140000
//let fw = unsafe { core::slice::from_raw_parts(0x10100000 as *const u8, 224190) };
//let clm = unsafe { core::slice::from_raw_parts(0x10140000 as *const u8, 4752) };
diff --git a/examples/rp/src/bin/wifi_tcp_server.rs b/examples/rp/src/bin/wifi_tcp_server.rs
index 026e056fa..e9d1079a6 100644
--- a/examples/rp/src/bin/wifi_tcp_server.rs
+++ b/examples/rp/src/bin/wifi_tcp_server.rs
@@ -42,8 +42,8 @@ async fn main(spawner: Spawner) {
// To make flashing faster for development, you may want to flash the firmwares independently
// at hardcoded addresses, instead of baking them into the program with `include_bytes!`:
- // probe-rs-cli download 43439A0.bin --format bin --chip RP2040 --base-address 0x10100000
- // probe-rs-cli download 43439A0_clm.bin --format bin --chip RP2040 --base-address 0x10140000
+ // probe-rs download 43439A0.bin --format bin --chip RP2040 --base-address 0x10100000
+ // probe-rs download 43439A0_clm.bin --format bin --chip RP2040 --base-address 0x10140000
//let fw = unsafe { core::slice::from_raw_parts(0x10100000 as *const u8, 224190) };
//let clm = unsafe { core::slice::from_raw_parts(0x10140000 as *const u8, 4752) };
diff --git a/examples/stm32c0/.cargo/config.toml b/examples/stm32c0/.cargo/config.toml
index 517101fae..29a8be7e1 100644
--- a/examples/stm32c0/.cargo/config.toml
+++ b/examples/stm32c0/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32G071C8Rx with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --speed 100 --chip STM32c031c6tx"
+# replace STM32G071C8Rx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --speed 100 --chip STM32c031c6tx"
[build]
target = "thumbv6m-none-eabi"
diff --git a/examples/stm32f0/.cargo/config.toml b/examples/stm32f0/.cargo/config.toml
index bd0c0cd97..def4c8c92 100644
--- a/examples/stm32f0/.cargo/config.toml
+++ b/examples/stm32f0/.cargo/config.toml
@@ -1,5 +1,5 @@
[target.thumbv6m-none-eabi]
-runner = 'probe-rs-cli run --chip STM32F091RCTX'
+runner = 'probe-rs run --chip STM32F091RCTX'
[build]
target = "thumbv6m-none-eabi"
diff --git a/examples/stm32f1/.cargo/config.toml b/examples/stm32f1/.cargo/config.toml
index 81199c5aa..ce6fef11b 100644
--- a/examples/stm32f1/.cargo/config.toml
+++ b/examples/stm32f1/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32F103C8 with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32F103C8"
+# replace STM32F103C8 with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32F103C8"
[build]
target = "thumbv7m-none-eabi"
diff --git a/examples/stm32f2/.cargo/config.toml b/examples/stm32f2/.cargo/config.toml
index 5532779c8..1198fcab8 100644
--- a/examples/stm32f2/.cargo/config.toml
+++ b/examples/stm32f2/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32F207ZGTx with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32F207ZGTx"
+# replace STM32F207ZGTx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32F207ZGTx"
[build]
target = "thumbv7m-none-eabi"
diff --git a/examples/stm32f3/.cargo/config.toml b/examples/stm32f3/.cargo/config.toml
index 7f3fda529..cb8a7c5af 100644
--- a/examples/stm32f3/.cargo/config.toml
+++ b/examples/stm32f3/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32F429ZITx with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32F303ZETx"
+# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32F303ZETx"
[build]
target = "thumbv7em-none-eabihf"
diff --git a/examples/stm32f4/.cargo/config.toml b/examples/stm32f4/.cargo/config.toml
index bed04b68f..16efa8e6f 100644
--- a/examples/stm32f4/.cargo/config.toml
+++ b/examples/stm32f4/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32F429ZITx with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32F429ZITx"
+# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32F429ZITx"
[build]
target = "thumbv7em-none-eabi"
diff --git a/examples/stm32f7/.cargo/config.toml b/examples/stm32f7/.cargo/config.toml
index 7d6c88a99..9088eea6e 100644
--- a/examples/stm32f7/.cargo/config.toml
+++ b/examples/stm32f7/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32F429ZITx with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32F767ZITx"
+# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32F767ZITx"
[build]
target = "thumbv7em-none-eabihf"
diff --git a/examples/stm32g0/.cargo/config.toml b/examples/stm32g0/.cargo/config.toml
index a7a5fbd84..35cca5412 100644
--- a/examples/stm32g0/.cargo/config.toml
+++ b/examples/stm32g0/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32G071C8Rx with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32G071RBTx"
+# replace STM32G071C8Rx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32G071RBTx"
[build]
target = "thumbv6m-none-eabi"
diff --git a/examples/stm32g4/.cargo/config.toml b/examples/stm32g4/.cargo/config.toml
index 606d7d5a3..d28ad069e 100644
--- a/examples/stm32g4/.cargo/config.toml
+++ b/examples/stm32g4/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32G071C8Rx with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32G484VETx"
+# replace STM32G071C8Rx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32G484VETx"
[build]
target = "thumbv7em-none-eabi"
diff --git a/examples/stm32h5/.cargo/config.toml b/examples/stm32h5/.cargo/config.toml
index c8b864b6c..478146142 100644
--- a/examples/stm32h5/.cargo/config.toml
+++ b/examples/stm32h5/.cargo/config.toml
@@ -1,5 +1,5 @@
[target.thumbv8m.main-none-eabihf]
-runner = 'probe-rs-cli run --chip STM32H563ZITx'
+runner = 'probe-rs run --chip STM32H563ZITx'
[build]
target = "thumbv8m.main-none-eabihf"
diff --git a/examples/stm32h7/.cargo/config.toml b/examples/stm32h7/.cargo/config.toml
index f08f57a54..5f680dbce 100644
--- a/examples/stm32h7/.cargo/config.toml
+++ b/examples/stm32h7/.cargo/config.toml
@@ -1,5 +1,5 @@
[target.thumbv7em-none-eabihf]
-runner = 'probe-rs-cli run --chip STM32H743ZITx'
+runner = 'probe-rs run --chip STM32H743ZITx'
[build]
target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
diff --git a/examples/stm32l0/.cargo/config.toml b/examples/stm32l0/.cargo/config.toml
index 526f5a1f7..b050334b2 100644
--- a/examples/stm32l0/.cargo/config.toml
+++ b/examples/stm32l0/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32L053R8Tx"
+# replace your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32L053R8Tx"
[build]
target = "thumbv6m-none-eabi"
diff --git a/examples/stm32l1/.cargo/config.toml b/examples/stm32l1/.cargo/config.toml
index 1401500a0..9cabd14ba 100644
--- a/examples/stm32l1/.cargo/config.toml
+++ b/examples/stm32l1/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32L151CBxxA"
+# replace your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32L151CBxxA"
[build]
target = "thumbv7m-none-eabi"
diff --git a/examples/stm32l4/.cargo/config.toml b/examples/stm32l4/.cargo/config.toml
index abf55eb2e..36e74e5a5 100644
--- a/examples/stm32l4/.cargo/config.toml
+++ b/examples/stm32l4/.cargo/config.toml
@@ -1,8 +1,8 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32F429ZITx with your chip as listed in `probe-rs-cli chip list`
-#runner = "probe-rs-cli run --chip STM32L475VGT6"
-#runner = "probe-rs-cli run --chip STM32L475VG"
-runner = "probe-rs-cli run --chip STM32L4S5VI"
+# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
+#runner = "probe-rs run --chip STM32L475VGT6"
+#runner = "probe-rs run --chip STM32L475VG"
+runner = "probe-rs run --chip STM32L4S5VI"
[build]
target = "thumbv7em-none-eabi"
diff --git a/examples/stm32l5/.cargo/config.toml b/examples/stm32l5/.cargo/config.toml
index 1dc3a6fb7..86a145a27 100644
--- a/examples/stm32l5/.cargo/config.toml
+++ b/examples/stm32l5/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32L552ZETxQ with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32L552ZETxQ"
+# replace STM32L552ZETxQ with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32L552ZETxQ"
[build]
target = "thumbv8m.main-none-eabihf"
diff --git a/examples/stm32u5/.cargo/config.toml b/examples/stm32u5/.cargo/config.toml
index cecd01938..36c5b63a6 100644
--- a/examples/stm32u5/.cargo/config.toml
+++ b/examples/stm32u5/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32U585AIIx with your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32U585AIIx"
+# replace STM32U585AIIx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32U585AIIx"
[build]
target = "thumbv8m.main-none-eabihf"
diff --git a/examples/stm32wb/.cargo/config.toml b/examples/stm32wb/.cargo/config.toml
index 35317a297..8b6d6d754 100644
--- a/examples/stm32wb/.cargo/config.toml
+++ b/examples/stm32wb/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace STM32WB55CCUx with your chip as listed in `probe-rs-cli chip list`
-# runner = "probe-rs-cli run --chip STM32WB55RGVx --speed 1000 --connect-under-reset"
+# replace STM32WB55CCUx with your chip as listed in `probe-rs chip list`
+# runner = "probe-rs run --chip STM32WB55RGVx --speed 1000 --connect-under-reset"
runner = "teleprobe local run --chip STM32WB55RG --elf"
[build]
diff --git a/examples/stm32wl/.cargo/config.toml b/examples/stm32wl/.cargo/config.toml
index b49b582e0..4f8094ff2 100644
--- a/examples/stm32wl/.cargo/config.toml
+++ b/examples/stm32wl/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace your chip as listed in `probe-rs-cli chip list`
-runner = "probe-rs-cli run --chip STM32WLE5JCIx"
+# replace your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32WLE5JCIx"
[build]
target = "thumbv7em-none-eabihf"
diff --git a/tests/rp/src/bin/cyw43-perf.rs b/tests/rp/src/bin/cyw43-perf.rs
index 9fc537a4b..1ecaab266 100644
--- a/tests/rp/src/bin/cyw43-perf.rs
+++ b/tests/rp/src/bin/cyw43-perf.rs
@@ -44,8 +44,8 @@ async fn main(spawner: Spawner) {
}
// cyw43 firmware needs to be flashed manually:
- // probe-rs-cli download 43439A0.bin --format bin --chip RP2040 --base-address 0x101c0000
- // probe-rs-cli download 43439A0_clm.bin --format bin --chip RP2040 --base-address 0x101f8000
+ // probe-rs download 43439A0.bin --format bin --chip RP2040 --base-address 0x101c0000
+ // probe-rs download 43439A0_clm.bin --format bin --chip RP2040 --base-address 0x101f8000
let fw = unsafe { core::slice::from_raw_parts(0x101c0000 as *const u8, 224190) };
let clm = unsafe { core::slice::from_raw_parts(0x101f8000 as *const u8, 4752) };
From 01101e3df0619dca85ab692be8b7c38f249b44e8 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Thu, 29 Jun 2023 03:11:22 +0200
Subject: [PATCH 41/48] Update readme
---
README.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/README.md b/README.md
index 315d247ee..b05e55aa5 100644
--- a/README.md
+++ b/README.md
@@ -99,10 +99,10 @@ Examples are found in the `examples/` folder seperated by the chip manufacturer
### Running examples
-- Install `probe-rs-cli` with defmt support.
+- Install `probe-rs`.
```bash
-cargo install probe-rs-cli
+cargo install probe-rs --features cli
```
- Change directory to the sample's base directory. For example:
From 96f1525ffe675b7e3ca26f038bc558488c03af9b Mon Sep 17 00:00:00 2001
From: Julian <20155974+JuliDi@users.noreply.github.com>
Date: Thu, 29 Jun 2023 09:20:25 +0200
Subject: [PATCH 42/48] Revert changes to dma.rs
---
embassy-stm32/src/dma/dma.rs | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
index 9c03599eb..8abe541d3 100644
--- a/embassy-stm32/src/dma/dma.rs
+++ b/embassy-stm32/src/dma/dma.rs
@@ -405,11 +405,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
pub fn is_running(&mut self) -> bool {
let ch = self.channel.regs().st(self.channel.num());
- let en = ch.cr().read().en();
- // Check if circular mode is enabled, if so it will still be running even if tcif == 1
- let circular = ch.cr().read().circ() == vals::Circ::ENABLED;
- let tcif = STATE.complete_count[self.channel.index()].load(Ordering::Acquire) != 0;
- en && (circular || !tcif)
+ ch.cr().read().en()
}
/// Gets the total remaining transfers for the channel
From f0b17675d89f87350faa8c61b491be53ef666894 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Thu, 29 Jun 2023 12:20:51 +0200
Subject: [PATCH 43/48] usb: add missing builder reexports.
Fixes #1176
cc #1596
---
embassy-usb/src/class/cdc_ncm/mod.rs | 4 ++--
embassy-usb/src/lib.rs | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/embassy-usb/src/class/cdc_ncm/mod.rs b/embassy-usb/src/class/cdc_ncm/mod.rs
index d5556dd0b..fcfa0bfcd 100644
--- a/embassy-usb/src/class/cdc_ncm/mod.rs
+++ b/embassy-usb/src/class/cdc_ncm/mod.rs
@@ -11,8 +11,8 @@
//! - On Pixel 4a, it refused to work on Android 11, worked on Android 12.
//! - if the host's MAC address has the "locally-administered" bit set (bit 1 of first byte),
//! it doesn't work! The "Ethernet tethering" option in settings doesn't get enabled.
-//! This is due to regex spaghetti: https://android.googlesource.com/platform/frameworks/base/+/refs/tags/android-mainline-12.0.0_r84/core/res/res/values/config.xml#417
-//! and this nonsense in the linux kernel: https://github.com/torvalds/linux/blob/c00c5e1d157bec0ef0b0b59aa5482eb8dc7e8e49/drivers/net/usb/usbnet.c#L1751-L1757
+//! This is due to regex spaghetti:
+//! and this nonsense in the linux kernel:
use core::intrinsics::copy_nonoverlapping;
use core::mem::{size_of, MaybeUninit};
diff --git a/embassy-usb/src/lib.rs b/embassy-usb/src/lib.rs
index d8563d59a..1180b9b66 100644
--- a/embassy-usb/src/lib.rs
+++ b/embassy-usb/src/lib.rs
@@ -23,7 +23,7 @@ mod config {
use embassy_futures::select::{select, Either};
use heapless::Vec;
-pub use crate::builder::{Builder, Config};
+pub use crate::builder::{Builder, Config, FunctionBuilder, InterfaceAltBuilder, InterfaceBuilder};
use crate::config::*;
use crate::control::*;
use crate::descriptor::*;
From 837d3bcdbb87af69d13cb799a137ad88ee015538 Mon Sep 17 00:00:00 2001
From: Kaspar Schleiser
Date: Thu, 29 Jun 2023 14:43:31 +0200
Subject: [PATCH 44/48] embassy-boot/nrf/README.md: typo fix
---
embassy-boot/nrf/README.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-boot/nrf/README.md b/embassy-boot/nrf/README.md
index 7ce3c7021..fe581823d 100644
--- a/embassy-boot/nrf/README.md
+++ b/embassy-boot/nrf/README.md
@@ -6,7 +6,7 @@ An adaptation of `embassy-boot` for nRF.
## Features
-* Load applications with our without the softdevice.
+* Load applications with or without the softdevice.
* Configure bootloader partitions based on linker script.
* Using watchdog timer to detect application failure.
From 2aa2b843ce6b96aacd72e52fe29b550e7ebc55b3 Mon Sep 17 00:00:00 2001
From: Cameron
Date: Thu, 29 Jun 2023 17:11:36 +0200
Subject: [PATCH 45/48] feature(1355): Add trigger to task, triggered + clear
to Event
---
embassy-nrf/src/ppi/mod.rs | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/embassy-nrf/src/ppi/mod.rs b/embassy-nrf/src/ppi/mod.rs
index 7c18da6ee..ba95849e8 100644
--- a/embassy-nrf/src/ppi/mod.rs
+++ b/embassy-nrf/src/ppi/mod.rs
@@ -137,6 +137,11 @@ impl Task {
Self(ptr)
}
+ // Triggers this task.
+ pub unsafe fn trigger(&mut self) {
+ self.0.write(|w| unsafe { w.bits(1) });
+ }
+
pub(crate) fn from_reg(reg: &T) -> Self {
Self(unsafe { NonNull::new_unchecked(reg as *const _ as *mut _) })
}
@@ -173,6 +178,16 @@ impl Event {
Self(unsafe { NonNull::new_unchecked(reg as *const _ as *mut _) })
}
+ // Describes whether this Event is currently in a triggered state.
+ pub unsafe fn is_triggered(&self) -> bool {
+ self.0.read().bits() == 1
+ }
+
+ // Clear the current register's triggered state, reverting it to 0.
+ pub unsafe fn clear(&mut self) {
+ self.0.write(|w| unsafe { w.bits(0) });
+ }
+
/// Address of publish register for this event.
#[cfg(feature = "_dppi")]
pub fn publish_reg(&self) -> *mut u32 {
From e90f47aba31be9d99935c758d87941c7106cbece Mon Sep 17 00:00:00 2001
From: Cameron
Date: Thu, 29 Jun 2023 17:37:51 +0200
Subject: [PATCH 46/48] Fixed Pointer Updates
---
embassy-nrf/src/ppi/mod.rs | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/embassy-nrf/src/ppi/mod.rs b/embassy-nrf/src/ppi/mod.rs
index ba95849e8..0789e2694 100644
--- a/embassy-nrf/src/ppi/mod.rs
+++ b/embassy-nrf/src/ppi/mod.rs
@@ -137,9 +137,9 @@ impl Task {
Self(ptr)
}
- // Triggers this task.
+ /// Triggers this task.
pub unsafe fn trigger(&mut self) {
- self.0.write(|w| unsafe { w.bits(1) });
+ *self.0.as_ptr() = 1;
}
pub(crate) fn from_reg(reg: &T) -> Self {
@@ -178,14 +178,14 @@ impl Event {
Self(unsafe { NonNull::new_unchecked(reg as *const _ as *mut _) })
}
- // Describes whether this Event is currently in a triggered state.
+ /// Describes whether this Event is currently in a triggered state.
pub unsafe fn is_triggered(&self) -> bool {
- self.0.read().bits() == 1
+ *self.0.as_ptr() == 1
}
- // Clear the current register's triggered state, reverting it to 0.
+ /// Clear the current register's triggered state, reverting it to 0.
pub unsafe fn clear(&mut self) {
- self.0.write(|w| unsafe { w.bits(0) });
+ *self.0.as_ptr() = 0;
}
/// Address of publish register for this event.
From 3f19879f41e8c39c5c38e7905a180160b24807fc Mon Sep 17 00:00:00 2001
From: Cameron
Date: Thu, 29 Jun 2023 17:44:46 +0200
Subject: [PATCH 47/48] PR Fixes
---
embassy-nrf/src/ppi/mod.rs | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/embassy-nrf/src/ppi/mod.rs b/embassy-nrf/src/ppi/mod.rs
index 0789e2694..76757a248 100644
--- a/embassy-nrf/src/ppi/mod.rs
+++ b/embassy-nrf/src/ppi/mod.rs
@@ -138,8 +138,8 @@ impl Task {
}
/// Triggers this task.
- pub unsafe fn trigger(&mut self) {
- *self.0.as_ptr() = 1;
+ pub fn trigger(&mut self) {
+ unsafe { self.0.as_ptr().write_volatile(1) };
}
pub(crate) fn from_reg(reg: &T) -> Self {
@@ -179,13 +179,13 @@ impl Event {
}
/// Describes whether this Event is currently in a triggered state.
- pub unsafe fn is_triggered(&self) -> bool {
- *self.0.as_ptr() == 1
+ pub fn is_triggered(&self) -> bool {
+ unsafe { self.0.as_ptr().read_volatile() == 1 }
}
/// Clear the current register's triggered state, reverting it to 0.
- pub unsafe fn clear(&mut self) {
- *self.0.as_ptr() = 0;
+ pub fn clear(&mut self) {
+ unsafe { self.0.as_ptr().write_volatile(0) };
}
/// Address of publish register for this event.
From 6eac49186d5a5da4c310027e59adcd0bf44ae514 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis
Date: Thu, 29 Jun 2023 19:51:16 +0200
Subject: [PATCH 48/48] Release embassy-net v0.1
---
embassy-net-driver-channel/Cargo.toml | 11 +++
embassy-net-driver-channel/README.md | 96 ++++++++++++++++++++
embassy-net-driver-channel/src/lib.rs | 1 +
embassy-net-driver/Cargo.toml | 11 ++-
embassy-net-driver/README.md | 16 ++++
embassy-net-w5500/src/lib.rs | 5 +-
embassy-net/Cargo.toml | 9 +-
embassy-net/README.md | 64 +++++++++----
embassy-net/src/lib.rs | 24 ++++-
embassy-usb/src/class/cdc_ncm/embassy_net.rs | 5 +-
examples/std/README.md | 23 +++++
11 files changed, 238 insertions(+), 27 deletions(-)
create mode 100644 embassy-net-driver-channel/README.md
create mode 100644 examples/std/README.md
diff --git a/embassy-net-driver-channel/Cargo.toml b/embassy-net-driver-channel/Cargo.toml
index e475551e1..bee2e3021 100644
--- a/embassy-net-driver-channel/Cargo.toml
+++ b/embassy-net-driver-channel/Cargo.toml
@@ -2,6 +2,14 @@
name = "embassy-net-driver-channel"
version = "0.1.0"
edition = "2021"
+license = "MIT OR Apache-2.0"
+description = "High-level channel-based driver for the `embassy-net` async TCP/IP network stack."
+repository = "https://github.com/embassy-rs/embassy"
+categories = [
+ "embedded",
+ "no-std",
+ "asynchronous",
+]
[package.metadata.embassy_docs]
src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-driver-channel-v$VERSION/embassy-net-driver-channel/src/"
@@ -9,6 +17,9 @@ src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-d
features = ["defmt"]
target = "thumbv7em-none-eabi"
+[package.metadata.docs.rs]
+features = ["defmt"]
+
[dependencies]
defmt = { version = "0.3", optional = true }
log = { version = "0.4.14", optional = true }
diff --git a/embassy-net-driver-channel/README.md b/embassy-net-driver-channel/README.md
new file mode 100644
index 000000000..dd90e7ad2
--- /dev/null
+++ b/embassy-net-driver-channel/README.md
@@ -0,0 +1,96 @@
+# embassy-net-driver-channel
+
+This crate provides a toolkit for implementing [`embassy-net`](https://crates.io/crates/embassy-net) drivers in a
+higher level way than implementing the [`embassy-net-driver`](https://crates.io/crates/embassy-net-driver) trait directly.
+
+The `embassy-net-driver` trait is polling-based. To implement it, you must write the packet receive/transmit state machines by
+hand, and hook up the `Waker`s provided by `embassy-net` to the right interrupt handlers so that `embassy-net`
+knows when to poll your driver again to make more progress.
+
+With `embassy-net-driver-channel`
+
+## A note about deadlocks
+
+When implementing a driver using this crate, it might be tempting to write it in the most straightforward way:
+
+```rust,ignore
+loop {
+ // Wait for either..
+ match select(
+ // ... the chip signaling an interrupt, indicating a packet is available to receive, or
+ irq_pin.wait_for_low(),
+ // ... a TX buffer becoming available, i.e. embassy-net wants to send a packet
+ tx_chan.tx_buf(),
+ ).await {
+ Either::First(_) => {
+ // a packet is ready to be received!
+ let buf = rx_chan.rx_buf().await; // allocate a rx buf from the packet queue
+ let n = receive_packet_over_spi(buf).await;
+ rx_chan.rx_done(n);
+ }
+ Either::Second(buf) => {
+ // a packet is ready to be sent!
+ send_packet_over_spi(buf).await;
+ tx_chan.tx_done();
+ }
+ }
+}
+```
+
+However, this code has a latent deadlock bug. The symptom is it can hang at `rx_chan.rx_buf().await` under load.
+
+The reason is that, under load, both the TX and RX queues can get full at the same time. When this happens, the `embassy-net` task stalls trying to send because the TX queue is full, therefore it stops processing packets in the RX queue. Your driver task also stalls because the RX queue is full, therefore it stops processing packets in the TX queue.
+
+The fix is to make sure to always service the TX queue while you're waiting for space to become available in the TX queue. For example, select on either "tx_chan.tx_buf() available" or "INT is low AND rx_chan.rx_buf() available":
+
+```rust,ignore
+loop {
+ // Wait for either..
+ match select(
+ async {
+ // ... the chip signaling an interrupt, indicating a packet is available to receive
+ irq_pin.wait_for_low().await;
+ // *AND* the buffer is ready...
+ rx_chan.rx_buf().await
+ },
+ // ... or a TX buffer becoming available, i.e. embassy-net wants to send a packet
+ tx_chan.tx_buf(),
+ ).await {
+ Either::First(buf) => {
+ // a packet is ready to be received!
+ let n = receive_packet_over_spi(buf).await;
+ rx_chan.rx_done(n);
+ }
+ Either::Second(buf) => {
+ // a packet is ready to be sent!
+ send_packet_over_spi(buf).await;
+ tx_chan.tx_done();
+ }
+ }
+}
+```
+
+## Examples
+
+These `embassy-net` drivers are implemented using this crate. You can look at them for inspiration.
+
+- [`cyw43`](https://github.com/embassy-rs/embassy/tree/main/cyw43) for WiFi on CYW43xx chips, used in the Raspberry Pi Pico W
+- [`embassy-usb`](https://github.com/embassy-rs/embassy/tree/main/embassy-usb) for Ethernet-over-USB (CDC NCM) support.
+- [`embassy-net-w5500`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-w5500) for Wiznet W5500 SPI Ethernet MAC+PHY chip.
+- [`embassy-net-esp-hosted`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-esp-hosted) for using ESP32 chips with the [`esp-hosted`](https://github.com/espressif/esp-hosted) firmware as WiFi adapters for another non-ESP32 MCU.
+
+
+## Interoperability
+
+This crate can run on any executor.
+
+
+## License
+
+This work is licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+ http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
diff --git a/embassy-net-driver-channel/src/lib.rs b/embassy-net-driver-channel/src/lib.rs
index 0c8dcc22b..02a4c00d6 100644
--- a/embassy-net-driver-channel/src/lib.rs
+++ b/embassy-net-driver-channel/src/lib.rs
@@ -1,4 +1,5 @@
#![no_std]
+#![doc = include_str!("../README.md")]
// must go first!
mod fmt;
diff --git a/embassy-net-driver/Cargo.toml b/embassy-net-driver/Cargo.toml
index ff6f29355..da6d9ad62 100644
--- a/embassy-net-driver/Cargo.toml
+++ b/embassy-net-driver/Cargo.toml
@@ -3,7 +3,13 @@ name = "embassy-net-driver"
version = "0.1.0"
edition = "2021"
license = "MIT OR Apache-2.0"
-
+description = "Driver trait for the `embassy-net` async TCP/IP network stack."
+repository = "https://github.com/embassy-rs/embassy"
+categories = [
+ "embedded",
+ "no-std",
+ "asynchronous",
+]
[package.metadata.embassy_docs]
src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-driver-v$VERSION/embassy-net-driver/src/"
@@ -11,5 +17,8 @@ src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-d
features = ["defmt"]
target = "thumbv7em-none-eabi"
+[package.metadata.docs.rs]
+features = ["defmt"]
+
[dependencies]
defmt = { version = "0.3", optional = true }
\ No newline at end of file
diff --git a/embassy-net-driver/README.md b/embassy-net-driver/README.md
index 84f25492d..6a757380d 100644
--- a/embassy-net-driver/README.md
+++ b/embassy-net-driver/README.md
@@ -1,5 +1,21 @@
# embassy-net-driver
+This crate contains the driver trait necessary for adding [`embassy-net`](https://crates.io/crates/embassy-net) support
+for a new hardware platform.
+
+If you want to *use* `embassy-net` with already made drivers, you should depend on the main `embassy-net` crate, not on this crate.
+
+If you are writing a driver, you should depend only on this crate, not on the main `embassy-net` crate.
+This will allow your driver to continue working for newer `embassy-net` major versions, without needing an update,
+if the driver trait has not had breaking changes.
+
+See also [`embassy-net-driver-channel`](https://crates.io/crates/embassy-net-driver-channel), which provides a higer-level API
+to construct a driver that processes packets in its own background task and communicates with the `embassy-net` task via
+packet queues for RX and TX.
+
+## Interoperability
+
+This crate can run on any executor.
## License
diff --git a/embassy-net-w5500/src/lib.rs b/embassy-net-w5500/src/lib.rs
index 6821373e3..efd9bed66 100644
--- a/embassy-net-w5500/src/lib.rs
+++ b/embassy-net-w5500/src/lib.rs
@@ -1,5 +1,6 @@
+//! [`embassy-net`](https://crates.io/crates/embassy-net) driver for the WIZnet W5500 ethernet chip.
#![no_std]
-/// [`embassy-net`](crates.io/crates/embassy-net) driver for the WIZnet W5500 ethernet chip.
+
mod device;
mod socket;
mod spi;
@@ -77,7 +78,7 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
}
}
-/// Obtain a driver for using the W5500 with [`embassy-net`](crates.io/crates/embassy-net).
+/// Obtain a driver for using the W5500 with [`embassy-net`](https://crates.io/crates/embassy-net).
pub async fn new<'a, const N_RX: usize, const N_TX: usize, SPI: SpiDevice, INT: Wait, RST: OutputPin>(
mac_addr: [u8; 6],
state: &'a mut State,
diff --git a/embassy-net/Cargo.toml b/embassy-net/Cargo.toml
index cef8247eb..e89039daa 100644
--- a/embassy-net/Cargo.toml
+++ b/embassy-net/Cargo.toml
@@ -3,7 +3,13 @@ name = "embassy-net"
version = "0.1.0"
edition = "2021"
license = "MIT OR Apache-2.0"
-
+description = "Async TCP/IP network stack for embedded systems"
+repository = "https://github.com/embassy-rs/embassy"
+categories = [
+ "embedded",
+ "no-std",
+ "asynchronous",
+]
[package.metadata.embassy_docs]
src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-v$VERSION/embassy-net/src/"
@@ -44,7 +50,6 @@ smoltcp = { version = "0.10.0", default-features = false, features = [
] }
embassy-net-driver = { version = "0.1.0", path = "../embassy-net-driver" }
-embassy-hal-common = { version = "0.1.0", path = "../embassy-hal-common" }
embassy-time = { version = "0.1.0", path = "../embassy-time" }
embassy-sync = { version = "0.2.0", path = "../embassy-sync" }
embedded-io = { version = "0.4.0", optional = true }
diff --git a/embassy-net/README.md b/embassy-net/README.md
index 470926c58..48f9fd832 100644
--- a/embassy-net/README.md
+++ b/embassy-net/README.md
@@ -1,30 +1,56 @@
# embassy-net
-embassy-net contains an async network API based on smoltcp and embassy, designed
-for embedded systems.
+`embassy-net` is a no-std no-alloc async network stack, designed for embedded systems.
-## Running the example
+It builds on [`smoltcp`](https://github.com/smoltcp-rs/smoltcp). It provides a higher-level and more opinionated
+API. It glues together the components provided by `smoltcp`, handling the low-level details with defaults and
+memory management designed to work well for embedded systems, aiiming for a more "Just Works" experience.
-First, create the tap0 interface. You only need to do this once.
+## Features
-```sh
-sudo ip tuntap add name tap0 mode tap user $USER
-sudo ip link set tap0 up
-sudo ip addr add 192.168.69.100/24 dev tap0
-sudo ip -6 addr add fe80::100/64 dev tap0
-sudo ip -6 addr add fdaa::100/64 dev tap0
-sudo ip -6 route add fe80::/64 dev tap0
-sudo ip -6 route add fdaa::/64 dev tap0
-```
+- IPv4, IPv6
+- Ethernet and bare-IP mediums.
+- TCP, UDP, DNS, DHCPv4, IGMPv4
+- TCP sockets implement the `embedded-io` async traits.
-Second, have something listening there. For example `nc -l 8000`
+See the [`smoltcp`](https://github.com/smoltcp-rs/smoltcp) README for a detailed list of implemented and
+unimplemented features of the network protocols.
-Then run the example located in the `examples` folder:
+## Hardware support
-```sh
-cd $EMBASSY_ROOT/examples/std/
-cargo run --bin net -- --static-ip
-```
+- [`esp-wifi`](https://github.com/esp-rs/esp-wifi) for WiFi support on bare-metal ESP32 chips. Maintained by Espressif.
+- [`cyw43`](https://github.com/embassy-rs/embassy/tree/main/cyw43) for WiFi on CYW43xx chips, used in the Raspberry Pi Pico W
+- [`embassy-usb`](https://github.com/embassy-rs/embassy/tree/main/embassy-usb) for Ethernet-over-USB (CDC NCM) support.
+- [`embassy-stm32`](https://github.com/embassy-rs/embassy/tree/main/embassy-stm32) for the builtin Ethernet MAC in all STM32 chips (STM32F1, STM32F2, STM32F4, STM32F7, STM32H7, STM32H5).
+- [`embassy-net-w5500`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-w5500) for Wiznet W5500 SPI Ethernet MAC+PHY chip.
+- [`embassy-net-esp-hosted`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-esp-hosted) for using ESP32 chips with the [`esp-hosted`](https://github.com/espressif/esp-hosted) firmware as WiFi adapters for another non-ESP32 MCU.
+
+## Examples
+
+- For usage with Embassy HALs and network chip drivers, search [here](https://github.com/embassy-rs/embassy/tree/main/examples) for `eth` or `wifi`.
+- The [`esp-wifi` repo](https://github.com/esp-rs/esp-wifi) has examples for use on bare-metal ESP32 chips.
+- For usage on `std` platforms, see [the `std` examples](https://github.com/embassy-rs/embassy/tree/main/examples/std/src/bin)
+
+## Adding support for new hardware
+
+To add `embassy-net` support for new hardware (i.e. a new Ethernet or WiFi chip, or
+an Ethernet/WiFi MCU peripheral), you have to implement the [`embassy-net-driver`](https://crates.io/crates/embassy-net-driver)
+traits.
+
+Alternatively, [`embassy-net-driver-channel`](https://crates.io/crates/embassy-net-driver-channel) provides a higer-level API
+to construct a driver that processes packets in its own background task and communicates with the `embassy-net` task via
+packet queues for RX and TX.
+
+Drivers should depend only on `embassy-net-driver` or `embassy-net-driver-channel`. Never on the main `embassy-net` crate.
+This allows existing drivers to continue working for newer `embassy-net` major versions, without needing an update, if the driver
+trait has not had breaking changes.
+
+## Interoperability
+
+This crate can run on any executor.
+
+[`embassy-time`](https://crates.io/crates/embassy-net-driver) is used for timekeeping and timeouts. You must
+link an `embassy-time` driver in your project to use this crate.
## License
diff --git a/embassy-net/src/lib.rs b/embassy-net/src/lib.rs
index 17a7a22a2..840d7a09a 100644
--- a/embassy-net/src/lib.rs
+++ b/embassy-net/src/lib.rs
@@ -419,7 +419,29 @@ impl Stack {
})
.await?;
- use embassy_hal_common::drop::OnDrop;
+ #[must_use = "to delay the drop handler invocation to the end of the scope"]
+ struct OnDrop {
+ f: core::mem::MaybeUninit,
+ }
+
+ impl OnDrop {
+ fn new(f: F) -> Self {
+ Self {
+ f: core::mem::MaybeUninit::new(f),
+ }
+ }
+
+ fn defuse(self) {
+ core::mem::forget(self)
+ }
+ }
+
+ impl Drop for OnDrop {
+ fn drop(&mut self) {
+ unsafe { self.f.as_ptr().read()() }
+ }
+ }
+
let drop = OnDrop::new(|| {
self.with_mut(|s, i| {
let socket = s.sockets.get_mut::(i.dns_socket);
diff --git a/embassy-usb/src/class/cdc_ncm/embassy_net.rs b/embassy-usb/src/class/cdc_ncm/embassy_net.rs
index bc79b3671..670709021 100644
--- a/embassy-usb/src/class/cdc_ncm/embassy_net.rs
+++ b/embassy-usb/src/class/cdc_ncm/embassy_net.rs
@@ -1,4 +1,5 @@
-//! [`embassy-net`](crates.io/crates/embassy-net) driver for the CDC-NCM class.
+//! [`embassy-net`](https://crates.io/crates/embassy-net) driver for the CDC-NCM class.
+
use embassy_futures::select::{select, Either};
use embassy_net_driver_channel as ch;
use embassy_net_driver_channel::driver::LinkState;
@@ -79,7 +80,7 @@ impl<'d, D: Driver<'d>, const MTU: usize> Runner<'d, D, MTU> {
pub type Device<'d, const MTU: usize> = embassy_net_driver_channel::Device<'d, MTU>;
impl<'d, D: Driver<'d>> CdcNcmClass<'d, D> {
- /// Obtain a driver for using the CDC-NCM class with [`embassy-net`](crates.io/crates/embassy-net).
+ /// Obtain a driver for using the CDC-NCM class with [`embassy-net`](https://crates.io/crates/embassy-net).
pub fn into_embassy_net_device(
self,
state: &'d mut State,
diff --git a/examples/std/README.md b/examples/std/README.md
new file mode 100644
index 000000000..adc795928
--- /dev/null
+++ b/examples/std/README.md
@@ -0,0 +1,23 @@
+
+## Running the `embassy-net` examples
+
+First, create the tap0 interface. You only need to do this once.
+
+```sh
+sudo ip tuntap add name tap0 mode tap user $USER
+sudo ip link set tap0 up
+sudo ip addr add 192.168.69.100/24 dev tap0
+sudo ip -6 addr add fe80::100/64 dev tap0
+sudo ip -6 addr add fdaa::100/64 dev tap0
+sudo ip -6 route add fe80::/64 dev tap0
+sudo ip -6 route add fdaa::/64 dev tap0
+```
+
+Second, have something listening there. For example `nc -l 8000`
+
+Then run the example located in the `examples` folder:
+
+```sh
+cd $EMBASSY_ROOT/examples/std/
+cargo run --bin net -- --static-ip
+```
\ No newline at end of file