rp/uart: report errors from buffered uart
this reports errors at the same location the blocking uart would, which works out to being mostly exact (except in the case of overruns, where one extra character is dropped). this is actually easier than going nuclear in the case of errors and nuking both the buffer contents and the rx fifo, both of which are things we'd have to do in addition to what's added here, and neither are needed for correctness.
This commit is contained in:
pennae
parent
7ab9fe0522
commit
861f49cfd4
2 changed files with 301 additions and 34 deletions
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@ -2,6 +2,7 @@ use core::future::{poll_fn, Future};
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use core::slice;
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use core::task::Poll;
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use atomic_polyfill::{AtomicU8, Ordering};
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use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
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use embassy_hal_common::atomic_ring_buffer::RingBuffer;
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use embassy_sync::waitqueue::AtomicWaker;
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@ -16,8 +17,15 @@ pub struct State {
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tx_buf: RingBuffer,
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rx_waker: AtomicWaker,
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rx_buf: RingBuffer,
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rx_error: AtomicU8,
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}
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// these must match bits 8..11 in UARTDR
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const RXE_OVERRUN: u8 = 8;
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const RXE_BREAK: u8 = 4;
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const RXE_PARITY: u8 = 2;
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const RXE_FRAMING: u8 = 1;
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impl State {
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pub const fn new() -> Self {
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Self {
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@ -25,6 +33,7 @@ impl State {
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tx_buf: RingBuffer::new(),
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rx_waker: AtomicWaker::new(),
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tx_waker: AtomicWaker::new(),
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rx_error: AtomicU8::new(0),
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}
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}
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}
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@ -196,7 +205,25 @@ impl<'d, T: Instance> BufferedUartRx<'d, T> {
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})
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}
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fn try_read(buf: &mut [u8]) -> Poll<Result<usize, Error>> {
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fn get_rx_error() -> Option<Error> {
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let errs = T::buffered_state().rx_error.swap(0, Ordering::Relaxed);
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if errs & RXE_OVERRUN != 0 {
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Some(Error::Overrun)
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} else if errs & RXE_BREAK != 0 {
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Some(Error::Break)
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} else if errs & RXE_PARITY != 0 {
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Some(Error::Parity)
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} else if errs & RXE_FRAMING != 0 {
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Some(Error::Framing)
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} else {
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None
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}
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}
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fn try_read(buf: &mut [u8]) -> Poll<Result<usize, Error>>
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where
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T: 'd,
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{
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if buf.is_empty() {
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return Poll::Ready(Ok(0));
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}
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@ -210,13 +237,16 @@ impl<'d, T: Instance> BufferedUartRx<'d, T> {
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});
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let result = if n == 0 {
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return Poll::Pending;
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match Self::get_rx_error() {
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None => return Poll::Pending,
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Some(e) => Err(e),
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}
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} else {
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Ok(n)
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};
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// (Re-)Enable the interrupt to receive more data in case it was
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// disabled because the buffer was full.
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// disabled because the buffer was full or errors were detected.
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let regs = T::regs();
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unsafe {
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regs.uartimsc().write_set(|w| {
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@ -237,18 +267,28 @@ impl<'d, T: Instance> BufferedUartRx<'d, T> {
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}
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}
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fn fill_buf<'a>() -> impl Future<Output = Result<&'a [u8], Error>> {
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fn fill_buf<'a>() -> impl Future<Output = Result<&'a [u8], Error>>
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where
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T: 'd,
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{
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poll_fn(move |cx| {
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let state = T::buffered_state();
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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let (p, n) = rx_reader.pop_buf();
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if n == 0 {
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state.rx_waker.register(cx.waker());
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return Poll::Pending;
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}
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let result = if n == 0 {
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match Self::get_rx_error() {
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None => {
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state.rx_waker.register(cx.waker());
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return Poll::Pending;
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}
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Some(e) => Err(e),
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}
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} else {
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let buf = unsafe { slice::from_raw_parts(p, n) };
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Ok(buf)
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};
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let buf = unsafe { slice::from_raw_parts(p, n) };
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Poll::Ready(Ok(buf))
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Poll::Ready(result)
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})
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}
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@ -258,7 +298,7 @@ impl<'d, T: Instance> BufferedUartRx<'d, T> {
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rx_reader.pop_done(amt);
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// (Re-)Enable the interrupt to receive more data in case it was
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// disabled because the buffer was full.
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// disabled because the buffer was full or errors were detected.
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let regs = T::regs();
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unsafe {
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regs.uartimsc().write_set(|w| {
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@ -478,19 +518,37 @@ pub(crate) unsafe fn on_interrupt<T: Instance>(_: *mut ()) {
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let mut rx_writer = s.rx_buf.writer();
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let rx_buf = rx_writer.push_slice();
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let mut n_read = 0;
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let mut error = false;
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for rx_byte in rx_buf {
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if r.uartfr().read().rxfe() {
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break;
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}
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*rx_byte = r.uartdr().read().data();
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let dr = r.uartdr().read();
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if (dr.0 >> 8) != 0 {
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s.rx_error.fetch_or((dr.0 >> 8) as u8, Ordering::Relaxed);
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error = true;
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// only fill the buffer with valid characters. the current character is fine
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// if the error is an overrun, but if we add it to the buffer we'll report
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// the overrun one character too late. drop it instead and pretend we were
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// a bit slower at draining the rx fifo than we actually were.
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// this is consistent with blocking uart error reporting.
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break;
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}
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*rx_byte = dr.data();
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n_read += 1;
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}
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if n_read > 0 {
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rx_writer.push_done(n_read);
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s.rx_waker.wake();
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} else if error {
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s.rx_waker.wake();
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}
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// Disable any further RX interrupts when the buffer becomes full.
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if s.rx_buf.is_full() {
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// Disable any further RX interrupts when the buffer becomes full or
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// errors have occured. this lets us buffer additional errors in the
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// fifo without needing more error storage locations, and most applications
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// will want to do a full reset of their uart state anyway once an error
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// has happened.
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if s.rx_buf.is_full() || error {
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r.uartimsc().write_clear(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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@ -2,39 +2,248 @@
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#![no_main]
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#![feature(type_alias_impl_trait)]
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use defmt::{assert_eq, *};
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use defmt::{assert_eq, panic, *};
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use embassy_executor::Spawner;
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use embassy_rp::gpio::{Level, Output};
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use embassy_rp::interrupt;
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use embassy_rp::uart::{BufferedUart, Config};
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use embedded_io::asynch::{Read, Write};
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use embassy_rp::uart::{BufferedUart, BufferedUartRx, Config, Error, Instance, Parity};
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use embassy_time::{Duration, Timer};
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use embedded_io::asynch::{Read, ReadExactError, Write};
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use {defmt_rtt as _, panic_probe as _};
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async fn read<const N: usize>(uart: &mut BufferedUart<'_, impl Instance>) -> Result<[u8; N], Error> {
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let mut buf = [255; N];
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match uart.read_exact(&mut buf).await {
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Ok(()) => Ok(buf),
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// we should not ever produce an Eof condition
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Err(ReadExactError::UnexpectedEof) => panic!(),
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Err(ReadExactError::Other(e)) => Err(e),
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}
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}
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async fn read1<const N: usize>(uart: &mut BufferedUartRx<'_, impl Instance>) -> Result<[u8; N], Error> {
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let mut buf = [255; N];
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match uart.read_exact(&mut buf).await {
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Ok(()) => Ok(buf),
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// we should not ever produce an Eof condition
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Err(ReadExactError::UnexpectedEof) => panic!(),
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Err(ReadExactError::Other(e)) => Err(e),
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}
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}
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async fn send(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, parity: Option<bool>) {
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pin.set_low();
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Timer::after(Duration::from_millis(1)).await;
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for i in 0..8 {
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if v & (1 << i) == 0 {
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pin.set_low();
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} else {
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pin.set_high();
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}
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Timer::after(Duration::from_millis(1)).await;
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}
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if let Some(b) = parity {
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if b {
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pin.set_high();
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} else {
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pin.set_low();
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}
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Timer::after(Duration::from_millis(1)).await;
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}
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pin.set_high();
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Timer::after(Duration::from_millis(1)).await;
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}
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let p = embassy_rp::init(Default::default());
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info!("Hello World!");
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let (tx, rx, uart) = (p.PIN_0, p.PIN_1, p.UART0);
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let (mut tx, mut rx, mut uart) = (p.PIN_0, p.PIN_1, p.UART0);
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let mut irq = interrupt::take!(UART0_IRQ);
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let config = Config::default();
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let irq = interrupt::take!(UART0_IRQ);
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let tx_buf = &mut [0u8; 16];
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let rx_buf = &mut [0u8; 16];
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let mut uart = BufferedUart::new(uart, irq, tx, rx, tx_buf, rx_buf, config);
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{
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let config = Config::default();
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let tx_buf = &mut [0u8; 16];
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let rx_buf = &mut [0u8; 16];
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let mut uart = BufferedUart::new(&mut uart, &mut irq, &mut tx, &mut rx, tx_buf, rx_buf, config);
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// Make sure we send more bytes than fits in the FIFO, to test the actual
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// bufferedUart.
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// Make sure we send more bytes than fits in the FIFO, to test the actual
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// bufferedUart.
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let data = [
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
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31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
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];
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uart.write_all(&data).await.unwrap();
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info!("Done writing");
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let data = [
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
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30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
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];
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uart.write_all(&data).await.unwrap();
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info!("Done writing");
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let mut buf = [0; 48];
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uart.read_exact(&mut buf).await.unwrap();
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assert_eq!(buf, data);
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assert_eq!(read(&mut uart).await.unwrap(), data);
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}
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info!("test overflow detection");
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{
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let config = Config::default();
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let tx_buf = &mut [0u8; 16];
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let rx_buf = &mut [0u8; 16];
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let mut uart = BufferedUart::new(&mut uart, &mut irq, &mut tx, &mut rx, tx_buf, rx_buf, config);
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// Make sure we send more bytes than fits in the FIFO, to test the actual
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// bufferedUart.
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let data = [
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
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30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
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];
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let overflow = [
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101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116,
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];
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// give each block time to settle into the fifo. we want the overrun to occur at a well-defined point.
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uart.write_all(&data).await.unwrap();
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uart.blocking_flush().unwrap();
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while uart.busy() {}
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uart.write_all(&overflow).await.unwrap();
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uart.blocking_flush().unwrap();
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while uart.busy() {}
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// already buffered/fifod prefix is valid
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assert_eq!(read(&mut uart).await.unwrap(), data);
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// next received character causes overrun error and is discarded
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uart.write_all(&[1, 2, 3]).await.unwrap();
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uart.blocking_flush().unwrap();
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assert_eq!(read::<1>(&mut uart).await.unwrap_err(), Error::Overrun);
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assert_eq!(read(&mut uart).await.unwrap(), [2, 3]);
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}
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info!("test break detection");
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{
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let mut config = Config::default();
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config.baudrate = 1000;
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let tx_buf = &mut [0u8; 16];
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let rx_buf = &mut [0u8; 16];
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let mut uart = BufferedUart::new(&mut uart, &mut irq, &mut tx, &mut rx, tx_buf, rx_buf, config);
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// break on empty buffer
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uart.send_break(20).await;
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assert_eq!(read::<1>(&mut uart).await.unwrap_err(), Error::Break);
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uart.write_all(&[64]).await.unwrap();
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assert_eq!(read(&mut uart).await.unwrap(), [64]);
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// break on partially filled buffer
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uart.write_all(&[65; 2]).await.unwrap();
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uart.send_break(20).await;
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uart.write_all(&[66]).await.unwrap();
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assert_eq!(read(&mut uart).await.unwrap(), [65; 2]);
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assert_eq!(read::<1>(&mut uart).await.unwrap_err(), Error::Break);
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assert_eq!(read(&mut uart).await.unwrap(), [66]);
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// break on full buffer
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uart.write_all(&[64; 16]).await.unwrap();
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uart.send_break(20).await;
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uart.write_all(&[65]).await.unwrap();
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assert_eq!(read(&mut uart).await.unwrap(), [64; 16]);
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assert_eq!(read::<1>(&mut uart).await.unwrap_err(), Error::Break);
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assert_eq!(read(&mut uart).await.unwrap(), [65]);
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}
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// parity detection. here we bitbang to not require two uarts.
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info!("test parity error detection");
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{
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let mut pin = Output::new(&mut tx, Level::High);
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// choose a very slow baud rate to make tests reliable even with O0
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let mut config = Config::default();
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config.baudrate = 1000;
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config.parity = Parity::ParityEven;
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let rx_buf = &mut [0u8; 16];
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let mut uart = BufferedUartRx::new(&mut uart, &mut irq, &mut rx, rx_buf, config);
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async fn chr(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, parity: u32) {
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send(pin, v, Some(parity != 0)).await;
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}
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// first check that we can send correctly
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chr(&mut pin, 64, 1).await;
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assert_eq!(read1(&mut uart).await.unwrap(), [64]);
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// parity on empty buffer
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chr(&mut pin, 64, 0).await;
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chr(&mut pin, 4, 1).await;
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assert_eq!(read1::<1>(&mut uart).await.unwrap_err(), Error::Parity);
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assert_eq!(read1(&mut uart).await.unwrap(), [4]);
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// parity on partially filled buffer
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chr(&mut pin, 64, 1).await;
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chr(&mut pin, 32, 1).await;
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chr(&mut pin, 64, 0).await;
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chr(&mut pin, 65, 0).await;
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assert_eq!(read1(&mut uart).await.unwrap(), [64, 32]);
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assert_eq!(read1::<1>(&mut uart).await.unwrap_err(), Error::Parity);
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assert_eq!(read1(&mut uart).await.unwrap(), [65]);
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// parity on full buffer
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for i in 0..16 {
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chr(&mut pin, i, i.count_ones() % 2).await;
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}
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chr(&mut pin, 64, 0).await;
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chr(&mut pin, 65, 0).await;
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assert_eq!(
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read1(&mut uart).await.unwrap(),
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[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
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);
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assert_eq!(read1::<1>(&mut uart).await.unwrap_err(), Error::Parity);
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assert_eq!(read1(&mut uart).await.unwrap(), [65]);
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}
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// framing error detection. here we bitbang because there's no other way.
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info!("test framing error detection");
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{
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let mut pin = Output::new(&mut tx, Level::High);
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// choose a very slow baud rate to make tests reliable even with O0
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let mut config = Config::default();
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config.baudrate = 1000;
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let rx_buf = &mut [0u8; 16];
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let mut uart = BufferedUartRx::new(&mut uart, &mut irq, &mut rx, rx_buf, config);
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async fn chr(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, good: bool) {
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if good {
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send(pin, v, None).await;
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} else {
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send(pin, v, Some(false)).await;
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}
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}
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// first check that we can send correctly
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chr(&mut pin, 64, true).await;
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assert_eq!(read1(&mut uart).await.unwrap(), [64]);
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// framing on empty buffer
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chr(&mut pin, 64, false).await;
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assert_eq!(read1::<1>(&mut uart).await.unwrap_err(), Error::Framing);
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chr(&mut pin, 65, true).await;
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assert_eq!(read1(&mut uart).await.unwrap(), [65]);
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|
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// framing on partially filled buffer
|
||||
chr(&mut pin, 64, true).await;
|
||||
chr(&mut pin, 32, true).await;
|
||||
chr(&mut pin, 64, false).await;
|
||||
chr(&mut pin, 65, true).await;
|
||||
assert_eq!(read1(&mut uart).await.unwrap(), [64, 32]);
|
||||
assert_eq!(read1::<1>(&mut uart).await.unwrap_err(), Error::Framing);
|
||||
assert_eq!(read1(&mut uart).await.unwrap(), [65]);
|
||||
|
||||
// framing on full buffer
|
||||
for i in 0..16 {
|
||||
chr(&mut pin, i, true).await;
|
||||
}
|
||||
chr(&mut pin, 64, false).await;
|
||||
chr(&mut pin, 65, true).await;
|
||||
assert_eq!(
|
||||
read1(&mut uart).await.unwrap(),
|
||||
[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
|
||||
);
|
||||
assert_eq!(read1::<1>(&mut uart).await.unwrap_err(), Error::Framing);
|
||||
assert_eq!(read1(&mut uart).await.unwrap(), [65]);
|
||||
}
|
||||
|
||||
info!("Test OK");
|
||||
cortex_m::asm::bkpt();
|
||||
|
|
|
|||
Loading…
Reference in a new issue