From 88052480b14b8dd38e7c4ba179b7035390f59618 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Mon, 19 Jun 2023 13:50:17 +0200
Subject: [PATCH] fix typo, minor cleanup

---
 embassy-stm32/src/dac/mod.rs  | 13 +++++++------
 embassy-stm32/src/dma/bdma.rs |  7 +++----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 0fbf67673..704b77b37 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -275,42 +275,43 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
         });
 
         let tx_request = self.txdma.request();
+        let channel = &mut self.txdma;
 
         // Initiate the correct type of DMA transfer depending on what data is passed
         let tx_f = match data_ch1 {
             ValueArray::Bit8(buf) => unsafe {
                 Transfer::new_write(
-                    &mut self.txdma,
+                    channel,
                     tx_request,
                     buf,
                     T::regs().dhr8r(CHANNEL).as_ptr() as *mut u8,
                     TransferOptions {
                         circular,
-                        halt_transfer_ir: false,
+                        half_transfer_ir: false,
                     },
                 )
             },
             ValueArray::Bit12Left(buf) => unsafe {
                 Transfer::new_write(
-                    &mut self.txdma,
+                    channel,
                     tx_request,
                     buf,
                     T::regs().dhr12l(CHANNEL).as_ptr() as *mut u16,
                     TransferOptions {
                         circular,
-                        halt_transfer_ir: false,
+                        half_transfer_ir: false,
                     },
                 )
             },
             ValueArray::Bit12Right(buf) => unsafe {
                 Transfer::new_write(
-                    &mut self.txdma,
+                    channel,
                     tx_request,
                     buf,
                     T::regs().dhr12r(CHANNEL).as_ptr() as *mut u16,
                     TransferOptions {
                         circular,
-                        halt_transfer_ir: false,
+                        half_transfer_ir: false,
                     },
                 )
             },
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index 3d315e20b..0ad20579a 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -1,7 +1,6 @@
 #![macro_use]
 
 use core::future::Future;
-use core::option;
 use core::pin::Pin;
 use core::sync::atomic::{fence, Ordering};
 use core::task::{Context, Poll, Waker};
@@ -24,14 +23,14 @@ use crate::pac::bdma::{regs, vals};
 #[non_exhaustive]
 pub struct TransferOptions {
     pub circular: bool,
-    pub halt_transfer_ir: bool,
+    pub half_transfer_ir: bool,
 }
 
 impl Default for TransferOptions {
     fn default() -> Self {
         Self {
             circular: false,
-            halt_transfer_ir: false,
+            half_transfer_ir: false,
         }
     }
 }
@@ -291,7 +290,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
             w.set_dir(dir.into());
             w.set_teie(true);
             w.set_tcie(true);
-            w.set_htie(options.halt_transfer_ir);
+            w.set_htie(options.half_transfer_ir);
             if options.circular {
                 w.set_circ(vals::Circ::ENABLED);
                 debug!("Setting circular mode");