Merge #663
663: stm32: Spi bugfixes r=Dirbaio a=GrantM11235 Co-authored-by: Grant Miller <GrantM11235@gmail.com>
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commit
8ef8ab1707
1 changed files with 18 additions and 9 deletions
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@ -7,7 +7,7 @@ use embassy_hal_common::unborrow;
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use futures::future::join;
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use self::sealed::WordSize;
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use crate::dma::{slice_ptr_parts, slice_ptr_parts_mut, NoDma, Transfer};
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use crate::dma::{NoDma, Transfer};
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use crate::gpio::sealed::{AFType, Pin as _};
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use crate::gpio::AnyPin;
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use crate::pac::spi::Spi as Regs;
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@ -411,6 +411,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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where
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Tx: TxDma<T>,
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{
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if data.len() == 0 {
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return Ok(());
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}
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self.set_word_size(W::WORDSIZE);
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unsafe {
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T::REGS.cr1().modify(|w| {
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@ -418,10 +422,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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});
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}
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// TODO: This is unnecessary in some versions because
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// clearing SPE automatically clears the fifos
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flush_rx_fifo(T::REGS);
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let tx_request = self.txdma.request();
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let tx_dst = T::REGS.tx_ptr();
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unsafe { self.txdma.start_write(tx_request, data, tx_dst) }
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@ -440,6 +440,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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tx_f.await;
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// flush here otherwise `finish_dma` hangs waiting for the rx fifo to empty
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flush_rx_fifo(T::REGS);
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finish_dma(T::REGS);
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Ok(())
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@ -450,6 +453,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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Tx: TxDma<T>,
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Rx: RxDma<T>,
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{
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if data.len() == 0 {
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return Ok(());
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}
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self.set_word_size(W::WORDSIZE);
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unsafe {
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T::REGS.cr1().modify(|w| {
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@ -458,7 +465,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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set_rxdmaen(T::REGS, true);
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}
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let (_, clock_byte_count) = slice_ptr_parts_mut(data);
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let clock_byte_count = data.len();
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let rx_request = self.rxdma.request();
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let rx_src = T::REGS.rx_ptr();
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@ -499,9 +506,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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Tx: TxDma<T>,
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Rx: RxDma<T>,
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{
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let (_, rx_len) = slice_ptr_parts(read);
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let (_, tx_len) = slice_ptr_parts(write);
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assert_eq!(rx_len, tx_len);
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assert_eq!(read.len(), write.len());
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if read.len() == 0 {
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return Ok(());
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}
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self.set_word_size(W::WORDSIZE);
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unsafe {
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