stm32/eth_v1: update to new embassy-net trait, remove PeripheralMutex.
This commit is contained in:
Dario Nieuwenhuis
parent
e9219405ca
commit
8f30652109
6 changed files with 424 additions and 526 deletions
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@ -1,14 +1,131 @@
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#![macro_use]
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#![cfg_attr(not(feature = "embassy-net"), allow(unused))]
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#[cfg(feature = "net")]
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#[cfg_attr(any(eth_v1a, eth_v1b, eth_v1c), path = "v1/mod.rs")]
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#[cfg_attr(eth_v2, path = "v2/mod.rs")]
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mod _version;
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pub mod generic_smi;
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#[cfg(feature = "net")]
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pub use _version::*;
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use embassy_sync::waitqueue::AtomicWaker;
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#[allow(unused)]
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const MTU: usize = 1514;
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const TX_BUFFER_SIZE: usize = 1514;
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const RX_BUFFER_SIZE: usize = 1536;
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#[repr(C, align(8))]
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#[derive(Copy, Clone)]
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pub(crate) struct Packet<const N: usize>([u8; N]);
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pub struct PacketQueue<const TX: usize, const RX: usize> {
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tx_desc: [TDes; TX],
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rx_desc: [RDes; RX],
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tx_buf: [Packet<TX_BUFFER_SIZE>; TX],
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rx_buf: [Packet<RX_BUFFER_SIZE>; RX],
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}
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impl<const TX: usize, const RX: usize> PacketQueue<TX, RX> {
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pub const fn new() -> Self {
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const NEW_TDES: TDes = TDes::new();
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const NEW_RDES: RDes = RDes::new();
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Self {
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tx_desc: [NEW_TDES; TX],
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rx_desc: [NEW_RDES; RX],
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tx_buf: [Packet([0; TX_BUFFER_SIZE]); TX],
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rx_buf: [Packet([0; RX_BUFFER_SIZE]); RX],
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}
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}
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}
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static WAKER: AtomicWaker = AtomicWaker::new();
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#[cfg(feature = "embassy-net")]
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mod embassy_net_impl {
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use core::task::Context;
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use embassy_net::device::{Device, DeviceCapabilities, LinkState};
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use super::*;
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impl<'d, T: Instance, P: PHY> Device for Ethernet<'d, T, P> {
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type RxToken<'a> = RxToken<'a, 'd> where Self: 'a;
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type TxToken<'a> = TxToken<'a, 'd> where Self: 'a;
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fn receive(&mut self, cx: &mut Context) -> Option<(Self::RxToken<'_>, Self::TxToken<'_>)> {
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WAKER.register(cx.waker());
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if self.rx.available().is_some() && self.tx.available().is_some() {
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Some((RxToken { rx: &mut self.rx }, TxToken { tx: &mut self.tx }))
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} else {
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None
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}
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}
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fn transmit(&mut self, cx: &mut Context) -> Option<Self::TxToken<'_>> {
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WAKER.register(cx.waker());
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if self.tx.available().is_some() {
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Some(TxToken { tx: &mut self.tx })
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} else {
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None
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}
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}
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fn capabilities(&self) -> DeviceCapabilities {
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let mut caps = DeviceCapabilities::default();
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caps.max_transmission_unit = MTU;
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caps.max_burst_size = Some(self.tx.len());
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caps
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}
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fn link_state(&mut self, cx: &mut Context) -> LinkState {
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// TODO: wake cx.waker on link state change
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cx.waker().wake_by_ref();
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if P::poll_link(self) {
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LinkState::Up
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} else {
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LinkState::Down
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}
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}
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fn ethernet_address(&self) -> [u8; 6] {
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self.mac_addr
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}
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}
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pub struct RxToken<'a, 'd> {
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rx: &'a mut RDesRing<'d>,
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}
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impl<'a, 'd> embassy_net::device::RxToken for RxToken<'a, 'd> {
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fn consume<R, F>(self, f: F) -> R
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where
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F: FnOnce(&mut [u8]) -> R,
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{
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// NOTE(unwrap): we checked the queue wasn't full when creating the token.
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let pkt = unwrap!(self.rx.available());
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let r = f(pkt);
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self.rx.pop_packet();
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r
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}
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}
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pub struct TxToken<'a, 'd> {
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tx: &'a mut TDesRing<'d>,
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}
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impl<'a, 'd> embassy_net::device::TxToken for TxToken<'a, 'd> {
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fn consume<R, F>(self, len: usize, f: F) -> R
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where
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F: FnOnce(&mut [u8]) -> R,
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{
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// NOTE(unwrap): we checked the queue wasn't full when creating the token.
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let pkt = unwrap!(self.tx.available());
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let r = f(&mut pkt[..len]);
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self.tx.transmit(len);
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r
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}
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}
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}
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/// Station Management Interface (SMI) on an ethernet PHY
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///
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/// # Safety
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@ -1,21 +0,0 @@
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use crate::eth::_version::rx_desc::RDesRing;
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use crate::eth::_version::tx_desc::TDesRing;
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pub struct DescriptorRing<const T: usize, const R: usize> {
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pub(crate) tx: TDesRing<T>,
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pub(crate) rx: RDesRing<R>,
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}
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impl<const T: usize, const R: usize> DescriptorRing<T, R> {
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pub const fn new() -> Self {
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Self {
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tx: TDesRing::new(),
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rx: RDesRing::new(),
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}
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}
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pub fn init(&mut self) {
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self.tx.init();
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self.rx.init();
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}
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}
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@ -1,14 +1,17 @@
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// The v1c ethernet driver was ported to embassy from the awesome stm32-eth project (https://github.com/stm32-rs/stm32-eth).
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use core::marker::PhantomData;
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mod rx_desc;
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mod tx_desc;
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use core::sync::atomic::{fence, Ordering};
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use core::task::Waker;
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use embassy_cortex_m::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
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use embassy_cortex_m::interrupt::InterruptExt;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use embassy_net::{Device, DeviceCapabilities, LinkState, PacketBuf, MTU};
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use embassy_sync::waitqueue::AtomicWaker;
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use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
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pub(crate) use self::rx_desc::{RDes, RDesRing};
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pub(crate) use self::tx_desc::{TDes, TDesRing};
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use super::*;
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use crate::gpio::sealed::{AFType, Pin as __GpioPin};
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use crate::gpio::{AnyPin, Speed};
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#[cfg(eth_v1a)]
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@ -18,29 +21,16 @@ use crate::pac::SYSCFG;
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use crate::pac::{ETH, RCC};
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use crate::Peripheral;
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mod descriptors;
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mod rx_desc;
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mod tx_desc;
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pub struct Ethernet<'d, T: Instance, P: PHY> {
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_peri: PeripheralRef<'d, T>,
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pub(crate) tx: TDesRing<'d>,
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pub(crate) rx: RDesRing<'d>,
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use descriptors::DescriptorRing;
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use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
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use super::*;
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pub struct State<'d, T: Instance, const TX: usize, const RX: usize>(StateStorage<Inner<'d, T, TX, RX>>);
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impl<'d, T: Instance, const TX: usize, const RX: usize> State<'d, T, TX, RX> {
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pub const fn new() -> Self {
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Self(StateStorage::new())
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}
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}
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pub struct Ethernet<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> {
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state: PeripheralMutex<'d, Inner<'d, T, TX, RX>>,
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pins: [PeripheralRef<'d, AnyPin>; 9],
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_phy: P,
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clock_range: Cr,
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phy_addr: u8,
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mac_addr: [u8; 6],
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pub(crate) mac_addr: [u8; 6],
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}
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#[cfg(eth_v1a)]
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@ -82,10 +72,10 @@ macro_rules! config_pins {
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};
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}
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impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T, P, TX, RX> {
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impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
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/// safety: the returned instance is not leak-safe
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pub unsafe fn new(
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state: &'d mut State<'d, T, TX, RX>,
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pub fn new<const TX: usize, const RX: usize>(
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queue: &'d mut PacketQueue<TX, RX>,
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peri: impl Peripheral<P = T> + 'd,
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interrupt: impl Peripheral<P = crate::interrupt::ETH> + 'd,
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ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
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@ -101,8 +91,9 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T,
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mac_addr: [u8; 6],
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phy_addr: u8,
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) -> Self {
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into_ref!(interrupt, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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into_ref!(peri, interrupt, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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unsafe {
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// Enable the necessary Clocks
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// NOTE(unsafe) We have exclusive access to the registers
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#[cfg(eth_v1a)]
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@ -142,9 +133,6 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T,
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#[cfg(any(eth_v1b, eth_v1c))]
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config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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// NOTE(unsafe) We are ourselves not leak-safe.
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let state = PeripheralMutex::new(interrupt, &mut state.0, || Inner::new(peri));
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// NOTE(unsafe) We have exclusive access to the registers
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let dma = ETH.ethernet_dma();
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let mac = ETH.ethernet_mac();
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@ -219,17 +207,16 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T,
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];
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let mut this = Self {
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state,
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_peri: peri,
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pins,
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_phy: phy,
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clock_range,
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phy_addr,
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mac_addr,
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tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
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rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
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};
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this.state.with(|s| {
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s.desc_ring.init();
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fence(Ordering::SeqCst);
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let mac = ETH.ethernet_mac();
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@ -245,23 +232,45 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T,
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w.set_sr(DmaomrSr::STARTED); // start receiving channel
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});
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this.rx.demand_poll();
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// Enable interrupts
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dma.dmaier().modify(|w| {
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w.set_nise(true);
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w.set_rie(true);
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w.set_tie(true);
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});
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});
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P::phy_reset(&mut this);
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P::phy_init(&mut this);
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interrupt.set_handler(Self::on_interrupt);
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interrupt.enable();
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this
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}
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}
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unsafe impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> StationManagement
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for Ethernet<'d, T, P, TX, RX>
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{
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fn on_interrupt(_cx: *mut ()) {
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WAKER.wake();
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// TODO: Check and clear more flags
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmasr().modify(|w| {
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w.set_ts(true);
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w.set_rs(true);
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w.set_nis(true);
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});
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// Delay two peripheral's clock
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dma.dmasr().read();
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dma.dmasr().read();
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}
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}
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}
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unsafe impl<'d, T: Instance, P: PHY> StationManagement for Ethernet<'d, T, P> {
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fn smi_read(&mut self, reg: u8) -> u16 {
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// NOTE(unsafe) These registers aren't used in the interrupt and we have `&mut self`
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unsafe {
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@ -297,44 +306,7 @@ unsafe impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> StationMa
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}
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}
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impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Device for Ethernet<'d, T, P, TX, RX> {
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fn is_transmit_ready(&mut self) -> bool {
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self.state.with(|s| s.desc_ring.tx.available())
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}
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fn transmit(&mut self, pkt: PacketBuf) {
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self.state.with(|s| unwrap!(s.desc_ring.tx.transmit(pkt)));
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}
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fn receive(&mut self) -> Option<PacketBuf> {
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self.state.with(|s| s.desc_ring.rx.pop_packet())
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}
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fn register_waker(&mut self, waker: &Waker) {
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WAKER.register(waker);
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}
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fn capabilities(&self) -> DeviceCapabilities {
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let mut caps = DeviceCapabilities::default();
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caps.max_transmission_unit = MTU;
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caps.max_burst_size = Some(TX.min(RX));
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caps
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}
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fn link_state(&mut self) -> LinkState {
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if P::poll_link(self) {
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LinkState::Up
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} else {
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LinkState::Down
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}
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}
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fn ethernet_address(&self) -> [u8; 6] {
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self.mac_addr
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}
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}
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impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Drop for Ethernet<'d, T, P, TX, RX> {
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impl<'d, T: Instance, P: PHY> Drop for Ethernet<'d, T, P> {
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fn drop(&mut self) {
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// NOTE(unsafe) We have `&mut self` and the interrupt doesn't use this registers
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unsafe {
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@ -361,46 +333,3 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Drop for Etherne
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})
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}
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}
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//----------------------------------------------------------------------
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struct Inner<'d, T: Instance, const TX: usize, const RX: usize> {
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_peri: PhantomData<&'d mut T>,
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desc_ring: DescriptorRing<TX, RX>,
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}
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impl<'d, T: Instance, const TX: usize, const RX: usize> Inner<'d, T, TX, RX> {
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pub fn new(_peri: impl Peripheral<P = T> + 'd) -> Self {
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Self {
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_peri: PhantomData,
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desc_ring: DescriptorRing::new(),
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}
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}
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}
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impl<'d, T: Instance, const TX: usize, const RX: usize> PeripheralState for Inner<'d, T, TX, RX> {
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type Interrupt = crate::interrupt::ETH;
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fn on_interrupt(&mut self) {
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unwrap!(self.desc_ring.tx.on_interrupt());
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self.desc_ring.rx.on_interrupt();
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WAKER.wake();
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// TODO: Check and clear more flags
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmasr().modify(|w| {
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w.set_ts(true);
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w.set_rs(true);
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w.set_nis(true);
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});
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// Delay two peripheral's clock
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dma.dmasr().read();
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dma.dmasr().read();
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}
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}
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}
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static WAKER: AtomicWaker = AtomicWaker::new();
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@ -1,9 +1,9 @@
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use core::sync::atomic::{compiler_fence, fence, Ordering};
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use embassy_net::{Packet, PacketBox, PacketBoxExt, PacketBuf};
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use stm32_metapac::eth::vals::{DmaomrSr, Rpd, Rps};
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use stm32_metapac::eth::vals::{Rpd, Rps};
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use vcell::VolatileCell;
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use crate::eth::RX_BUFFER_SIZE;
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use crate::pac::ETH;
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mod rx_consts {
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@ -28,6 +28,8 @@ mod rx_consts {
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use rx_consts::*;
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use super::Packet;
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/// Receive Descriptor representation
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///
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/// * rdes0: OWN and Status
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@ -35,7 +37,7 @@ use rx_consts::*;
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/// * rdes2: data buffer address
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/// * rdes3: next descriptor address
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#[repr(C)]
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struct RDes {
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pub(crate) struct RDes {
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rdes0: VolatileCell<u32>,
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rdes1: VolatileCell<u32>,
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rdes2: VolatileCell<u32>,
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||||
|
|
@ -54,7 +56,7 @@ impl RDes {
|
|||
|
||||
/// Return true if this RDes is acceptable to us
|
||||
#[inline(always)]
|
||||
pub fn valid(&self) -> bool {
|
||||
fn valid(&self) -> bool {
|
||||
// Write-back descriptor is valid if:
|
||||
//
|
||||
// Contains first buffer of packet AND contains last buf of
|
||||
|
|
@ -64,15 +66,16 @@ impl RDes {
|
|||
|
||||
/// Return true if this RDes is not currently owned by the DMA
|
||||
#[inline(always)]
|
||||
pub fn available(&self) -> bool {
|
||||
fn available(&self) -> bool {
|
||||
self.rdes0.get() & RXDESC_0_OWN == 0 // Owned by us
|
||||
}
|
||||
|
||||
/// Configures the reception buffer address and length and passed descriptor ownership to the DMA
|
||||
#[inline(always)]
|
||||
pub fn set_ready(&mut self, buf_addr: u32, buf_len: usize) {
|
||||
self.rdes1.set(self.rdes1.get() | (buf_len as u32) & RXDESC_1_RBS_MASK);
|
||||
self.rdes2.set(buf_addr);
|
||||
fn set_ready(&self, buf: *mut u8) {
|
||||
self.rdes1
|
||||
.set(self.rdes1.get() | (RX_BUFFER_SIZE as u32) & RXDESC_1_RBS_MASK);
|
||||
self.rdes2.set(buf as u32);
|
||||
|
||||
// "Preceding reads and writes cannot be moved past subsequent writes."
|
||||
fence(Ordering::Release);
|
||||
|
|
@ -88,12 +91,12 @@ impl RDes {
|
|||
|
||||
// points to next descriptor (RCH)
|
||||
#[inline(always)]
|
||||
fn set_buffer2(&mut self, buffer: *const u8) {
|
||||
fn set_buffer2(&self, buffer: *const u8) {
|
||||
self.rdes3.set(buffer as u32);
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn set_end_of_ring(&mut self) {
|
||||
fn set_end_of_ring(&self) {
|
||||
self.rdes1.set(self.rdes1.get() | RXDESC_1_RER);
|
||||
}
|
||||
|
||||
|
|
@ -102,7 +105,7 @@ impl RDes {
|
|||
((self.rdes0.get() >> RXDESC_0_FL_SHIFT) & RXDESC_0_FL_MASK) as usize
|
||||
}
|
||||
|
||||
pub fn setup(&mut self, next: Option<&Self>) {
|
||||
fn setup(&self, next: Option<&Self>, buf: *mut u8) {
|
||||
// Defer this initialization to this function, so we can have `RingEntry` on bss.
|
||||
self.rdes1.set(self.rdes1.get() | RXDESC_1_RCH);
|
||||
|
||||
|
|
@ -113,8 +116,11 @@ impl RDes {
|
|||
self.set_end_of_ring();
|
||||
}
|
||||
}
|
||||
|
||||
self.set_ready(buf);
|
||||
}
|
||||
}
|
||||
|
||||
/// Running state of the `RxRing`
|
||||
#[derive(PartialEq, Eq, Debug)]
|
||||
pub enum RunningState {
|
||||
|
|
@ -123,116 +129,42 @@ pub enum RunningState {
|
|||
Running,
|
||||
}
|
||||
|
||||
impl RunningState {
|
||||
/// whether self equals to `RunningState::Running`
|
||||
pub fn is_running(&self) -> bool {
|
||||
*self == RunningState::Running
|
||||
}
|
||||
}
|
||||
|
||||
/// Rx ring of descriptors and packets
|
||||
///
|
||||
/// This ring has three major locations that work in lock-step. The DMA will never write to the tail
|
||||
/// index, so the `read_index` must never pass the tail index. The `next_tail_index` is always 1
|
||||
/// slot ahead of the real tail index, and it must never pass the `read_index` or it could overwrite
|
||||
/// a packet still to be passed to the application.
|
||||
///
|
||||
/// nt can't pass r (no alloc)
|
||||
/// +---+---+---+---+ Read ok +---+---+---+---+ No Read +---+---+---+---+
|
||||
/// | | | | | ------------> | | | | | ------------> | | | | |
|
||||
/// +---+---+---+---+ Allocation ok +---+---+---+---+ +---+---+---+---+
|
||||
/// ^ ^t ^t ^ ^t ^
|
||||
/// |r |r |r
|
||||
/// |nt |nt |nt
|
||||
///
|
||||
///
|
||||
/// +---+---+---+---+ Read ok +---+---+---+---+ Can't read +---+---+---+---+
|
||||
/// | | | | | ------------> | | | | | ------------> | | | | |
|
||||
/// +---+---+---+---+ Allocation fail +---+---+---+---+ Allocation ok +---+---+---+---+
|
||||
/// ^ ^t ^ ^t ^ ^ ^ ^t
|
||||
/// |r | |r | | |r
|
||||
/// |nt |nt |nt
|
||||
///
|
||||
pub(crate) struct RDesRing<const N: usize> {
|
||||
descriptors: [RDes; N],
|
||||
buffers: [Option<PacketBox>; N],
|
||||
read_index: usize,
|
||||
next_tail_index: usize,
|
||||
pub(crate) struct RDesRing<'a> {
|
||||
descriptors: &'a mut [RDes],
|
||||
buffers: &'a mut [Packet<RX_BUFFER_SIZE>],
|
||||
index: usize,
|
||||
}
|
||||
|
||||
impl<const N: usize> RDesRing<N> {
|
||||
pub const fn new() -> Self {
|
||||
const RDES: RDes = RDes::new();
|
||||
const BUFFERS: Option<PacketBox> = None;
|
||||
impl<'a> RDesRing<'a> {
|
||||
pub(crate) fn new(descriptors: &'a mut [RDes], buffers: &'a mut [Packet<RX_BUFFER_SIZE>]) -> Self {
|
||||
assert!(descriptors.len() > 1);
|
||||
assert!(descriptors.len() == buffers.len());
|
||||
|
||||
Self {
|
||||
descriptors: [RDES; N],
|
||||
buffers: [BUFFERS; N],
|
||||
read_index: 0,
|
||||
next_tail_index: 0,
|
||||
}
|
||||
for (i, entry) in descriptors.iter().enumerate() {
|
||||
entry.setup(descriptors.get(i + 1), buffers[i].0.as_mut_ptr());
|
||||
}
|
||||
|
||||
pub(crate) fn init(&mut self) {
|
||||
assert!(N > 1);
|
||||
let mut last_index = 0;
|
||||
for (index, buf) in self.buffers.iter_mut().enumerate() {
|
||||
let pkt = match PacketBox::new(Packet::new()) {
|
||||
Some(p) => p,
|
||||
None => {
|
||||
if index == 0 {
|
||||
panic!("Could not allocate at least one buffer for Ethernet receiving");
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
};
|
||||
self.descriptors[index].set_ready(pkt.as_ptr() as u32, pkt.len());
|
||||
*buf = Some(pkt);
|
||||
last_index = index;
|
||||
}
|
||||
self.next_tail_index = (last_index + 1) % N;
|
||||
|
||||
// not sure if this is supposed to span all of the descriptor or just those that contain buffers
|
||||
{
|
||||
let mut previous: Option<&mut RDes> = None;
|
||||
for entry in self.descriptors.iter_mut() {
|
||||
if let Some(prev) = &mut previous {
|
||||
prev.setup(Some(entry));
|
||||
}
|
||||
previous = Some(entry);
|
||||
}
|
||||
|
||||
if let Some(entry) = &mut previous {
|
||||
entry.setup(None);
|
||||
}
|
||||
}
|
||||
|
||||
// Register txdescriptor start
|
||||
// Register rx descriptor start
|
||||
// NOTE (unsafe) Used for atomic writes
|
||||
unsafe {
|
||||
ETH.ethernet_dma()
|
||||
.dmardlar()
|
||||
.write(|w| w.0 = &self.descriptors as *const _ as u32);
|
||||
.write(|w| w.0 = descriptors.as_ptr() as u32);
|
||||
};
|
||||
// We already have fences in `set_owned`, which is called in `setup`
|
||||
|
||||
// Start receive
|
||||
unsafe { ETH.ethernet_dma().dmaomr().modify(|w| w.set_sr(DmaomrSr::STARTED)) };
|
||||
|
||||
self.demand_poll();
|
||||
Self {
|
||||
descriptors,
|
||||
buffers,
|
||||
index: 0,
|
||||
}
|
||||
}
|
||||
|
||||
fn demand_poll(&self) {
|
||||
pub(crate) fn demand_poll(&self) {
|
||||
unsafe { ETH.ethernet_dma().dmarpdr().write(|w| w.set_rpd(Rpd::POLL)) };
|
||||
}
|
||||
|
||||
pub(crate) fn on_interrupt(&mut self) {
|
||||
// XXX: Do we need to do anything here ? Maybe we should try to advance the tail ptr, but it
|
||||
// would soon hit the read ptr anyway, and we will wake smoltcp's stack on the interrupt
|
||||
// which should try to pop a packet...
|
||||
}
|
||||
|
||||
/// Get current `RunningState`
|
||||
fn running_state(&self) -> RunningState {
|
||||
match unsafe { ETH.ethernet_dma().dmasr().read().rps() } {
|
||||
|
|
@ -252,52 +184,52 @@ impl<const N: usize> RDesRing<N> {
|
|||
}
|
||||
}
|
||||
|
||||
pub(crate) fn pop_packet(&mut self) -> Option<PacketBuf> {
|
||||
if !self.running_state().is_running() {
|
||||
/// Get a received packet if any, or None.
|
||||
pub(crate) fn available(&mut self) -> Option<&mut [u8]> {
|
||||
if self.running_state() != RunningState::Running {
|
||||
self.demand_poll();
|
||||
}
|
||||
|
||||
// Not sure if the contents of the write buffer on the M7 can affects reads, so we are using
|
||||
// a DMB here just in case, it also serves as a hint to the compiler that we're syncing the
|
||||
// buffer (I think .-.)
|
||||
fence(Ordering::SeqCst);
|
||||
|
||||
let read_available = self.descriptors[self.read_index].available();
|
||||
let tail_index = (self.next_tail_index + N - 1) % N;
|
||||
|
||||
let pkt = if read_available && self.read_index != tail_index {
|
||||
let pkt = self.buffers[self.read_index].take();
|
||||
let len = self.descriptors[self.read_index].packet_len();
|
||||
|
||||
assert!(pkt.is_some());
|
||||
let valid = self.descriptors[self.read_index].valid();
|
||||
|
||||
self.read_index = (self.read_index + 1) % N;
|
||||
if valid {
|
||||
pkt.map(|p| p.slice(0..len))
|
||||
} else {
|
||||
None
|
||||
// We might have to process many packets, in case some have been rx'd but are invalid.
|
||||
loop {
|
||||
let descriptor = &mut self.descriptors[self.index];
|
||||
if !descriptor.available() {
|
||||
return None;
|
||||
}
|
||||
} else {
|
||||
None
|
||||
};
|
||||
|
||||
// Try to advance the tail_index
|
||||
if self.next_tail_index != self.read_index {
|
||||
match PacketBox::new(Packet::new()) {
|
||||
Some(b) => {
|
||||
let addr = b.as_ptr() as u32;
|
||||
let buffer_len = b.len();
|
||||
self.buffers[self.next_tail_index].replace(b);
|
||||
self.descriptors[self.next_tail_index].set_ready(addr, buffer_len);
|
||||
|
||||
// "Preceding reads and writes cannot be moved past subsequent writes."
|
||||
fence(Ordering::Release);
|
||||
|
||||
self.next_tail_index = (self.next_tail_index + 1) % N;
|
||||
// If packet is invalid, pop it and try again.
|
||||
if !descriptor.valid() {
|
||||
warn!("invalid packet: {:08x}", descriptor.rdes0.get());
|
||||
self.pop_packet();
|
||||
continue;
|
||||
}
|
||||
None => {}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
let descriptor = &mut self.descriptors[self.index];
|
||||
let len = descriptor.packet_len();
|
||||
return Some(&mut self.buffers[self.index].0[..len]);
|
||||
}
|
||||
|
||||
/// Pop the packet previously returned by `available`.
|
||||
pub(crate) fn pop_packet(&mut self) {
|
||||
let descriptor = &mut self.descriptors[self.index];
|
||||
assert!(descriptor.available());
|
||||
|
||||
self.descriptors[self.index].set_ready(self.buffers[self.index].0.as_mut_ptr());
|
||||
|
||||
self.demand_poll();
|
||||
|
||||
// Increment index.
|
||||
self.index += 1;
|
||||
if self.index == self.descriptors.len() {
|
||||
self.index = 0
|
||||
}
|
||||
}
|
||||
pkt
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,20 +1,10 @@
|
|||
use core::sync::atomic::{compiler_fence, fence, Ordering};
|
||||
|
||||
use embassy_net::PacketBuf;
|
||||
use stm32_metapac::eth::vals::St;
|
||||
use vcell::VolatileCell;
|
||||
|
||||
use crate::eth::TX_BUFFER_SIZE;
|
||||
use crate::pac::ETH;
|
||||
|
||||
#[non_exhaustive]
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
pub enum Error {
|
||||
NoBufferAvailable,
|
||||
// TODO: Break down this error into several others
|
||||
TransmissionError,
|
||||
}
|
||||
|
||||
/// Transmit and Receive Descriptor fields
|
||||
#[allow(dead_code)]
|
||||
mod tx_consts {
|
||||
|
|
@ -37,6 +27,8 @@ mod tx_consts {
|
|||
}
|
||||
use tx_consts::*;
|
||||
|
||||
use super::Packet;
|
||||
|
||||
/// Transmit Descriptor representation
|
||||
///
|
||||
/// * tdes0: control
|
||||
|
|
@ -44,7 +36,7 @@ use tx_consts::*;
|
|||
/// * tdes2: data buffer address
|
||||
/// * tdes3: next descriptor address
|
||||
#[repr(C)]
|
||||
struct TDes {
|
||||
pub(crate) struct TDes {
|
||||
tdes0: VolatileCell<u32>,
|
||||
tdes1: VolatileCell<u32>,
|
||||
tdes2: VolatileCell<u32>,
|
||||
|
|
@ -62,7 +54,7 @@ impl TDes {
|
|||
}
|
||||
|
||||
/// Return true if this TDes is not currently owned by the DMA
|
||||
pub fn available(&self) -> bool {
|
||||
fn available(&self) -> bool {
|
||||
(self.tdes0.get() & TXDESC_0_OWN) == 0
|
||||
}
|
||||
|
||||
|
|
@ -79,26 +71,26 @@ impl TDes {
|
|||
fence(Ordering::SeqCst);
|
||||
}
|
||||
|
||||
fn set_buffer1(&mut self, buffer: *const u8) {
|
||||
fn set_buffer1(&self, buffer: *const u8) {
|
||||
self.tdes2.set(buffer as u32);
|
||||
}
|
||||
|
||||
fn set_buffer1_len(&mut self, len: usize) {
|
||||
fn set_buffer1_len(&self, len: usize) {
|
||||
self.tdes1
|
||||
.set((self.tdes1.get() & !TXDESC_1_TBS_MASK) | ((len as u32) << TXDESC_1_TBS_SHIFT));
|
||||
}
|
||||
|
||||
// points to next descriptor (RCH)
|
||||
fn set_buffer2(&mut self, buffer: *const u8) {
|
||||
fn set_buffer2(&self, buffer: *const u8) {
|
||||
self.tdes3.set(buffer as u32);
|
||||
}
|
||||
|
||||
fn set_end_of_ring(&mut self) {
|
||||
fn set_end_of_ring(&self) {
|
||||
self.tdes0.set(self.tdes0.get() | TXDESC_0_TER);
|
||||
}
|
||||
|
||||
// set up as a part fo the ring buffer - configures the tdes
|
||||
pub fn setup(&mut self, next: Option<&Self>) {
|
||||
fn setup(&self, next: Option<&Self>) {
|
||||
// Defer this initialization to this function, so we can have `RingEntry` on bss.
|
||||
self.tdes0.set(TXDESC_0_TCH | TXDESC_0_IOC | TXDESC_0_FS | TXDESC_0_LS);
|
||||
match next {
|
||||
|
|
@ -111,85 +103,58 @@ impl TDes {
|
|||
}
|
||||
}
|
||||
|
||||
pub(crate) struct TDesRing<const N: usize> {
|
||||
descriptors: [TDes; N],
|
||||
buffers: [Option<PacketBuf>; N],
|
||||
next_entry: usize,
|
||||
}
|
||||
|
||||
impl<const N: usize> TDesRing<N> {
|
||||
pub const fn new() -> Self {
|
||||
const TDES: TDes = TDes::new();
|
||||
const BUFFERS: Option<PacketBuf> = None;
|
||||
|
||||
Self {
|
||||
descriptors: [TDES; N],
|
||||
buffers: [BUFFERS; N],
|
||||
next_entry: 0,
|
||||
}
|
||||
pub(crate) struct TDesRing<'a> {
|
||||
descriptors: &'a mut [TDes],
|
||||
buffers: &'a mut [Packet<TX_BUFFER_SIZE>],
|
||||
index: usize,
|
||||
}
|
||||
|
||||
impl<'a> TDesRing<'a> {
|
||||
/// Initialise this TDesRing. Assume TDesRing is corrupt
|
||||
///
|
||||
/// The current memory address of the buffers inside this TDesRing
|
||||
/// will be stored in the descriptors, so ensure the TDesRing is
|
||||
/// not moved after initialisation.
|
||||
pub(crate) fn init(&mut self) {
|
||||
assert!(N > 0);
|
||||
pub(crate) fn new(descriptors: &'a mut [TDes], buffers: &'a mut [Packet<TX_BUFFER_SIZE>]) -> Self {
|
||||
assert!(descriptors.len() > 0);
|
||||
assert!(descriptors.len() == buffers.len());
|
||||
|
||||
{
|
||||
let mut previous: Option<&mut TDes> = None;
|
||||
for entry in self.descriptors.iter_mut() {
|
||||
if let Some(prev) = &mut previous {
|
||||
prev.setup(Some(entry));
|
||||
for (i, entry) in descriptors.iter().enumerate() {
|
||||
entry.setup(descriptors.get(i + 1));
|
||||
}
|
||||
previous = Some(entry);
|
||||
}
|
||||
|
||||
if let Some(entry) = &mut previous {
|
||||
entry.setup(None);
|
||||
}
|
||||
}
|
||||
self.next_entry = 0;
|
||||
|
||||
// Register txdescriptor start
|
||||
// NOTE (unsafe) Used for atomic writes
|
||||
unsafe {
|
||||
ETH.ethernet_dma()
|
||||
.dmatdlar()
|
||||
.write(|w| w.0 = &self.descriptors as *const _ as u32);
|
||||
.write(|w| w.0 = descriptors.as_ptr() as u32);
|
||||
}
|
||||
|
||||
// "Preceding reads and writes cannot be moved past subsequent writes."
|
||||
#[cfg(feature = "fence")]
|
||||
fence(Ordering::Release);
|
||||
|
||||
// We don't need a compiler fence here because all interactions with `Descriptor` are
|
||||
// volatiles
|
||||
|
||||
// Start transmission
|
||||
unsafe { ETH.ethernet_dma().dmaomr().modify(|w| w.set_st(St::STARTED)) };
|
||||
Self {
|
||||
descriptors,
|
||||
buffers,
|
||||
index: 0,
|
||||
}
|
||||
}
|
||||
|
||||
/// Return true if a TDes is available for use
|
||||
pub(crate) fn available(&self) -> bool {
|
||||
self.descriptors[self.next_entry].available()
|
||||
pub(crate) fn len(&self) -> usize {
|
||||
self.descriptors.len()
|
||||
}
|
||||
|
||||
pub(crate) fn transmit(&mut self, pkt: PacketBuf) -> Result<(), Error> {
|
||||
if !self.available() {
|
||||
return Err(Error::NoBufferAvailable);
|
||||
/// Return the next available packet buffer for transmitting, or None
|
||||
pub(crate) fn available(&mut self) -> Option<&mut [u8]> {
|
||||
let descriptor = &mut self.descriptors[self.index];
|
||||
if descriptor.available() {
|
||||
Some(&mut self.buffers[self.index].0)
|
||||
} else {
|
||||
None
|
||||
}
|
||||
}
|
||||
|
||||
let descriptor = &mut self.descriptors[self.next_entry];
|
||||
/// Transmit the packet written in a buffer returned by `available`.
|
||||
pub(crate) fn transmit(&mut self, len: usize) {
|
||||
let descriptor = &mut self.descriptors[self.index];
|
||||
assert!(descriptor.available());
|
||||
|
||||
let pkt_len = pkt.len();
|
||||
let address = pkt.as_ptr() as *const u8;
|
||||
|
||||
descriptor.set_buffer1(address);
|
||||
descriptor.set_buffer1_len(pkt_len);
|
||||
|
||||
self.buffers[self.next_entry].replace(pkt);
|
||||
descriptor.set_buffer1(self.buffers[self.index].0.as_ptr());
|
||||
descriptor.set_buffer1_len(len);
|
||||
|
||||
descriptor.set_owned();
|
||||
|
||||
|
|
@ -198,36 +163,12 @@ impl<const N: usize> TDesRing<N> {
|
|||
// "Preceding reads and writes cannot be moved past subsequent writes."
|
||||
fence(Ordering::Release);
|
||||
|
||||
// Move the tail pointer (TPR) to the next descriptor
|
||||
self.next_entry = (self.next_entry + 1) % N;
|
||||
|
||||
// Move the index to the next descriptor
|
||||
self.index += 1;
|
||||
if self.index == self.descriptors.len() {
|
||||
self.index = 0
|
||||
}
|
||||
// Request the DMA engine to poll the latest tx descriptor
|
||||
unsafe { ETH.ethernet_dma().dmatpdr().modify(|w| w.0 = 1) }
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub(crate) fn on_interrupt(&mut self) -> Result<(), Error> {
|
||||
let previous = (self.next_entry + N - 1) % N;
|
||||
let td = &self.descriptors[previous];
|
||||
|
||||
// DMB to ensure that we are reading an updated value, probably not needed at the hardware
|
||||
// level, but this is also a hint to the compiler that we're syncing on the buffer.
|
||||
fence(Ordering::SeqCst);
|
||||
|
||||
let tdes0 = td.tdes0.get();
|
||||
|
||||
if tdes0 & TXDESC_0_OWN != 0 {
|
||||
// Transmission isn't done yet, probably a receive interrupt that fired this
|
||||
return Ok(());
|
||||
}
|
||||
|
||||
// Release the buffer
|
||||
self.buffers[previous].take();
|
||||
|
||||
if tdes0 & TXDESC_0_ES != 0 {
|
||||
Err(Error::TransmissionError)
|
||||
} else {
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ use embassy_executor::Spawner;
|
|||
use embassy_net::tcp::TcpSocket;
|
||||
use embassy_net::{Ipv4Address, Stack, StackResources};
|
||||
use embassy_stm32::eth::generic_smi::GenericSMI;
|
||||
use embassy_stm32::eth::{Ethernet, State};
|
||||
use embassy_stm32::eth::{Ethernet, PacketQueue};
|
||||
use embassy_stm32::peripherals::ETH;
|
||||
use embassy_stm32::rng::Rng;
|
||||
use embassy_stm32::time::mhz;
|
||||
|
|
@ -22,11 +22,12 @@ macro_rules! singleton {
|
|||
($val:expr) => {{
|
||||
type T = impl Sized;
|
||||
static STATIC_CELL: StaticCell<T> = StaticCell::new();
|
||||
STATIC_CELL.init_with(move || $val)
|
||||
let (x,) = STATIC_CELL.init(($val,));
|
||||
x
|
||||
}};
|
||||
}
|
||||
|
||||
type Device = Ethernet<'static, ETH, GenericSMI, 4, 4>;
|
||||
type Device = Ethernet<'static, ETH, GenericSMI>;
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn net_task(stack: &'static Stack<Device>) -> ! {
|
||||
|
|
@ -50,9 +51,8 @@ async fn main(spawner: Spawner) -> ! {
|
|||
let eth_int = interrupt::take!(ETH);
|
||||
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
|
||||
|
||||
let device = unsafe {
|
||||
Ethernet::new(
|
||||
singleton!(State::new()),
|
||||
let device = Ethernet::new(
|
||||
singleton!(PacketQueue::<16, 16>::new()),
|
||||
p.ETH,
|
||||
eth_int,
|
||||
p.PA1,
|
||||
|
|
@ -67,8 +67,7 @@ async fn main(spawner: Spawner) -> ! {
|
|||
GenericSMI,
|
||||
mac_addr,
|
||||
0,
|
||||
)
|
||||
};
|
||||
);
|
||||
|
||||
let config = embassy_net::ConfigStrategy::Dhcp;
|
||||
//let config = embassy_net::ConfigStrategy::Static(embassy_net::Config {
|
||||
|
|
@ -91,8 +90,8 @@ async fn main(spawner: Spawner) -> ! {
|
|||
info!("Network task initialized");
|
||||
|
||||
// Then we can use it!
|
||||
let mut rx_buffer = [0; 1024];
|
||||
let mut tx_buffer = [0; 1024];
|
||||
let mut rx_buffer = [0; 4096];
|
||||
let mut tx_buffer = [0; 4096];
|
||||
|
||||
loop {
|
||||
let mut socket = TcpSocket::new(&stack, &mut rx_buffer, &mut tx_buffer);
|
||||
|
|
@ -107,8 +106,9 @@ async fn main(spawner: Spawner) -> ! {
|
|||
continue;
|
||||
}
|
||||
info!("connected!");
|
||||
let buf = [0; 1024];
|
||||
loop {
|
||||
let r = socket.write_all(b"Hello\n").await;
|
||||
let r = socket.write_all(&buf).await;
|
||||
if let Err(e) = r {
|
||||
info!("write error: {:?}", e);
|
||||
return;
|
||||
|
|
|
|||
Loading…
Reference in a new issue