Simplify
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1 changed files with 84 additions and 91 deletions
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@ -103,6 +103,83 @@ pub enum PLLSource {
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/// HSI speed
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/// HSI speed
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pub const HSI_FREQ: u32 = 16_000_000;
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pub const HSI_FREQ: u32 = 16_000_000;
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impl Into<Pllmul> for PLLMul {
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fn into(self) -> Pllmul {
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match self {
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PLLMul::Mul3 => Pllmul::MUL3,
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PLLMul::Mul4 => Pllmul::MUL4,
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PLLMul::Mul6 => Pllmul::MUL6,
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PLLMul::Mul8 => Pllmul::MUL8,
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PLLMul::Mul12 => Pllmul::MUL12,
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PLLMul::Mul16 => Pllmul::MUL16,
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PLLMul::Mul24 => Pllmul::MUL24,
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PLLMul::Mul32 => Pllmul::MUL32,
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PLLMul::Mul48 => Pllmul::MUL48,
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}
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}
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}
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impl Into<Plldiv> for PLLDiv {
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fn into(self) -> Plldiv {
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match self {
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PLLDiv::Div2 => Plldiv::DIV2,
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PLLDiv::Div3 => Plldiv::DIV3,
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PLLDiv::Div4 => Plldiv::DIV4,
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}
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}
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}
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impl Into<Pllsrc> for PLLSource {
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fn into(self) -> Pllsrc {
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match self {
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PLLSource::HSI16 => Pllsrc::HSI16,
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PLLSource::HSE(_) => Pllsrc::HSE,
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}
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}
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}
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impl Into<Ppre> for APBPrescaler {
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fn into(self) -> Ppre {
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match self {
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APBPrescaler::NotDivided => Ppre::DIV1,
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APBPrescaler::Div2 => Ppre::DIV2,
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APBPrescaler::Div4 => Ppre::DIV4,
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APBPrescaler::Div8 => Ppre::DIV8,
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APBPrescaler::Div16 => Ppre::DIV16,
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}
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}
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}
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impl Into<Hpre> for AHBPrescaler {
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fn into(self) -> Hpre {
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match self {
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AHBPrescaler::NotDivided => Hpre::DIV1,
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AHBPrescaler::Div2 => Hpre::DIV2,
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AHBPrescaler::Div4 => Hpre::DIV4,
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AHBPrescaler::Div8 => Hpre::DIV8,
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AHBPrescaler::Div16 => Hpre::DIV16,
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AHBPrescaler::Div64 => Hpre::DIV64,
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AHBPrescaler::Div128 => Hpre::DIV128,
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AHBPrescaler::Div256 => Hpre::DIV256,
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AHBPrescaler::Div512 => Hpre::DIV512,
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}
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}
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}
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impl Into<Msirange> for MSIRange {
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fn into(self) -> Msirange {
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match self {
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MSIRange::Range0 => Msirange::RANGE0,
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MSIRange::Range1 => Msirange::RANGE1,
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MSIRange::Range2 => Msirange::RANGE2,
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MSIRange::Range3 => Msirange::RANGE3,
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MSIRange::Range4 => Msirange::RANGE4,
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MSIRange::Range5 => Msirange::RANGE5,
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MSIRange::Range6 => Msirange::RANGE6,
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}
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}
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}
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/// Clocks configutation
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/// Clocks configutation
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pub struct Config {
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pub struct Config {
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mux: ClockSrc,
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mux: ClockSrc,
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@ -192,11 +269,6 @@ impl Config {
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}
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}
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}
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}
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/// RCC peripheral
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pub struct Rcc {
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clocks: Clocks,
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}
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/*
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/*
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impl Rcc {
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impl Rcc {
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pub fn enable_lse(&mut self, _: &PWR) -> LSE {
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pub fn enable_lse(&mut self, _: &PWR) -> LSE {
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@ -266,7 +338,7 @@ impl Rcc {
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/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
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/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
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pub trait RccExt {
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pub trait RccExt {
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fn freeze(self, config: Config) -> Rcc;
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fn freeze(&mut self, config: Config) -> Clocks;
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}
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}
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impl RccExt for RCC {
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impl RccExt for RCC {
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@ -274,7 +346,7 @@ impl RccExt for RCC {
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// marking this function and all `Config` constructors and setters as `#[inline]`.
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// marking this function and all `Config` constructors and setters as `#[inline]`.
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// This saves ~900 Bytes for the `pwr.rs` example.
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// This saves ~900 Bytes for the `pwr.rs` example.
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#[inline]
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#[inline]
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fn freeze(self, cfgr: Config) -> Rcc {
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fn freeze(&mut self, cfgr: Config) -> Clocks {
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let rcc = pac::RCC;
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let rcc = pac::RCC;
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let (sys_clk, sw) = match cfgr.mux {
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let (sys_clk, sw) = match cfgr.mux {
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ClockSrc::MSI(range) => {
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ClockSrc::MSI(range) => {
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@ -409,7 +481,7 @@ impl RccExt for RCC {
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}
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}
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};
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};
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let clocks = Clocks {
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Clocks {
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source: cfgr.mux,
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source: cfgr.mux,
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sys_clk: sys_clk.hz(),
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sys_clk: sys_clk.hz(),
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ahb_clk: ahb_freq.hz(),
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ahb_clk: ahb_freq.hz(),
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@ -419,9 +491,7 @@ impl RccExt for RCC {
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apb2_tim_clk: apb2_tim_freq.hz(),
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apb2_tim_clk: apb2_tim_freq.hz(),
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apb1_pre,
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apb1_pre,
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apb2_pre,
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apb2_pre,
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};
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}
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Rcc { clocks }
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}
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}
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}
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}
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@ -506,83 +576,6 @@ pub struct MCOEnabled(());
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#[derive(Clone, Copy)]
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#[derive(Clone, Copy)]
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pub struct LSE(());
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pub struct LSE(());
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impl Into<Pllmul> for PLLMul {
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fn into(self) -> Pllmul {
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match self {
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PLLMul::Mul3 => Pllmul::MUL3,
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PLLMul::Mul4 => Pllmul::MUL4,
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PLLMul::Mul6 => Pllmul::MUL6,
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PLLMul::Mul8 => Pllmul::MUL8,
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PLLMul::Mul12 => Pllmul::MUL12,
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PLLMul::Mul16 => Pllmul::MUL16,
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PLLMul::Mul24 => Pllmul::MUL24,
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PLLMul::Mul32 => Pllmul::MUL32,
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PLLMul::Mul48 => Pllmul::MUL48,
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}
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}
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}
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impl Into<Plldiv> for PLLDiv {
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fn into(self) -> Plldiv {
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match self {
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PLLDiv::Div2 => Plldiv::DIV2,
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PLLDiv::Div3 => Plldiv::DIV3,
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PLLDiv::Div4 => Plldiv::DIV4,
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}
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}
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}
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impl Into<Pllsrc> for PLLSource {
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fn into(self) -> Pllsrc {
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match self {
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PLLSource::HSI16 => Pllsrc::HSI16,
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PLLSource::HSE(_) => Pllsrc::HSE,
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}
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}
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}
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impl Into<Ppre> for APBPrescaler {
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fn into(self) -> Ppre {
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match self {
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APBPrescaler::NotDivided => Ppre::DIV1,
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APBPrescaler::Div2 => Ppre::DIV2,
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APBPrescaler::Div4 => Ppre::DIV4,
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APBPrescaler::Div8 => Ppre::DIV8,
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APBPrescaler::Div16 => Ppre::DIV16,
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}
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}
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}
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impl Into<Hpre> for AHBPrescaler {
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fn into(self) -> Hpre {
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match self {
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AHBPrescaler::NotDivided => Hpre::DIV1,
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AHBPrescaler::Div2 => Hpre::DIV2,
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AHBPrescaler::Div4 => Hpre::DIV4,
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AHBPrescaler::Div8 => Hpre::DIV8,
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AHBPrescaler::Div16 => Hpre::DIV16,
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AHBPrescaler::Div64 => Hpre::DIV64,
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AHBPrescaler::Div128 => Hpre::DIV128,
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AHBPrescaler::Div256 => Hpre::DIV256,
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AHBPrescaler::Div512 => Hpre::DIV512,
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}
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}
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}
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impl Into<Msirange> for MSIRange {
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fn into(self) -> Msirange {
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match self {
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MSIRange::Range0 => Msirange::RANGE0,
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MSIRange::Range1 => Msirange::RANGE1,
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MSIRange::Range2 => Msirange::RANGE2,
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MSIRange::Range3 => Msirange::RANGE3,
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MSIRange::Range4 => Msirange::RANGE4,
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MSIRange::Range5 => Msirange::RANGE5,
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MSIRange::Range6 => Msirange::RANGE6,
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}
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}
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}
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// We use TIM2 as SystemClock
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// We use TIM2 as SystemClock
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pub type SystemClock = Clock<TIM2>;
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pub type SystemClock = Clock<TIM2>;
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@ -598,8 +591,8 @@ pub unsafe fn init(config: Config) -> SystemClock {
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w.set_iophen(enabled);
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w.set_iophen(enabled);
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});
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});
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let r = <peripherals::RCC as embassy::util::Steal>::steal();
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let mut r = <peripherals::RCC as embassy::util::Steal>::steal();
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let r = r.freeze(config);
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let clocks = r.freeze(config);
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rcc.apb1enr().modify(|w| w.set_tim2en(Lptimen::ENABLED));
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rcc.apb1enr().modify(|w| w.set_tim2en(Lptimen::ENABLED));
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rcc.apb1rstr().modify(|w| w.set_tim2rst(true));
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rcc.apb1rstr().modify(|w| w.set_tim2rst(true));
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@ -608,6 +601,6 @@ pub unsafe fn init(config: Config) -> SystemClock {
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Clock::new(
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Clock::new(
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<peripherals::TIM2 as embassy::util::Steal>::steal(),
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<peripherals::TIM2 as embassy::util::Steal>::steal(),
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interrupt::take!(TIM2),
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interrupt::take!(TIM2),
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r.clocks.apb1_clk(),
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clocks.apb1_clk(),
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)
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)
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}
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}
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