From 1920e90dcdbebc1e2f86001f1491a9f28eb0f0f3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Alse=CC=81r?= <henrik.alser@me.com>
Date: Sat, 5 Nov 2022 00:15:43 +0100
Subject: [PATCH 01/14] embassy-nrf: Add SPIS module

---
 embassy-nrf/src/chips/nrf52805.rs    |   2 +
 embassy-nrf/src/chips/nrf52810.rs    |   2 +
 embassy-nrf/src/chips/nrf52811.rs    |   3 +
 embassy-nrf/src/chips/nrf52820.rs    |   3 +
 embassy-nrf/src/chips/nrf52832.rs    |   4 +
 embassy-nrf/src/chips/nrf52833.rs    |   4 +
 embassy-nrf/src/chips/nrf52840.rs    |   4 +
 embassy-nrf/src/chips/nrf5340_app.rs |   5 +
 embassy-nrf/src/chips/nrf5340_net.rs |   1 +
 embassy-nrf/src/chips/nrf9160.rs     |   5 +
 embassy-nrf/src/lib.rs               |   1 +
 embassy-nrf/src/spis.rs              | 516 +++++++++++++++++++++++++++
 examples/nrf/src/bin/spis.rs         |  25 ++
 13 files changed, 575 insertions(+)
 create mode 100644 embassy-nrf/src/spis.rs
 create mode 100644 examples/nrf/src/bin/spis.rs

diff --git a/embassy-nrf/src/chips/nrf52805.rs b/embassy-nrf/src/chips/nrf52805.rs
index dec31a84c..11a6840c8 100644
--- a/embassy-nrf/src/chips/nrf52805.rs
+++ b/embassy-nrf/src/chips/nrf52805.rs
@@ -131,6 +131,8 @@ impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
 
 impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0);
 
+impl_spis!(SPI0, SPIS0, SPIM0_SPIS0_SPI0);
+
 impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0);
 
 impl_timer!(TIMER0, TIMER0, TIMER0);
diff --git a/embassy-nrf/src/chips/nrf52810.rs b/embassy-nrf/src/chips/nrf52810.rs
index e57a4a383..3614cd229 100644
--- a/embassy-nrf/src/chips/nrf52810.rs
+++ b/embassy-nrf/src/chips/nrf52810.rs
@@ -137,6 +137,8 @@ impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
 
 impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0);
 
+impl_spis!(SPI0, SPIS0, SPIM0_SPIS0_SPI0);
+
 impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0);
 
 impl_pwm!(PWM0, PWM0, PWM0);
diff --git a/embassy-nrf/src/chips/nrf52811.rs b/embassy-nrf/src/chips/nrf52811.rs
index 918404cf1..dc4a8660e 100644
--- a/embassy-nrf/src/chips/nrf52811.rs
+++ b/embassy-nrf/src/chips/nrf52811.rs
@@ -138,6 +138,9 @@ impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
 impl_spim!(TWISPI0, SPIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
 impl_spim!(SPI1, SPIM1, SPIM1_SPIS1_SPI1);
 
+impl_spis!(TWISPI0, SPIS0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
+impl_spis!(SPI1, SPIS1, SPIM1_SPIS1_SPI1);
+
 impl_twim!(TWISPI0, TWIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
 
 impl_pwm!(PWM0, PWM0, PWM0);
diff --git a/embassy-nrf/src/chips/nrf52820.rs b/embassy-nrf/src/chips/nrf52820.rs
index dba033b0f..7668920bd 100644
--- a/embassy-nrf/src/chips/nrf52820.rs
+++ b/embassy-nrf/src/chips/nrf52820.rs
@@ -136,6 +136,9 @@ impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
 impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
 impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
 
+impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
+impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
+
 impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
 impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
 
diff --git a/embassy-nrf/src/chips/nrf52832.rs b/embassy-nrf/src/chips/nrf52832.rs
index 81e66c193..851643b55 100644
--- a/embassy-nrf/src/chips/nrf52832.rs
+++ b/embassy-nrf/src/chips/nrf52832.rs
@@ -146,6 +146,10 @@ impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
 impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
 impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
 
+impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
+impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
+impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2);
+
 impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
 impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
 
diff --git a/embassy-nrf/src/chips/nrf52833.rs b/embassy-nrf/src/chips/nrf52833.rs
index 92499e3c9..5342ba8c2 100644
--- a/embassy-nrf/src/chips/nrf52833.rs
+++ b/embassy-nrf/src/chips/nrf52833.rs
@@ -174,6 +174,10 @@ impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
 impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
 impl_spim!(SPI3, SPIM3, SPIM3);
 
+impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
+impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
+impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2);
+
 impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
 impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
 
diff --git a/embassy-nrf/src/chips/nrf52840.rs b/embassy-nrf/src/chips/nrf52840.rs
index 4beadfba8..a330aef8b 100644
--- a/embassy-nrf/src/chips/nrf52840.rs
+++ b/embassy-nrf/src/chips/nrf52840.rs
@@ -177,6 +177,10 @@ impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
 impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
 impl_spim!(SPI3, SPIM3, SPIM3);
 
+impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
+impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
+impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2);
+
 impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
 impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
 
diff --git a/embassy-nrf/src/chips/nrf5340_app.rs b/embassy-nrf/src/chips/nrf5340_app.rs
index 7845d4a8e..1c027ec02 100644
--- a/embassy-nrf/src/chips/nrf5340_app.rs
+++ b/embassy-nrf/src/chips/nrf5340_app.rs
@@ -361,6 +361,11 @@ impl_spim!(UARTETWISPI1, SPIM1, SERIAL1);
 impl_spim!(UARTETWISPI2, SPIM2, SERIAL2);
 impl_spim!(UARTETWISPI3, SPIM3, SERIAL3);
 
+impl_spis!(UARTETWISPI0, SPIS0, SERIAL0);
+impl_spis!(UARTETWISPI1, SPIS1, SERIAL1);
+impl_spis!(UARTETWISPI2, SPIS2, SERIAL2);
+impl_spis!(UARTETWISPI3, SPIS3, SERIAL3);
+
 impl_twim!(UARTETWISPI0, TWIM0, SERIAL0);
 impl_twim!(UARTETWISPI1, TWIM1, SERIAL1);
 impl_twim!(UARTETWISPI2, TWIM2, SERIAL2);
diff --git a/embassy-nrf/src/chips/nrf5340_net.rs b/embassy-nrf/src/chips/nrf5340_net.rs
index ae136e09d..3bcd44fcb 100644
--- a/embassy-nrf/src/chips/nrf5340_net.rs
+++ b/embassy-nrf/src/chips/nrf5340_net.rs
@@ -238,6 +238,7 @@ embassy_hal_common::peripherals! {
 
 impl_uarte!(UARTETWISPI0, UARTE0, SERIAL0);
 impl_spim!(UARTETWISPI0, SPIM0, SERIAL0);
+impl_spis!(UARTETWISPI0, SPIS0, SERIAL0);
 impl_twim!(UARTETWISPI0, TWIM0, SERIAL0);
 
 impl_timer!(TIMER0, TIMER0, TIMER0);
diff --git a/embassy-nrf/src/chips/nrf9160.rs b/embassy-nrf/src/chips/nrf9160.rs
index b5a53ed80..0dfa112fe 100644
--- a/embassy-nrf/src/chips/nrf9160.rs
+++ b/embassy-nrf/src/chips/nrf9160.rs
@@ -275,6 +275,11 @@ impl_spim!(UARTETWISPI1, SPIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
 impl_spim!(UARTETWISPI2, SPIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
 impl_spim!(UARTETWISPI3, SPIM3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
 
+impl_spis!(UARTETWISPI0, SPIS0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
+impl_spis!(UARTETWISPI1, SPIS1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
+impl_spis!(UARTETWISPI2, SPIS2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
+impl_spis!(UARTETWISPI3, SPIS3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
+
 impl_twim!(UARTETWISPI0, TWIM0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
 impl_twim!(UARTETWISPI1, TWIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
 impl_twim!(UARTETWISPI2, TWIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index bc70fc2f6..587e19be5 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -96,6 +96,7 @@ pub mod rng;
 #[cfg(not(any(feature = "nrf52820", feature = "_nrf5340-net")))]
 pub mod saadc;
 pub mod spim;
+pub mod spis;
 #[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
 pub mod temp;
 pub mod timer;
diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
new file mode 100644
index 000000000..32c0b6f93
--- /dev/null
+++ b/embassy-nrf/src/spis.rs
@@ -0,0 +1,516 @@
+#![macro_use]
+
+use core::future::poll_fn;
+use core::sync::atomic::{compiler_fence, Ordering};
+use core::task::Poll;
+
+use embassy_embedded_hal::SetConfig;
+use embassy_hal_common::{into_ref, PeripheralRef};
+pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
+
+use crate::chip::FORCE_COPY_BUFFER_SIZE;
+use crate::gpio::sealed::Pin as _;
+use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
+use crate::interrupt::{Interrupt, InterruptExt};
+use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
+use crate::{pac, Peripheral};
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Error {
+    TxBufferTooLong,
+    RxBufferTooLong,
+    /// EasyDMA can only read from data memory, read only buffers in flash will fail.
+    DMABufferNotInDataMemory,
+}
+
+/// Interface for the SPIS peripheral using EasyDMA to offload the transmission and reception workload.
+///
+/// For more details about EasyDMA, consult the module documentation.
+pub struct Spis<'d, T: Instance> {
+    _p: PeripheralRef<'d, T>,
+}
+
+#[non_exhaustive]
+pub struct Config {
+    pub mode: Mode,
+    pub orc: u8,
+    pub def: u8,
+    pub auto_acquire: bool,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            mode: MODE_0,
+            orc: 0x00,
+            def: 0x00,
+            auto_acquire: true,
+        }
+    }
+}
+
+impl<'d, T: Instance> Spis<'d, T> {
+    pub fn new(
+        spis: impl Peripheral<P = T> + 'd,
+        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        cs: impl Peripheral<P = impl GpioPin> + 'd,
+        sck: impl Peripheral<P = impl GpioPin> + 'd,
+        miso: impl Peripheral<P = impl GpioPin> + 'd,
+        mosi: impl Peripheral<P = impl GpioPin> + 'd,
+        config: Config,
+    ) -> Self {
+        into_ref!(cs, sck, miso, mosi);
+        Self::new_inner(
+            spis,
+            irq,
+            cs.map_into(),
+            sck.map_into(),
+            Some(miso.map_into()),
+            Some(mosi.map_into()),
+            config,
+        )
+    }
+
+    pub fn new_txonly(
+        spis: impl Peripheral<P = T> + 'd,
+        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        cs: impl Peripheral<P = impl GpioPin> + 'd,
+        sck: impl Peripheral<P = impl GpioPin> + 'd,
+        mosi: impl Peripheral<P = impl GpioPin> + 'd,
+        config: Config,
+    ) -> Self {
+        into_ref!(cs, sck, mosi);
+        Self::new_inner(spis, irq, cs.map_into(), sck.map_into(), None, Some(mosi.map_into()), config)
+    }
+
+    pub fn new_rxonly(
+        spis: impl Peripheral<P = T> + 'd,
+        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        cs: impl Peripheral<P = impl GpioPin> + 'd,
+        sck: impl Peripheral<P = impl GpioPin> + 'd,
+        miso: impl Peripheral<P = impl GpioPin> + 'd,
+        config: Config,
+    ) -> Self {
+        into_ref!(cs, sck, miso);
+        Self::new_inner(spis, irq, cs.map_into(), sck.map_into(), Some(miso.map_into()), None, config)
+    }
+
+    fn new_inner(
+        spis: impl Peripheral<P = T> + 'd,
+        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        cs: PeripheralRef<'d, AnyPin>,
+        sck: PeripheralRef<'d, AnyPin>,
+        miso: Option<PeripheralRef<'d, AnyPin>>,
+        mosi: Option<PeripheralRef<'d, AnyPin>>,
+        config: Config,
+    ) -> Self {
+        into_ref!(cs, spis, irq);
+
+        let r = T::regs();
+
+        // Configure pins
+        sck.conf().write(|w| w.input().connect().drive().h0h1());
+        cs.conf().write(|w| w.input().connect().drive().h0h1());
+        if let Some(mosi) = &mosi {
+            mosi.conf().write(|w| w.input().connect().drive().h0h1());
+        }
+        if let Some(miso) = &miso {
+            miso.conf().write(|w| w.dir().output().drive().h0h1());
+        }
+
+        match config.mode.polarity {
+            Polarity::IdleHigh => {
+                sck.set_high();
+                if let Some(mosi) = &mosi {
+                    mosi.set_high();
+                }
+            }
+            Polarity::IdleLow => {
+                sck.set_low();
+                if let Some(mosi) = &mosi {
+                    mosi.set_low();
+                }
+            }
+        }
+
+        if config.auto_acquire {
+            r.shorts.write(|w| w.end_acquire().bit(true));
+        }
+
+        // Select pins.
+        r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
+        r.psel.csn.write(|w| unsafe { w.bits(cs.psel_bits()) });
+        r.psel.mosi.write(|w| unsafe { w.bits(mosi.psel_bits()) });
+        r.psel.miso.write(|w| unsafe { w.bits(miso.psel_bits()) });
+
+        // Enable SPIS instance.
+        r.enable.write(|w| w.enable().enabled());
+
+        // Configure mode.
+        let mode = config.mode;
+        r.config.write(|w| {
+            match mode {
+                MODE_0 => {
+                    w.order().msb_first();
+                    w.cpol().active_high();
+                    w.cpha().leading();
+                }
+                MODE_1 => {
+                    w.order().msb_first();
+                    w.cpol().active_high();
+                    w.cpha().trailing();
+                }
+                MODE_2 => {
+                    w.order().msb_first();
+                    w.cpol().active_low();
+                    w.cpha().leading();
+                }
+                MODE_3 => {
+                    w.order().msb_first();
+                    w.cpol().active_low();
+                    w.cpha().trailing();
+                }
+            }
+
+            w
+        });
+
+        // Set over-read character
+        let orc = config.orc;
+        r.orc.write(|w| unsafe { w.orc().bits(orc) });
+
+        // Set default character
+        let def = config.def;
+        r.def.write(|w| unsafe { w.def().bits(def) });
+
+        // Disable all events interrupts
+        r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
+
+        irq.set_handler(Self::on_interrupt);
+        irq.unpend();
+        irq.enable();
+
+        Self { _p: spis }
+    }
+
+    fn on_interrupt(_: *mut ()) {
+        let r = T::regs();
+        let s = T::state();
+
+        if r.events_end.read().bits() != 0 {
+            s.end_waker.wake();
+            r.intenclr.write(|w| w.end().clear());
+        }
+
+        if r.events_acquired.read().bits() != 0 {
+            s.acquire_waker.wake();
+            r.intenclr.write(|w| w.acquired().clear());
+        }
+    }
+
+    fn prepare(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
+        slice_in_ram_or(tx, Error::DMABufferNotInDataMemory)?;
+        // NOTE: RAM slice check for rx is not necessary, as a mutable
+        // slice can only be built from data located in RAM.
+
+        compiler_fence(Ordering::SeqCst);
+
+        let r = T::regs();
+
+        // Set up the DMA write.
+        let (ptr, len) = slice_ptr_parts(tx);
+        r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
+        r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
+
+        // Set up the DMA read.
+        let (ptr, len) = slice_ptr_parts_mut(rx);
+        r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
+        r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
+
+        // Reset and enable the end event
+        r.events_end.reset();
+        r.intenset.write(|w| w.end().set());
+
+        // Release the semaphore
+        r.tasks_release.write(|w| unsafe { w.bits(1) });
+
+        Ok(())
+    }
+
+    fn blocking_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(usize, usize), Error> {
+        self.prepare(rx, tx)?;
+        let r = T::regs();
+
+        // Wait for 'end' event.
+        while r.events_end.read().bits() == 0 {}
+
+        let n_rx = r.rxd.amount.read().bits() as usize;
+        let n_tx = r.txd.amount.read().bits() as usize;
+
+        compiler_fence(Ordering::SeqCst);
+
+        Ok((n_rx, n_tx))
+    }
+
+    fn blocking_inner(&mut self, rx: &mut [u8], tx: &[u8]) -> Result<(usize, usize), Error> {
+        match self.blocking_inner_from_ram(rx, tx) {
+            Ok(n) => Ok(n),
+            Err(Error::DMABufferNotInDataMemory) => {
+                trace!("Copying SPIS tx buffer into RAM for DMA");
+                let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
+                tx_ram_buf.copy_from_slice(tx);
+                self.blocking_inner_from_ram(rx, tx_ram_buf)
+            }
+            Err(error) => Err(error),
+        }
+    }
+
+    async fn async_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(usize, usize), Error> {
+        let r = T::regs();
+        let s = T::state();
+
+        if r.semstat.read().bits() != 1 {
+            // Reset and enable the acquire event
+            r.events_acquired.reset();
+            r.intenset.write(|w| w.acquired().set());
+
+            // Requests acquiring the SPIS semaphore
+            r.tasks_acquire.write(|w| unsafe { w.bits(1) });
+            
+            // Wait for 'acquire' event.
+            poll_fn(|cx| {
+                s.acquire_waker.register(cx.waker());
+                if r.events_acquired.read().bits() != 0 {
+                    return Poll::Ready(());
+                }
+                Poll::Pending
+            })
+            .await;
+        }
+
+        self.prepare(rx, tx)?;
+
+        // Wait for 'end' event.
+        poll_fn(|cx| {
+            s.end_waker.register(cx.waker());
+            if r.events_end.read().bits() != 0 {
+                return Poll::Ready(());
+            }
+
+            Poll::Pending
+        })
+        .await;
+
+        let n_rx = r.rxd.amount.read().bits() as usize;
+        let n_tx = r.txd.amount.read().bits() as usize;
+
+        compiler_fence(Ordering::SeqCst);
+
+        Ok((n_rx, n_tx))
+    }
+
+    async fn async_inner(&mut self, rx: &mut [u8], tx: &[u8]) -> Result<(usize, usize), Error> {
+        match self.async_inner_from_ram(rx, tx).await {
+            Ok(n) => Ok(n),
+            Err(Error::DMABufferNotInDataMemory) => {
+                trace!("Copying SPIS tx buffer into RAM for DMA");
+                let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
+                tx_ram_buf.copy_from_slice(tx);
+                self.async_inner_from_ram(rx, tx_ram_buf).await
+            }
+            Err(error) => Err(error),
+        }
+    }
+
+    /// Reads data from the SPI bus without sending anything. Blocks until the buffer has been filled.
+    /// Returns number of bytes read
+    pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<usize, Error> {
+        self.blocking_inner(data, &[]).map(|n| n.0)
+    }
+
+    /// Simultaneously sends and receives data. Blocks until the transmission is completed.
+    /// If necessary, the write buffer will be copied into RAM (see struct description for detail).
+    /// Returns number of bytes transferred `(n_rx, n_tx)`
+    pub fn blocking_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
+        self.blocking_inner(read, write)
+    }
+
+    /// Same as [`blocking_transfer`](Spis::blocking_transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
+    /// Returns number of bytes transferred `(n_rx, n_tx)`
+    pub fn blocking_transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
+        self.blocking_inner(read, write)
+    }
+
+    /// Simultaneously sends and receives data.
+    /// Places the received data into the same buffer and blocks until the transmission is completed.
+    /// Returns number of bytes transferred
+    pub fn blocking_transfer_in_place(&mut self, data: &mut [u8]) -> Result<usize, Error> {
+        self.blocking_inner_from_ram(data, data).map(|n| n.0)
+    }
+
+    /// Sends data, discarding any received data. Blocks  until the transmission is completed.
+    /// If necessary, the write buffer will be copied into RAM (see struct description for detail).
+    /// Returns number of bytes written
+    pub fn blocking_write(&mut self, data: &[u8]) -> Result<usize, Error> {
+        self.blocking_inner(&mut [], data).map(|n| n.1)
+    }
+
+    /// Same as [`blocking_write`](Spis::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
+    /// Returns number of bytes written
+    pub fn blocking_write_from_ram(&mut self, data: &[u8]) -> Result<usize, Error> {
+        self.blocking_inner(&mut [], data).map(|n| n.1)
+    }
+
+    /// Reads data from the SPI bus without sending anything.
+    /// Returns number of bytes read
+    pub async fn read(&mut self, data: &mut [u8]) -> Result<usize, Error> {
+        self.async_inner(data, &[]).await.map(|n| n.0)
+    }
+
+    /// Simultaneously sends and receives data.
+    /// If necessary, the write buffer will be copied into RAM (see struct description for detail).
+    /// Returns number of bytes transferred `(n_rx, n_tx)`
+    pub async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
+        self.async_inner(read, write).await
+    }
+
+    /// Same as [`transfer`](Spis::transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
+    /// Returns number of bytes transferred `(n_rx, n_tx)`
+    pub async fn transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
+        self.async_inner_from_ram(read, write).await
+    }
+
+    /// Simultaneously sends and receives data. Places the received data into the same buffer.
+    /// Returns number of bytes transferred
+    pub async fn transfer_in_place(&mut self, data: &mut [u8]) -> Result<usize, Error> {
+        self.async_inner_from_ram(data, data).await.map(|n| n.0)
+    }
+
+    /// Sends data, discarding any received data.
+    /// If necessary, the write buffer will be copied into RAM (see struct description for detail).
+    /// Returns number of bytes written
+    pub async fn write(&mut self, data: &[u8]) -> Result<usize, Error> {
+        self.async_inner(&mut [], data).await.map(|n| n.1)
+    }
+
+    /// Same as [`write`](Spis::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
+    /// Returns number of bytes written
+    pub async fn write_from_ram(&mut self, data: &[u8]) -> Result<usize, Error> {
+        self.async_inner_from_ram(&mut [], data).await.map(|n| n.1)
+    }
+}
+
+impl<'d, T: Instance> Drop for Spis<'d, T> {
+    fn drop(&mut self) {
+        trace!("spis drop");
+
+        // Disable
+        let r = T::regs();
+        r.enable.write(|w| w.enable().disabled());
+
+        gpio::deconfigure_pin(r.psel.sck.read().bits());
+        gpio::deconfigure_pin(r.psel.csn.read().bits());
+        gpio::deconfigure_pin(r.psel.miso.read().bits());
+        gpio::deconfigure_pin(r.psel.mosi.read().bits());
+
+        trace!("spis drop: done");
+    }
+}
+
+pub(crate) mod sealed {
+    use embassy_sync::waitqueue::AtomicWaker;
+
+    use super::*;
+
+    pub struct State {
+        pub end_waker: AtomicWaker,
+        pub acquire_waker: AtomicWaker,
+    }
+
+    impl State {
+        pub const fn new() -> Self {
+            Self {
+                end_waker: AtomicWaker::new(),
+                acquire_waker: AtomicWaker::new(),
+            }
+        }
+    }
+
+    pub trait Instance {
+        fn regs() -> &'static pac::spis0::RegisterBlock;
+        fn state() -> &'static State;
+    }
+}
+
+pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static {
+    type Interrupt: Interrupt;
+}
+
+macro_rules! impl_spis {
+    ($type:ident, $pac_type:ident, $irq:ident) => {
+        impl crate::spis::sealed::Instance for peripherals::$type {
+            fn regs() -> &'static pac::spis0::RegisterBlock {
+                unsafe { &*pac::$pac_type::ptr() }
+            }
+            fn state() -> &'static crate::spis::sealed::State {
+                static STATE: crate::spis::sealed::State = crate::spis::sealed::State::new();
+                &STATE
+            }
+        }
+        impl crate::spis::Instance for peripherals::$type {
+            type Interrupt = crate::interrupt::$irq;
+        }
+    };
+}
+
+// ====================
+
+impl<'d, T: Instance> SetConfig for Spis<'d, T> {
+    type Config = Config;
+    fn set_config(&mut self, config: &Self::Config) {
+        let r = T::regs();
+        // Configure mode.
+        let mode = config.mode;
+        r.config.write(|w| {
+            match mode {
+                MODE_0 => {
+                    w.order().msb_first();
+                    w.cpol().active_high();
+                    w.cpha().leading();
+                }
+                MODE_1 => {
+                    w.order().msb_first();
+                    w.cpol().active_high();
+                    w.cpha().trailing();
+                }
+                MODE_2 => {
+                    w.order().msb_first();
+                    w.cpol().active_low();
+                    w.cpha().leading();
+                }
+                MODE_3 => {
+                    w.order().msb_first();
+                    w.cpol().active_low();
+                    w.cpha().trailing();
+                }
+            }
+
+            w
+        });
+
+        // Set over-read character
+        let orc = config.orc;
+        r.orc.write(|w| unsafe { w.orc().bits(orc) });
+
+        // Set default character
+        let def = config.def;
+        r.def.write(|w| unsafe { w.def().bits(def) });
+
+        // Set auto acquire
+        let auto_acquire = config.auto_acquire;
+        r.shorts.write(|w| w.end_acquire().bit(auto_acquire));
+
+    }
+}
diff --git a/examples/nrf/src/bin/spis.rs b/examples/nrf/src/bin/spis.rs
new file mode 100644
index 000000000..181e08404
--- /dev/null
+++ b/examples/nrf/src/bin/spis.rs
@@ -0,0 +1,25 @@
+#![no_std]
+#![no_main]
+#![feature(type_alias_impl_trait)]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_nrf::interrupt;
+use embassy_nrf::spis::{self, Config};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_nrf::init(Default::default());
+    info!("Running!");
+
+    let irq = interrupt::take!(SPIM2_SPIS2_SPI2);
+    let mut spis = spis::Spis::new(p.SPI2, irq, p.P0_31, p.P0_29, p.P0_28, p.P0_30, Config::default());
+
+    loop {
+        let mut buf = [0_u8; 64];
+        if let Ok(n) = spis.read(&mut buf).await {
+            info!("RX: {:?}", buf[..n]);
+        }
+    }
+}

From a3e8a6bc3a706bc59b9d017699eaab93c1ba60d3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Alse=CC=81r?= <henrik.alser@me.com>
Date: Sat, 5 Nov 2022 00:19:52 +0100
Subject: [PATCH 02/14] rustfmt

---
 embassy-nrf/src/spis.rs | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 32c0b6f93..ab7986b89 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -82,7 +82,15 @@ impl<'d, T: Instance> Spis<'d, T> {
         config: Config,
     ) -> Self {
         into_ref!(cs, sck, mosi);
-        Self::new_inner(spis, irq, cs.map_into(), sck.map_into(), None, Some(mosi.map_into()), config)
+        Self::new_inner(
+            spis,
+            irq,
+            cs.map_into(),
+            sck.map_into(),
+            None,
+            Some(mosi.map_into()),
+            config,
+        )
     }
 
     pub fn new_rxonly(
@@ -94,7 +102,15 @@ impl<'d, T: Instance> Spis<'d, T> {
         config: Config,
     ) -> Self {
         into_ref!(cs, sck, miso);
-        Self::new_inner(spis, irq, cs.map_into(), sck.map_into(), Some(miso.map_into()), None, config)
+        Self::new_inner(
+            spis,
+            irq,
+            cs.map_into(),
+            sck.map_into(),
+            Some(miso.map_into()),
+            None,
+            config,
+        )
     }
 
     fn new_inner(
@@ -278,7 +294,7 @@ impl<'d, T: Instance> Spis<'d, T> {
 
             // Requests acquiring the SPIS semaphore
             r.tasks_acquire.write(|w| unsafe { w.bits(1) });
-            
+
             // Wait for 'acquire' event.
             poll_fn(|cx| {
                 s.acquire_waker.register(cx.waker());
@@ -511,6 +527,5 @@ impl<'d, T: Instance> SetConfig for Spis<'d, T> {
         // Set auto acquire
         let auto_acquire = config.auto_acquire;
         r.shorts.write(|w| w.end_acquire().bit(auto_acquire));
-
     }
 }

From 7da18e194a8a9fef207803b96b16e7b7bc787ca7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Alse=CC=81r?= <henrik.alser@me.com>
Date: Sat, 5 Nov 2022 01:12:25 +0100
Subject: [PATCH 03/14] Add status checks

---
 embassy-nrf/src/spis.rs      | 69 ++++++++++++++++++++++--------------
 examples/nrf/src/bin/spis.rs |  4 +--
 2 files changed, 44 insertions(+), 29 deletions(-)

diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index ab7986b89..71106b7df 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -126,7 +126,7 @@ impl<'d, T: Instance> Spis<'d, T> {
 
         let r = T::regs();
 
-        // Configure pins
+        // Configure pins.
         sck.conf().write(|w| w.input().connect().drive().h0h1());
         cs.conf().write(|w| w.input().connect().drive().h0h1());
         if let Some(mosi) = &mosi {
@@ -151,10 +151,6 @@ impl<'d, T: Instance> Spis<'d, T> {
             }
         }
 
-        if config.auto_acquire {
-            r.shorts.write(|w| w.end_acquire().bit(true));
-        }
-
         // Select pins.
         r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
         r.psel.csn.write(|w| unsafe { w.bits(cs.psel_bits()) });
@@ -193,15 +189,20 @@ impl<'d, T: Instance> Spis<'d, T> {
             w
         });
 
-        // Set over-read character
+        // Set over-read character.
         let orc = config.orc;
         r.orc.write(|w| unsafe { w.orc().bits(orc) });
 
-        // Set default character
+        // Set default character.
         let def = config.def;
         r.def.write(|w| unsafe { w.def().bits(def) });
 
-        // Disable all events interrupts
+        // Configure auto-acquire on 'transfer end' event.
+        if config.auto_acquire {
+            r.shorts.write(|w| w.end_acquire().bit(true));
+        }
+
+        // Disable all events interrupts.
         r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
 
         irq.set_handler(Self::on_interrupt);
@@ -245,11 +246,11 @@ impl<'d, T: Instance> Spis<'d, T> {
         r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
         r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
 
-        // Reset and enable the end event
+        // Reset and enable the end event.
         r.events_end.reset();
         r.intenset.write(|w| w.end().set());
 
-        // Release the semaphore
+        // Release the semaphore.
         r.tasks_release.write(|w| unsafe { w.bits(1) });
 
         Ok(())
@@ -287,12 +288,15 @@ impl<'d, T: Instance> Spis<'d, T> {
         let r = T::regs();
         let s = T::state();
 
+        // Clear status register.
+        r.status.write(|w| w.overflow().clear().overread().clear());
+
         if r.semstat.read().bits() != 1 {
-            // Reset and enable the acquire event
+            // Reset and enable the acquire event.
             r.events_acquired.reset();
             r.intenset.write(|w| w.acquired().set());
 
-            // Requests acquiring the SPIS semaphore
+            // Request acquiring the SPIS semaphore.
             r.tasks_acquire.write(|w| unsafe { w.bits(1) });
 
             // Wait for 'acquire' event.
@@ -341,81 +345,92 @@ impl<'d, T: Instance> Spis<'d, T> {
     }
 
     /// Reads data from the SPI bus without sending anything. Blocks until the buffer has been filled.
-    /// Returns number of bytes read
+    /// Returns number of bytes read.
     pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<usize, Error> {
         self.blocking_inner(data, &[]).map(|n| n.0)
     }
 
     /// Simultaneously sends and receives data. Blocks until the transmission is completed.
     /// If necessary, the write buffer will be copied into RAM (see struct description for detail).
-    /// Returns number of bytes transferred `(n_rx, n_tx)`
+    /// Returns number of bytes transferred `(n_rx, n_tx)`.
     pub fn blocking_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
         self.blocking_inner(read, write)
     }
 
     /// Same as [`blocking_transfer`](Spis::blocking_transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
-    /// Returns number of bytes transferred `(n_rx, n_tx)`
+    /// Returns number of bytes transferred `(n_rx, n_tx)`.
     pub fn blocking_transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
         self.blocking_inner(read, write)
     }
 
     /// Simultaneously sends and receives data.
     /// Places the received data into the same buffer and blocks until the transmission is completed.
-    /// Returns number of bytes transferred
+    /// Returns number of bytes transferred.
     pub fn blocking_transfer_in_place(&mut self, data: &mut [u8]) -> Result<usize, Error> {
         self.blocking_inner_from_ram(data, data).map(|n| n.0)
     }
 
     /// Sends data, discarding any received data. Blocks  until the transmission is completed.
     /// If necessary, the write buffer will be copied into RAM (see struct description for detail).
-    /// Returns number of bytes written
+    /// Returns number of bytes written.
     pub fn blocking_write(&mut self, data: &[u8]) -> Result<usize, Error> {
         self.blocking_inner(&mut [], data).map(|n| n.1)
     }
 
     /// Same as [`blocking_write`](Spis::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
-    /// Returns number of bytes written
+    /// Returns number of bytes written.
     pub fn blocking_write_from_ram(&mut self, data: &[u8]) -> Result<usize, Error> {
         self.blocking_inner(&mut [], data).map(|n| n.1)
     }
 
     /// Reads data from the SPI bus without sending anything.
-    /// Returns number of bytes read
+    /// Returns number of bytes read.
     pub async fn read(&mut self, data: &mut [u8]) -> Result<usize, Error> {
         self.async_inner(data, &[]).await.map(|n| n.0)
     }
 
     /// Simultaneously sends and receives data.
     /// If necessary, the write buffer will be copied into RAM (see struct description for detail).
-    /// Returns number of bytes transferred `(n_rx, n_tx)`
+    /// Returns number of bytes transferred `(n_rx, n_tx)`.
     pub async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
         self.async_inner(read, write).await
     }
 
     /// Same as [`transfer`](Spis::transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
-    /// Returns number of bytes transferred `(n_rx, n_tx)`
+    /// Returns number of bytes transferred `(n_rx, n_tx)`.
     pub async fn transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
         self.async_inner_from_ram(read, write).await
     }
 
     /// Simultaneously sends and receives data. Places the received data into the same buffer.
-    /// Returns number of bytes transferred
+    /// Returns number of bytes transferred.
     pub async fn transfer_in_place(&mut self, data: &mut [u8]) -> Result<usize, Error> {
         self.async_inner_from_ram(data, data).await.map(|n| n.0)
     }
 
     /// Sends data, discarding any received data.
     /// If necessary, the write buffer will be copied into RAM (see struct description for detail).
-    /// Returns number of bytes written
+    /// Returns number of bytes written.
     pub async fn write(&mut self, data: &[u8]) -> Result<usize, Error> {
         self.async_inner(&mut [], data).await.map(|n| n.1)
     }
 
     /// Same as [`write`](Spis::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
-    /// Returns number of bytes written
+    /// Returns number of bytes written.
     pub async fn write_from_ram(&mut self, data: &[u8]) -> Result<usize, Error> {
         self.async_inner_from_ram(&mut [], data).await.map(|n| n.1)
     }
+
+    /// Checks if last transaction overread.
+    pub fn is_overread(&mut self) -> bool {
+        T::regs().status.read().overread().is_present()
+    }
+
+    /// Checks if last transaction overflowed.
+    pub fn is_overflow(&mut self) -> bool {
+        T::regs().status.read().overflow().is_present()
+    }
+
 }
 
 impl<'d, T: Instance> Drop for Spis<'d, T> {
@@ -516,15 +531,15 @@ impl<'d, T: Instance> SetConfig for Spis<'d, T> {
             w
         });
 
-        // Set over-read character
+        // Set over-read character.
         let orc = config.orc;
         r.orc.write(|w| unsafe { w.orc().bits(orc) });
 
-        // Set default character
+        // Set default character.
         let def = config.def;
         r.def.write(|w| unsafe { w.def().bits(def) });
 
-        // Set auto acquire
+        // Configure auto-acquire on 'transfer end' event.
         let auto_acquire = config.auto_acquire;
         r.shorts.write(|w| w.end_acquire().bit(auto_acquire));
     }
diff --git a/examples/nrf/src/bin/spis.rs b/examples/nrf/src/bin/spis.rs
index 181e08404..0fce23d31 100644
--- a/examples/nrf/src/bin/spis.rs
+++ b/examples/nrf/src/bin/spis.rs
@@ -5,7 +5,7 @@
 use defmt::info;
 use embassy_executor::Spawner;
 use embassy_nrf::interrupt;
-use embassy_nrf::spis::{self, Config};
+use embassy_nrf::spis::{Spis, Config};
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
     info!("Running!");
 
     let irq = interrupt::take!(SPIM2_SPIS2_SPI2);
-    let mut spis = spis::Spis::new(p.SPI2, irq, p.P0_31, p.P0_29, p.P0_28, p.P0_30, Config::default());
+    let mut spis = Spis::new(p.SPI2, irq, p.P0_31, p.P0_29, p.P0_28, p.P0_30, Config::default());
 
     loop {
         let mut buf = [0_u8; 64];

From 207fa195512c9e6604a1dec80ec055b06b9b49dd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Alse=CC=81r?= <henrik.alser@me.com>
Date: Sat, 5 Nov 2022 01:34:52 +0100
Subject: [PATCH 04/14] Acquire semaphore on blocking

---
 embassy-nrf/src/spis.rs | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 71106b7df..22c13557a 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -257,9 +257,19 @@ impl<'d, T: Instance> Spis<'d, T> {
     }
 
     fn blocking_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(usize, usize), Error> {
-        self.prepare(rx, tx)?;
+        compiler_fence(Ordering::SeqCst);
         let r = T::regs();
 
+        // Acquire semaphore.
+        if r.semstat.read().bits() != 1 {
+            r.events_acquired.reset();
+            r.tasks_acquire.write(|w| unsafe { w.bits(1) });
+            // Wait until CPU has acquired the semaphore.
+            while r.semstat.read().bits() != 1 {}
+        }
+
+        self.prepare(rx, tx)?;
+
         // Wait for 'end' event.
         while r.events_end.read().bits() == 0 {}
 
@@ -291,6 +301,7 @@ impl<'d, T: Instance> Spis<'d, T> {
         // Clear status register.
         r.status.write(|w| w.overflow().clear().overread().clear());
 
+        // Acquire semaphore.
         if r.semstat.read().bits() != 1 {
             // Reset and enable the acquire event.
             r.events_acquired.reset();
@@ -299,10 +310,10 @@ impl<'d, T: Instance> Spis<'d, T> {
             // Request acquiring the SPIS semaphore.
             r.tasks_acquire.write(|w| unsafe { w.bits(1) });
 
-            // Wait for 'acquire' event.
+            // Wait until CPU has acquired the semaphore.
             poll_fn(|cx| {
                 s.acquire_waker.register(cx.waker());
-                if r.events_acquired.read().bits() != 0 {
+                if r.semstat.read().bits() == 1 {
                     return Poll::Ready(());
                 }
                 Poll::Pending

From aecfce1159480610586bc60cb90af712fae782c6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Alse=CC=81r?= <henrik.alser@me.com>
Date: Sat, 5 Nov 2022 01:36:29 +0100
Subject: [PATCH 05/14] rustfmt

---
 embassy-nrf/src/spis.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 22c13557a..3f77c61d1 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -441,7 +441,6 @@ impl<'d, T: Instance> Spis<'d, T> {
     pub fn is_overflow(&mut self) -> bool {
         T::regs().status.read().overflow().is_present()
     }
-
 }
 
 impl<'d, T: Instance> Drop for Spis<'d, T> {

From af34fc4ccc110bf37165f2b9655585ba3a33889a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Alse=CC=81r?= <henrik.alser@me.com>
Date: Sat, 5 Nov 2022 01:40:20 +0100
Subject: [PATCH 06/14] rustfmt

---
 examples/nrf/src/bin/spis.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/nrf/src/bin/spis.rs b/examples/nrf/src/bin/spis.rs
index 0fce23d31..dade5fcbd 100644
--- a/examples/nrf/src/bin/spis.rs
+++ b/examples/nrf/src/bin/spis.rs
@@ -5,7 +5,7 @@
 use defmt::info;
 use embassy_executor::Spawner;
 use embassy_nrf::interrupt;
-use embassy_nrf::spis::{Spis, Config};
+use embassy_nrf::spis::{Config, Spis};
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]

From dca11095e2f41d50dbc96d48474a64d9198728c4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Als=C3=A9r?= <henrik.alser@ucsmindbite.se>
Date: Sun, 13 Nov 2022 01:49:55 +0100
Subject: [PATCH 07/14] Disable UARTE in embassy-nrf::init

---
 embassy-nrf/src/lib.rs       |  6 ++++++
 embassy-nrf/src/spis.rs      | 39 +++++++++++-------------------------
 examples/nrf/src/bin/spis.rs |  8 +++++---
 3 files changed, 23 insertions(+), 30 deletions(-)

diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 587e19be5..67b254989 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -268,5 +268,11 @@ pub fn init(config: config::Config) -> Peripherals {
     #[cfg(feature = "_time-driver")]
     time_driver::init(config.time_interrupt_priority);
 
+    // Disable UARTE (enabled by default for some reason)
+    unsafe {
+        (*pac::UARTE0::ptr()).enable.write(|w| w.enable().disabled());
+        (*pac::UARTE1::ptr()).enable.write(|w| w.enable().disabled());
+    }
+
     peripherals
 }
diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 3f77c61d1..416db2d33 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -1,5 +1,4 @@
 #![macro_use]
-
 use core::future::poll_fn;
 use core::sync::atomic::{compiler_fence, Ordering};
 use core::task::Poll;
@@ -10,7 +9,7 @@ pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MO
 
 use crate::chip::FORCE_COPY_BUFFER_SIZE;
 use crate::gpio::sealed::Pin as _;
-use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
+use crate::gpio::{self, AnyPin, Pin as GpioPin};
 use crate::interrupt::{Interrupt, InterruptExt};
 use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
 use crate::{pac, Peripheral};
@@ -122,41 +121,26 @@ impl<'d, T: Instance> Spis<'d, T> {
         mosi: Option<PeripheralRef<'d, AnyPin>>,
         config: Config,
     ) -> Self {
-        into_ref!(cs, spis, irq);
+        compiler_fence(Ordering::SeqCst);
+
+        into_ref!(spis, irq, cs, sck);
 
         let r = T::regs();
 
         // Configure pins.
         sck.conf().write(|w| w.input().connect().drive().h0h1());
+        r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
         cs.conf().write(|w| w.input().connect().drive().h0h1());
+        r.psel.csn.write(|w| unsafe { w.bits(cs.psel_bits()) });
         if let Some(mosi) = &mosi {
             mosi.conf().write(|w| w.input().connect().drive().h0h1());
+            r.psel.mosi.write(|w| unsafe { w.bits(mosi.psel_bits()) });
         }
         if let Some(miso) = &miso {
             miso.conf().write(|w| w.dir().output().drive().h0h1());
+            r.psel.miso.write(|w| unsafe { w.bits(miso.psel_bits()) });
         }
 
-        match config.mode.polarity {
-            Polarity::IdleHigh => {
-                sck.set_high();
-                if let Some(mosi) = &mosi {
-                    mosi.set_high();
-                }
-            }
-            Polarity::IdleLow => {
-                sck.set_low();
-                if let Some(mosi) = &mosi {
-                    mosi.set_low();
-                }
-            }
-        }
-
-        // Select pins.
-        r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
-        r.psel.csn.write(|w| unsafe { w.bits(cs.psel_bits()) });
-        r.psel.mosi.write(|w| unsafe { w.bits(mosi.psel_bits()) });
-        r.psel.miso.write(|w| unsafe { w.bits(miso.psel_bits()) });
-
         // Enable SPIS instance.
         r.enable.write(|w| w.enable().enabled());
 
@@ -246,9 +230,8 @@ impl<'d, T: Instance> Spis<'d, T> {
         r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
         r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
 
-        // Reset and enable the end event.
+        // Reset end event.
         r.events_end.reset();
-        r.intenset.write(|w| w.end().set());
 
         // Release the semaphore.
         r.tasks_release.write(|w| unsafe { w.bits(1) });
@@ -316,6 +299,7 @@ impl<'d, T: Instance> Spis<'d, T> {
                 if r.semstat.read().bits() == 1 {
                     return Poll::Ready(());
                 }
+                r.intenset.write(|w| w.acquired().set());
                 Poll::Pending
             })
             .await;
@@ -324,12 +308,13 @@ impl<'d, T: Instance> Spis<'d, T> {
         self.prepare(rx, tx)?;
 
         // Wait for 'end' event.
+        r.intenset.write(|w| w.end().set());
         poll_fn(|cx| {
             s.end_waker.register(cx.waker());
             if r.events_end.read().bits() != 0 {
                 return Poll::Ready(());
             }
-
+            r.intenset.write(|w| w.end().set());
             Poll::Pending
         })
         .await;
diff --git a/examples/nrf/src/bin/spis.rs b/examples/nrf/src/bin/spis.rs
index dade5fcbd..fe3b0c53d 100644
--- a/examples/nrf/src/bin/spis.rs
+++ b/examples/nrf/src/bin/spis.rs
@@ -17,9 +17,11 @@ async fn main(_spawner: Spawner) {
     let mut spis = Spis::new(p.SPI2, irq, p.P0_31, p.P0_29, p.P0_28, p.P0_30, Config::default());
 
     loop {
-        let mut buf = [0_u8; 64];
-        if let Ok(n) = spis.read(&mut buf).await {
-            info!("RX: {:?}", buf[..n]);
+        let mut rx_buf = [0_u8; 64];
+        let tx_buf = [1_u8, 2, 3, 4, 5, 6, 7, 8];
+        if let Ok((n_rx, n_tx)) = spis.transfer(&mut rx_buf, &tx_buf).await {
+            info!("RX: {:?}", rx_buf[..n_rx]);
+            info!("TX: {:?}", tx_buf[..n_tx]);
         }
     }
 }

From 5cfad3f853280069e2927e4838d9b56980e28e34 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Als=C3=A9r?= <henrik.alser@ucsmindbite.se>
Date: Sun, 13 Nov 2022 02:37:23 +0100
Subject: [PATCH 08/14] Feature gate UARTE disable

---
 embassy-nrf/src/lib.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 67b254989..5726f1181 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -269,6 +269,7 @@ pub fn init(config: config::Config) -> Peripherals {
     time_driver::init(config.time_interrupt_priority);
 
     // Disable UARTE (enabled by default for some reason)
+    #[cfg(feature = "_nrf9160")]
     unsafe {
         (*pac::UARTE0::ptr()).enable.write(|w| w.enable().disabled());
         (*pac::UARTE1::ptr()).enable.write(|w| w.enable().disabled());

From 8d2d5a30a519de76c3c74e5e8066ac3bc9aa8f77 Mon Sep 17 00:00:00 2001
From: kalkyl <henrik.alser@me.com>
Date: Mon, 14 Nov 2022 11:39:55 +0100
Subject: [PATCH 09/14] Single waker

---
 embassy-nrf/src/spis.rs | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 416db2d33..f3105007f 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -201,12 +201,12 @@ impl<'d, T: Instance> Spis<'d, T> {
         let s = T::state();
 
         if r.events_end.read().bits() != 0 {
-            s.end_waker.wake();
+            s.waker.wake();
             r.intenclr.write(|w| w.end().clear());
         }
 
         if r.events_acquired.read().bits() != 0 {
-            s.acquire_waker.wake();
+            s.waker.wake();
             r.intenclr.write(|w| w.acquired().clear());
         }
     }
@@ -295,7 +295,7 @@ impl<'d, T: Instance> Spis<'d, T> {
 
             // Wait until CPU has acquired the semaphore.
             poll_fn(|cx| {
-                s.acquire_waker.register(cx.waker());
+                s.waker.register(cx.waker());
                 if r.semstat.read().bits() == 1 {
                     return Poll::Ready(());
                 }
@@ -310,7 +310,7 @@ impl<'d, T: Instance> Spis<'d, T> {
         // Wait for 'end' event.
         r.intenset.write(|w| w.end().set());
         poll_fn(|cx| {
-            s.end_waker.register(cx.waker());
+            s.waker.register(cx.waker());
             if r.events_end.read().bits() != 0 {
                 return Poll::Ready(());
             }
@@ -451,15 +451,13 @@ pub(crate) mod sealed {
     use super::*;
 
     pub struct State {
-        pub end_waker: AtomicWaker,
-        pub acquire_waker: AtomicWaker,
+        pub waker: AtomicWaker,
     }
 
     impl State {
         pub const fn new() -> Self {
             Self {
-                end_waker: AtomicWaker::new(),
-                acquire_waker: AtomicWaker::new(),
+                waker: AtomicWaker::new(),
             }
         }
     }

From 3a1ddd66c64db1c5efd79b89efd76ac97d9eccce Mon Sep 17 00:00:00 2001
From: kalkyl <henrik.alser@me.com>
Date: Mon, 14 Nov 2022 16:18:11 +0100
Subject: [PATCH 10/14] Cleanup interrupts

---
 embassy-nrf/src/spis.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index f3105007f..d382ee0c5 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -297,9 +297,9 @@ impl<'d, T: Instance> Spis<'d, T> {
             poll_fn(|cx| {
                 s.waker.register(cx.waker());
                 if r.semstat.read().bits() == 1 {
+                    r.events_acquired.reset();
                     return Poll::Ready(());
                 }
-                r.intenset.write(|w| w.acquired().set());
                 Poll::Pending
             })
             .await;
@@ -312,9 +312,9 @@ impl<'d, T: Instance> Spis<'d, T> {
         poll_fn(|cx| {
             s.waker.register(cx.waker());
             if r.events_end.read().bits() != 0 {
+                r.events_end.reset();
                 return Poll::Ready(());
             }
-            r.intenset.write(|w| w.end().set());
             Poll::Pending
         })
         .await;

From 0b066b22d11ee07ed64906b27e950ba83368aa49 Mon Sep 17 00:00:00 2001
From: kalkyl <henrik.alser@me.com>
Date: Mon, 14 Nov 2022 16:24:21 +0100
Subject: [PATCH 11/14] Check events_acquired

---
 embassy-nrf/src/spis.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index d382ee0c5..f6f7db3a0 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -296,7 +296,7 @@ impl<'d, T: Instance> Spis<'d, T> {
             // Wait until CPU has acquired the semaphore.
             poll_fn(|cx| {
                 s.waker.register(cx.waker());
-                if r.semstat.read().bits() == 1 {
+                if r.events_acquired.read().bits() == 1 {
                     r.events_acquired.reset();
                     return Poll::Ready(());
                 }

From a6d941fac3d08512f7ef90131d7189ae3aa83bf0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Alse=CC=81r?= <henrik.alser@me.com>
Date: Tue, 22 Nov 2022 00:55:05 +0100
Subject: [PATCH 12/14] Fix txonly/rxonly data pin dir, _from_ram and doc

---
 embassy-nrf/src/spis.rs | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 3f77c61d1..e005f7b92 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -78,7 +78,7 @@ impl<'d, T: Instance> Spis<'d, T> {
         irq: impl Peripheral<P = T::Interrupt> + 'd,
         cs: impl Peripheral<P = impl GpioPin> + 'd,
         sck: impl Peripheral<P = impl GpioPin> + 'd,
-        mosi: impl Peripheral<P = impl GpioPin> + 'd,
+        miso: impl Peripheral<P = impl GpioPin> + 'd,
         config: Config,
     ) -> Self {
         into_ref!(cs, sck, mosi);
@@ -87,8 +87,8 @@ impl<'d, T: Instance> Spis<'d, T> {
             irq,
             cs.map_into(),
             sck.map_into(),
+            Some(miso.map_into()),
             None,
-            Some(mosi.map_into()),
             config,
         )
     }
@@ -98,7 +98,7 @@ impl<'d, T: Instance> Spis<'d, T> {
         irq: impl Peripheral<P = T::Interrupt> + 'd,
         cs: impl Peripheral<P = impl GpioPin> + 'd,
         sck: impl Peripheral<P = impl GpioPin> + 'd,
-        miso: impl Peripheral<P = impl GpioPin> + 'd,
+        mosi: impl Peripheral<P = impl GpioPin> + 'd,
         config: Config,
     ) -> Self {
         into_ref!(cs, sck, miso);
@@ -107,8 +107,8 @@ impl<'d, T: Instance> Spis<'d, T> {
             irq,
             cs.map_into(),
             sck.map_into(),
-            Some(miso.map_into()),
             None,
+            Some(mosi.map_into()),
             config,
         )
     }
@@ -355,7 +355,7 @@ impl<'d, T: Instance> Spis<'d, T> {
         }
     }
 
-    /// Reads data from the SPI bus without sending anything. Blocks until the buffer has been filled.
+    /// Reads data from the SPI bus without sending anything. Blocks until `cs` is deasserted.
     /// Returns number of bytes read.
     pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<usize, Error> {
         self.blocking_inner(data, &[]).map(|n| n.0)
@@ -371,7 +371,7 @@ impl<'d, T: Instance> Spis<'d, T> {
     /// Same as [`blocking_transfer`](Spis::blocking_transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
     /// Returns number of bytes transferred `(n_rx, n_tx)`.
     pub fn blocking_transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
-        self.blocking_inner(read, write)
+        self.blocking_inner_from_ram(read, write)
     }
 
     /// Simultaneously sends and receives data.
@@ -391,7 +391,7 @@ impl<'d, T: Instance> Spis<'d, T> {
     /// Same as [`blocking_write`](Spis::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
     /// Returns number of bytes written.
     pub fn blocking_write_from_ram(&mut self, data: &[u8]) -> Result<usize, Error> {
-        self.blocking_inner(&mut [], data).map(|n| n.1)
+        self.blocking_inner_from_ram(&mut [], data).map(|n| n.1)
     }
 
     /// Reads data from the SPI bus without sending anything.

From e6b9722a31fe0a61d1ef66aa796be89cd95b1ea9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Alse=CC=81r?= <henrik.alser@me.com>
Date: Tue, 22 Nov 2022 01:07:59 +0100
Subject: [PATCH 13/14] Remove nrf9160 UARTE fix

---
 embassy-nrf/src/lib.rs | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 5726f1181..587e19be5 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -268,12 +268,5 @@ pub fn init(config: config::Config) -> Peripherals {
     #[cfg(feature = "_time-driver")]
     time_driver::init(config.time_interrupt_priority);
 
-    // Disable UARTE (enabled by default for some reason)
-    #[cfg(feature = "_nrf9160")]
-    unsafe {
-        (*pac::UARTE0::ptr()).enable.write(|w| w.enable().disabled());
-        (*pac::UARTE1::ptr()).enable.write(|w| w.enable().disabled());
-    }
-
     peripherals
 }

From da9f82f5079ace916b8b5d26fe261cb98fb483fc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Alse=CC=81r?= <henrik.alser@me.com>
Date: Tue, 22 Nov 2022 02:13:03 +0100
Subject: [PATCH 14/14] Fix pin refs

---
 embassy-nrf/src/spis.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 61c5fe998..44af61a19 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -80,7 +80,7 @@ impl<'d, T: Instance> Spis<'d, T> {
         miso: impl Peripheral<P = impl GpioPin> + 'd,
         config: Config,
     ) -> Self {
-        into_ref!(cs, sck, mosi);
+        into_ref!(cs, sck, miso);
         Self::new_inner(
             spis,
             irq,
@@ -100,7 +100,7 @@ impl<'d, T: Instance> Spis<'d, T> {
         mosi: impl Peripheral<P = impl GpioPin> + 'd,
         config: Config,
     ) -> Self {
-        into_ref!(cs, sck, miso);
+        into_ref!(cs, sck, mosi);
         Self::new_inner(
             spis,
             irq,