rp/clocks: fix wrong PLL setup
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1 changed files with 7 additions and 6 deletions
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@ -155,15 +155,16 @@ unsafe fn configure_pll(
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});
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p.fbdiv_int().write(|w| w.set_fbdiv_int(0));
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let ref_mhz = XOSC_MHZ / refdiv;
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p.cs().write(|w| w.set_refdiv(ref_mhz as _));
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let ref_freq = XOSC_MHZ * 1_000_000 / refdiv;
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let fbdiv = vco_freq / (ref_mhz * 1_000_000);
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assert!(fbdiv >= 16 && fbdiv <= 520);
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assert!((post_div1 >= 1 && post_div1 <= 7) && (post_div2 >= 1 && post_div2 <= 7));
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let fbdiv = vco_freq / ref_freq;
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assert!(fbdiv >= 16 && fbdiv <= 320);
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assert!(post_div1 >= 1 && post_div1 <= 7);
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assert!(post_div2 >= 1 && post_div2 <= 7);
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assert!(post_div2 <= post_div1);
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assert!(ref_mhz <= (vco_freq / 16));
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assert!(ref_freq <= (vco_freq / 16));
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p.cs().write(|w| w.set_refdiv(refdiv as _));
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p.fbdiv_int().write(|w| w.set_fbdiv_int(fbdiv as _));
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p.pwr().modify(|w| {
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