diff --git a/.github/workflows/rust.yml b/.github/workflows/rust.yml
index c73c6c7e3..d95c388f3 100644
--- a/.github/workflows/rust.yml
+++ b/.github/workflows/rust.yml
@@ -82,6 +82,8 @@ jobs:
             target: thumbv7em-none-eabi
           - package: examples/stm32l4
             target: thumbv7em-none-eabi
+          - package: examples/stm32h7
+            target: thumbv7em-none-eabi
 
     steps:
       - uses: actions/checkout@v2
diff --git a/examples/stm32h7/Cargo.toml b/examples/stm32h7/Cargo.toml
new file mode 100644
index 000000000..d7288e4c7
--- /dev/null
+++ b/examples/stm32h7/Cargo.toml
@@ -0,0 +1,39 @@
+[package]
+authors = ["Dario Nieuwenhuis <dirbaio@dirbaio.net>"]
+edition = "2018"
+name = "embassy-stm32h7-examples"
+version = "0.1.0"
+resolver = "2"
+
+[features]
+default = [
+    "defmt-default",
+]
+defmt-default = []
+defmt-trace = []
+defmt-debug = []
+defmt-info = []
+defmt-warn = []
+defmt-error = []
+
+[dependencies]
+embassy = { version = "0.1.0", path = "../../embassy", features = ["defmt", "defmt-trace"] }
+embassy-traits = { version = "0.1.0", path = "../../embassy-traits", features = ["defmt"] }
+embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "defmt-trace", "stm32h743zi"]  }
+embassy-extras = {version = "0.1.0", path = "../../embassy-extras" }
+stm32h7 = { version = "0.13", features = ["stm32h743"]}
+stm32h7xx-hal = { version = "0.9.0", features = ["stm32h743"] }
+
+defmt = "0.2.0"
+defmt-rtt = "0.2.0"
+
+cortex-m = "0.7.1"
+cortex-m-rt = "0.6.14"
+embedded-hal = { version = "0.2.4" }
+panic-probe = { version = "0.2.0", features= ["print-defmt"] }
+futures = { version = "0.3.8", default-features = false, features = ["async-await"] }
+rtt-target = { version = "0.3", features = ["cortex-m"] }
+heapless = { version = "0.7.1", default-features = false }
+
+micromath = "2.0.0"
+
diff --git a/examples/stm32h7/memory.x b/examples/stm32h7/memory.x
new file mode 100644
index 000000000..48f58e36b
--- /dev/null
+++ b/examples/stm32h7/memory.x
@@ -0,0 +1,5 @@
+MEMORY
+{
+  FLASH : ORIGIN = 0x08000000, LENGTH = 2048K
+  RAM : ORIGIN = 0x20000000, LENGTH = 128K
+}
diff --git a/examples/stm32h7/src/bin/blinky.rs b/examples/stm32h7/src/bin/blinky.rs
new file mode 100644
index 000000000..c425b7f8e
--- /dev/null
+++ b/examples/stm32h7/src/bin/blinky.rs
@@ -0,0 +1,75 @@
+#![no_std]
+#![no_main]
+#![feature(trait_alias)]
+#![feature(min_type_alias_impl_trait)]
+#![feature(impl_trait_in_bindings)]
+#![feature(type_alias_impl_trait)]
+#![allow(incomplete_features)]
+
+#[path = "../example_common.rs"]
+mod example_common;
+use embassy_stm32::gpio::{Level, Output};
+use embedded_hal::digital::v2::OutputPin;
+use example_common::*;
+
+use cortex_m_rt::entry;
+use stm32h7::stm32h743 as pac;
+
+use stm32h7xx_hal as hal;
+use hal::prelude::*;
+
+#[entry]
+fn main() -> ! {
+    info!("Hello World!");
+
+    let pp = pac::Peripherals::take().unwrap();
+
+    let pwrcfg = pp.PWR.constrain()
+        .freeze();
+
+    let rcc = pp.RCC.constrain();
+
+    let ccdr = rcc
+        .sys_ck(96.mhz())
+        .pclk1(48.mhz())
+        .pclk2(48.mhz())
+        .pclk3(48.mhz())
+        .pclk4(48.mhz())
+        .pll1_q_ck(48.mhz())
+        .freeze(pwrcfg, &pp.SYSCFG);
+
+    let pp = unsafe { pac::Peripherals::steal() };
+
+    pp.DBGMCU.cr.modify(|_, w| {
+        w.dbgsleep_d1().set_bit();
+        w.dbgstby_d1().set_bit();
+        w.dbgstop_d1().set_bit();
+        w.d1dbgcken().set_bit();
+        w
+    });
+
+    pp.RCC.ahb4enr.modify(|_, w| {
+        w.gpioaen().set_bit();
+        w.gpioben().set_bit();
+        w.gpiocen().set_bit();
+        w.gpioden().set_bit();
+        w.gpioeen().set_bit();
+        w.gpiofen().set_bit();
+        w
+    });
+
+    let p = embassy_stm32::init(Default::default());
+
+    let mut led = Output::new(p.PB14, Level::High);
+
+    loop {
+        info!("high");
+        led.set_high().unwrap();
+        cortex_m::asm::delay(10_000_000);
+
+        info!("low");
+        led.set_low().unwrap();
+        cortex_m::asm::delay(10_000_000);
+    }
+
+}
diff --git a/examples/stm32h7/src/bin/dac.rs b/examples/stm32h7/src/bin/dac.rs
new file mode 100644
index 000000000..c6f3de7b6
--- /dev/null
+++ b/examples/stm32h7/src/bin/dac.rs
@@ -0,0 +1,92 @@
+#![no_std]
+#![no_main]
+#![feature(trait_alias)]
+#![feature(min_type_alias_impl_trait)]
+#![feature(impl_trait_in_bindings)]
+#![feature(type_alias_impl_trait)]
+
+#[path = "../example_common.rs"]
+mod example_common;
+
+use embassy_stm32::gpio::{Level, Output, Input, Pull, NoPin};
+use embedded_hal::digital::v2::{OutputPin, InputPin};
+use example_common::*;
+
+use cortex_m_rt::entry;
+use stm32h7::stm32h743 as pac;
+use embassy_stm32::spi::{Spi, MODE_0, ByteOrder, Config};
+use embassy_stm32::time::Hertz;
+use embedded_hal::blocking::spi::Transfer;
+use stm32h7xx_hal::{rcc, prelude::*};
+use embassy_stm32::dac::{Dac, Value, Channel};
+
+#[entry]
+fn main() -> ! {
+    info!("Hello World, dude!");
+
+    let pp = pac::Peripherals::take().unwrap();
+
+    let pwrcfg = pp.PWR.constrain()
+        .freeze();
+
+    let rcc = pp.RCC.constrain();
+
+    let ccdr = rcc
+        .sys_ck(96.mhz())
+        .pclk1(48.mhz())
+        .pclk2(48.mhz())
+        .pclk3(48.mhz())
+        .pclk4(48.mhz())
+        .pll1_q_ck(48.mhz())
+        .freeze(pwrcfg, &pp.SYSCFG);
+
+    let pp = unsafe { pac::Peripherals::steal() };
+
+    pp.DBGMCU.cr.modify(|_, w| {
+        w.dbgsleep_d1().set_bit();
+        w.dbgstby_d1().set_bit();
+        w.dbgstop_d1().set_bit();
+        w.d1dbgcken().set_bit();
+        w
+    });
+
+    pp.RCC.apb1lenr.modify(|_, w|{
+        w.dac12en().set_bit();
+        w
+    });
+
+    pp.RCC.ahb4enr.modify(|_, w| {
+        w.gpioaen().set_bit();
+        w.gpioben().set_bit();
+        w.gpiocen().set_bit();
+        w.gpioden().set_bit();
+        w.gpioeen().set_bit();
+        w.gpiofen().set_bit();
+        w
+    });
+
+    let p = embassy_stm32::init(Default::default());
+
+    let mut dac = Dac::new(p.DAC1, p.PA4, NoPin);
+
+    loop {
+        for v in 0..=255 {
+            dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v)));
+            dac.trigger( Channel::Ch1 );
+        }
+    }
+}
+
+use micromath::F32Ext;
+
+fn to_sine_wave(v: u8) -> u8 {
+    if v >= 128 {
+        // top half
+        let r = 3.14 * ( (v-128) as f32/ 128.0) ;
+        (r.sin() * 128.0 + 127.0) as u8
+    } else {
+        // bottom half
+        let r = 3.14 + 3.14 * (v as f32/ 128.0);
+        (r.sin() * 128.0 + 127.0) as u8
+    }
+}
diff --git a/examples/stm32h7/src/example_common.rs b/examples/stm32h7/src/example_common.rs
new file mode 100644
index 000000000..54d633837
--- /dev/null
+++ b/examples/stm32h7/src/example_common.rs
@@ -0,0 +1,17 @@
+#![macro_use]
+
+use defmt_rtt as _; // global logger
+use panic_probe as _;
+
+pub use defmt::*;
+
+use core::sync::atomic::{AtomicUsize, Ordering};
+
+defmt::timestamp! {"{=u64}", {
+        static COUNT: AtomicUsize = AtomicUsize::new(0);
+        // NOTE(no-CAS) `timestamps` runs with interrupts disabled
+        let n = COUNT.load(Ordering::Relaxed);
+        COUNT.store(n + 1, Ordering::Relaxed);
+        n as u64
+    }
+}
diff --git a/stm32-data b/stm32-data
index 4bb1b178c..f07c793bb 160000
--- a/stm32-data
+++ b/stm32-data
@@ -1 +1 @@
-Subproject commit 4bb1b178cd1c555cfedaea31ad0be3c6a7b99563
+Subproject commit f07c793bbe81b01b2f3668177648f024ec1c8fb1