Merge pull request #2520 from Ecco/stm32wba-rcc-v3
Migrate STM32WBA to RCCv3
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
a099084bff
1 changed files with 104 additions and 91 deletions
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@ -1,5 +1,8 @@
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use stm32_metapac::rcc::vals::{Pllsrc, Sw};
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pub use crate::pac::pwr::vals::Vos as VoltageScale;
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use crate::pac::rcc::regs::Cfgr1;
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pub use crate::pac::rcc::vals::{
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Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as ClockSrc,
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};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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@ -9,82 +12,108 @@ pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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// HSE speed
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pub const HSE_FREQ: Hertz = Hertz(32_000_000);
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pub use crate::pac::pwr::vals::Vos as VoltageScale;
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pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
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#[derive(Copy, Clone)]
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pub enum ClockSrc {
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HSE,
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HSI,
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}
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#[derive(Clone, Copy, Debug)]
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pub enum PllSource {
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HSE,
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HSI,
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}
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impl Into<Pllsrc> for PllSource {
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fn into(self) -> Pllsrc {
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match self {
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PllSource::HSE => Pllsrc::HSE,
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PllSource::HSI => Pllsrc::HSI,
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}
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}
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}
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impl Into<Sw> for ClockSrc {
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fn into(self) -> Sw {
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match self {
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ClockSrc::HSE => Sw::HSE,
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ClockSrc::HSI => Sw::HSI,
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}
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub struct Hse {
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pub prescaler: HsePrescaler,
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}
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/// Clocks configuration
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pub struct Config {
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// base clock sources
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pub hsi: bool,
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pub hse: Option<Hse>,
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// sysclk, buses.
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pub mux: ClockSrc,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub apb7_pre: APBPrescaler,
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// low speed LSI/LSE/RTC
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pub ls: super::LsConfig,
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pub adc_clock_source: AdcClockSource,
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pub voltage_scale: VoltageScale,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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#[inline]
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fn default() -> Config {
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Config {
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hse: None,
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hsi: true,
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mux: ClockSrc::HSI,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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apb7_pre: APBPrescaler::DIV1,
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ls: Default::default(),
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adc_clock_source: AdcClockSource::HCLK1,
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voltage_scale: VoltageScale::RANGE2,
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}
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}
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}
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fn hsi_enable() {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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}
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pub(crate) unsafe fn init(config: Config) {
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// Switch to HSI to prevent problems with PLL configuration.
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if !RCC.cr().read().hsion() {
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hsi_enable()
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}
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if RCC.cfgr1().read().sws() != ClockSrc::HSI {
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// Set HSI as a clock source, reset prescalers.
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RCC.cfgr1().write_value(Cfgr1::default());
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// Wait for clock switch status bits to change.
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while RCC.cfgr1().read().sws() != ClockSrc::HSI {}
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}
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// Set voltage scale
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crate::pac::PWR.vosr().write(|w| w.set_vos(config.voltage_scale));
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while !crate::pac::PWR.vosr().read().vosrdy() {}
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let rtc = config.ls.init();
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let hsi = config.hsi.then(|| {
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hsi_enable();
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HSI_FREQ
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});
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let hse = config.hse.map(|hse| {
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RCC.cr().write(|w| {
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w.set_hseon(true);
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w.set_hsepre(hse.prescaler);
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});
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while !RCC.cr().read().hserdy() {}
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HSE_FREQ
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});
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let sys_clk = match config.mux {
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ClockSrc::HSE => {
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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HSE_FREQ
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}
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ClockSrc::HSI => {
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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HSI_FREQ
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}
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ClockSrc::HSE => hse.unwrap(),
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ClockSrc::HSI => hsi.unwrap(),
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ClockSrc::_RESERVED_1 => unreachable!(),
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ClockSrc::PLL1_R => todo!(),
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};
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// TODO make configurable
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let power_vos = VoltageScale::RANGE1;
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assert!(sys_clk.0 <= 100_000_000);
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// states and programming delay
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let wait_states = match power_vos {
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let hclk1 = sys_clk / config.ahb_pre;
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let hclk2 = hclk1;
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let hclk4 = hclk1;
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// TODO: hclk5
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let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk1, config.apb1_pre);
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let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk1, config.apb2_pre);
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let (pclk7, _) = super::util::calc_pclk(hclk1, config.apb7_pre);
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// Set flash wait states
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let flash_latency = match config.voltage_scale {
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VoltageScale::RANGE1 => match sys_clk.0 {
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..=32_000_000 => 0,
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..=64_000_000 => 1,
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@ -99,13 +128,24 @@ pub(crate) unsafe fn init(config: Config) {
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},
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};
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FLASH.acr().modify(|w| {
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w.set_latency(wait_states);
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});
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FLASH.acr().modify(|w| w.set_latency(flash_latency));
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while FLASH.acr().read().latency() != flash_latency {}
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// Set sram wait states
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let _sram_latency = match config.voltage_scale {
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VoltageScale::RANGE1 => 0,
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VoltageScale::RANGE2 => match sys_clk.0 {
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..=12_000_000 => 0,
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..=16_000_000 => 1,
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_ => 2,
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},
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};
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// TODO: Set the SRAM wait states
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RCC.cfgr1().modify(|w| {
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w.set_sw(config.mux.into());
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w.set_sw(config.mux);
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});
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while RCC.cfgr1().read().sws() != config.mux {}
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RCC.cfgr2().modify(|w| {
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w.set_hpre(config.ahb_pre);
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@ -113,45 +153,18 @@ pub(crate) unsafe fn init(config: Config) {
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w.set_ppre2(config.apb2_pre);
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});
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RCC.cfgr3().modify(|w| {
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w.set_ppre7(config.apb7_pre);
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});
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let ahb_freq = sys_clk / config.ahb_pre;
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let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let freq = ahb_freq / pre;
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(freq, freq * 2u32)
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}
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};
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let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let freq = ahb_freq / pre;
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(freq, freq * 2u32)
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}
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};
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let (apb7_freq, _apb7_tim_freq) = match config.apb7_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let freq = ahb_freq / pre;
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(freq, freq * 2u32)
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}
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};
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let rtc = config.ls.init();
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RCC.ccipr3().modify(|w| w.set_adcsel(config.adc_clock_source));
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set_freqs(Clocks {
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sys: sys_clk,
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hclk1: ahb_freq,
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hclk2: ahb_freq,
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hclk4: ahb_freq,
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pclk1: apb1_freq,
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pclk2: apb2_freq,
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pclk7: apb7_freq,
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pclk1_tim: apb1_tim_freq,
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pclk2_tim: apb2_tim_freq,
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hclk1,
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hclk2,
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hclk4,
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pclk1,
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pclk2,
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pclk7,
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pclk1_tim,
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pclk2_tim,
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rtc,
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});
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}
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