Merge branch 'adc_h5' into add-pll1_p_mul_2-clock
This commit is contained in:
commit
a308b9ac2f
4 changed files with 93 additions and 46 deletions
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@ -10,7 +10,7 @@
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#[cfg_attr(adc_v1, path = "v1.rs")]
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#[cfg_attr(adc_l0, path = "v1.rs")]
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#[cfg_attr(adc_v2, path = "v2.rs")]
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#[cfg_attr(any(adc_v3, adc_g0), path = "v3.rs")]
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#[cfg_attr(any(adc_v3, adc_g0, adc_h5), path = "v3.rs")]
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#[cfg_attr(adc_v4, path = "v4.rs")]
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mod _version;
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@ -79,10 +79,10 @@ pub(crate) mod sealed {
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}
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/// ADC instance.
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#[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0)))]
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#[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0, adc_h5)))]
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pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {}
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/// ADC instance.
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#[cfg(any(adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0))]
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#[cfg(any(adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0, adc_h5))]
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pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {}
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/// ADC pin.
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@ -1,6 +1,6 @@
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/// ADC resolution
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#[allow(missing_docs)]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
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#[derive(Clone, Copy, Debug, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Resolution {
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@ -25,7 +25,7 @@ pub enum Resolution {
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impl Default for Resolution {
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fn default() -> Self {
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
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{
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Self::TwelveBit
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}
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@ -46,7 +46,7 @@ impl From<Resolution> for crate::pac::adc::vals::Res {
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Resolution::TwelveBit => crate::pac::adc::vals::Res::TWELVEBIT,
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Resolution::TenBit => crate::pac::adc::vals::Res::TENBIT,
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Resolution::EightBit => crate::pac::adc::vals::Res::EIGHTBIT,
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
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Resolution::SixBit => crate::pac::adc::vals::Res::SIXBIT,
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}
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}
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@ -65,7 +65,7 @@ impl Resolution {
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Resolution::TwelveBit => (1 << 12) - 1,
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Resolution::TenBit => (1 << 10) - 1,
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Resolution::EightBit => (1 << 8) - 1,
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
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Resolution::SixBit => (1 << 6) - 1,
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}
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}
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@ -67,7 +67,7 @@ impl_sample_time!(
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)
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);
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#[cfg(adc_v3)]
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#[cfg(any(adc_v3, adc_h5))]
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impl_sample_time!(
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"2.5",
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Cycles2_5,
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@ -1,3 +1,4 @@
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use cfg_if::cfg_if;
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use embassy_hal_internal::into_ref;
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use embedded_hal_02::blocking::delay::DelayUs;
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@ -13,10 +14,15 @@ pub struct VrefInt;
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impl<T: Instance> AdcPin<T> for VrefInt {}
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impl<T: Instance> super::sealed::AdcPin<T> for VrefInt {
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fn channel(&self) -> u8 {
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#[cfg(not(adc_g0))]
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let val = 0;
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#[cfg(adc_g0)]
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let val = 13;
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cfg_if! {
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if #[cfg(adc_g0)] {
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let val = 13;
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} else if #[cfg(adc_h5)] {
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let val = 17;
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} else {
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let val = 0;
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}
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}
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val
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}
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}
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@ -25,10 +31,15 @@ pub struct Temperature;
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impl<T: Instance> AdcPin<T> for Temperature {}
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impl<T: Instance> super::sealed::AdcPin<T> for Temperature {
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fn channel(&self) -> u8 {
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#[cfg(not(adc_g0))]
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let val = 17;
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#[cfg(adc_g0)]
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let val = 12;
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cfg_if! {
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if #[cfg(adc_g0)] {
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let val = 12;
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} else if #[cfg(adc_h5)] {
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let val = 16;
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} else {
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let val = 17;
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}
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}
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val
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}
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}
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@ -37,14 +48,31 @@ pub struct Vbat;
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impl<T: Instance> AdcPin<T> for Vbat {}
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impl<T: Instance> super::sealed::AdcPin<T> for Vbat {
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fn channel(&self) -> u8 {
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#[cfg(not(adc_g0))]
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let val = 18;
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#[cfg(adc_g0)]
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let val = 14;
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cfg_if! {
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if #[cfg(adc_g0)] {
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let val = 14;
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} else if #[cfg(adc_h5)] {
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let val = 2;
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} else {
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let val = 18;
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}
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}
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val
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}
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}
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cfg_if! {
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if #[cfg(adc_h5)] {
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pub struct VddCore;
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impl<T: Instance> AdcPin<T> for VddCore {}
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impl<T: Instance> super::sealed::AdcPin<T> for VddCore {
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fn channel(&self) -> u8 {
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6
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}
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}
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}
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}
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impl<'d, T: Instance> Adc<'d, T> {
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pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
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into_ref!(adc);
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@ -98,27 +126,41 @@ impl<'d, T: Instance> Adc<'d, T> {
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}
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pub fn enable_temperature(&self) -> Temperature {
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#[cfg(not(adc_g0))]
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T::common_regs().ccr().modify(|reg| {
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reg.set_ch17sel(true);
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});
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#[cfg(adc_g0)]
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T::regs().ccr().modify(|reg| {
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reg.set_tsen(true);
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});
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cfg_if! {
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if #[cfg(adc_g0)] {
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T::regs().ccr().modify(|reg| {
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reg.set_tsen(true);
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});
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} else if #[cfg(adc_h5)] {
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T::common_regs().ccr().modify(|reg| {
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reg.set_tsen(true);
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});
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} else {
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T::common_regs().ccr().modify(|reg| {
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reg.set_ch17sel(true);
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});
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}
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}
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Temperature {}
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}
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pub fn enable_vbat(&self) -> Vbat {
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#[cfg(not(adc_g0))]
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T::common_regs().ccr().modify(|reg| {
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reg.set_ch18sel(true);
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});
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#[cfg(adc_g0)]
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T::regs().ccr().modify(|reg| {
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reg.set_vbaten(true);
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});
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cfg_if! {
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if #[cfg(adc_g0)] {
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T::regs().ccr().modify(|reg| {
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reg.set_vbaten(true);
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});
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} else if #[cfg(adc_h5)] {
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T::common_regs().ccr().modify(|reg| {
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reg.set_vbaten(true);
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});
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} else {
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T::common_regs().ccr().modify(|reg| {
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reg.set_ch18sel(true);
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});
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}
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}
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Vbat {}
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}
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@ -205,16 +247,21 @@ impl<'d, T: Instance> Adc<'d, T> {
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val
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}
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#[cfg(adc_g0)]
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fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
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T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
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}
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#[cfg(not(adc_g0))]
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fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
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let sample_time = sample_time.into();
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T::regs()
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.smpr(ch as usize / 10)
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.modify(|reg| reg.set_smp(ch as usize % 10, sample_time));
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cfg_if! {
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if #[cfg(adc_g0)] {
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T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
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} else if #[cfg(adc_h5)] {
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match _ch {
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0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
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_ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
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}
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} else {
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let sample_time = sample_time.into();
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T::regs()
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.smpr(ch as usize / 10)
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.modify(|reg| reg.set_smp(ch as usize % 10, sample_time));
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}
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}
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}
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}
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