usb: make ControlPipe accept, reject async.
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883e28a0fb
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3 changed files with 24 additions and 12 deletions
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@ -616,6 +616,8 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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type SetupFuture<'a> = impl Future<Output = [u8;8]> + 'a where Self: 'a;
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type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a;
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type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a;
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type AcceptFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
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type RejectFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
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fn max_packet_size(&self) -> usize {
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usize::from(self.max_packet_size)
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@ -740,17 +742,21 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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}
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}
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fn accept(&mut self) {
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fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a> {
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async move {
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let regs = T::regs();
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regs.tasks_ep0status
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.write(|w| w.tasks_ep0status().bit(true));
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}
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}
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fn reject(&mut self) {
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fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a> {
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async move {
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let regs = T::regs();
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regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true));
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}
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}
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}
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fn dma_start() {
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compiler_fence(Ordering::Release);
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@ -142,6 +142,12 @@ pub trait ControlPipe {
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where
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Self: 'a;
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type DataInFuture<'a>: Future<Output = Result<(), EndpointError>> + 'a
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where
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Self: 'a;
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type AcceptFuture<'a>: Future<Output = ()> + 'a
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where
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Self: 'a;
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type RejectFuture<'a>: Future<Output = ()> + 'a
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where
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Self: 'a;
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@ -171,12 +177,12 @@ pub trait ControlPipe {
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/// Accepts a control request.
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///
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/// Causes the STATUS packet for the current request to be ACKed.
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fn accept(&mut self);
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fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a>;
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/// Rejects a control request.
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///
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/// Sets a STALL condition on the pipe to indicate an error.
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fn reject(&mut self);
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fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a>;
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}
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pub trait EndpointIn: Endpoint {
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@ -306,7 +306,7 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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}
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}
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}
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InResponse::Rejected => self.control.reject(),
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InResponse::Rejected => self.control.reject().await,
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}
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}
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@ -337,8 +337,8 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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trace!(" control out data: {:02x?}", data);
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match self.inner.handle_control_out(req, data) {
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OutResponse::Accepted => self.control.accept(),
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OutResponse::Rejected => self.control.reject(),
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OutResponse::Accepted => self.control.accept().await,
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OutResponse::Rejected => self.control.reject().await,
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}
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}
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}
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