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Change all logging level to debug.

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This commit is contained in:
Dario Nieuwenhuis 2023-05-08 20:27:44 +02:00
parent d3d424dad3
commit a7dee5b65c
2 changed files with 18 additions and 18 deletions
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14
src/control.rs
View file

@ -35,7 +35,7 @@ impl<'a> Control<'a> {
pub async fn init(&mut self, clm: &[u8]) { pub async fn init(&mut self, clm: &[u8]) {
const CHUNK_SIZE: usize = 1024; const CHUNK_SIZE: usize = 1024;
info!("Downloading CLM..."); debug!("Downloading CLM...");
let mut offs = 0; let mut offs = 0;
for chunk in clm.chunks(CHUNK_SIZE) { for chunk in clm.chunks(CHUNK_SIZE) {
@ -65,7 +65,7 @@ impl<'a> Control<'a> {
// check clmload ok // check clmload ok
assert_eq!(self.get_iovar_u32("clmload_status").await, 0); assert_eq!(self.get_iovar_u32("clmload_status").await, 0);
info!("Configuring misc stuff..."); debug!("Configuring misc stuff...");
// Disable tx gloming which transfers multiple packets in one request. // Disable tx gloming which transfers multiple packets in one request.
// 'glom' is short for "conglomerate" which means "gather together into // 'glom' is short for "conglomerate" which means "gather together into
@ -76,7 +76,7 @@ impl<'a> Control<'a> {
// read MAC addr. // read MAC addr.
let mut mac_addr = [0; 6]; let mut mac_addr = [0; 6];
assert_eq!(self.get_iovar("cur_etheraddr", &mut mac_addr).await, 6); assert_eq!(self.get_iovar("cur_etheraddr", &mut mac_addr).await, 6);
info!("mac addr: {:02x}", Bytes(&mac_addr)); debug!("mac addr: {:02x}", Bytes(&mac_addr));
let country = countries::WORLD_WIDE_XX; let country = countries::WORLD_WIDE_XX;
let country_info = CountryInfo { let country_info = CountryInfo {
@ -135,7 +135,7 @@ impl<'a> Control<'a> {
self.state_ch.set_ethernet_address(mac_addr); self.state_ch.set_ethernet_address(mac_addr);
info!("INIT DONE"); debug!("INIT DONE");
} }
pub async fn set_power_management(&mut self, mode: PowerManagementMode) { pub async fn set_power_management(&mut self, mode: PowerManagementMode) {
@ -226,7 +226,7 @@ impl<'a> Control<'a> {
if status == EStatus::SUCCESS { if status == EStatus::SUCCESS {
// successful join // successful join
self.state_ch.set_link_state(LinkState::Up); self.state_ch.set_link_state(LinkState::Up);
info!("JOINED"); debug!("JOINED");
Ok(()) Ok(())
} else { } else {
warn!("JOIN failed with status={} auth={}", status, auth_status); warn!("JOIN failed with status={} auth={}", status, auth_status);
@ -330,7 +330,7 @@ impl<'a> Control<'a> {
} }
async fn set_iovar_v<const BUFSIZE: usize>(&mut self, name: &str, val: &[u8]) { async fn set_iovar_v<const BUFSIZE: usize>(&mut self, name: &str, val: &[u8]) {
info!("set {} = {:02x}", name, Bytes(val)); debug!("set {} = {:02x}", name, Bytes(val));
let mut buf = [0; BUFSIZE]; let mut buf = [0; BUFSIZE];
buf[..name.len()].copy_from_slice(name.as_bytes()); buf[..name.len()].copy_from_slice(name.as_bytes());
@ -344,7 +344,7 @@ impl<'a> Control<'a> {
// TODO this is not really working, it always returns all zeros. // TODO this is not really working, it always returns all zeros.
async fn get_iovar(&mut self, name: &str, res: &mut [u8]) -> usize { async fn get_iovar(&mut self, name: &str, res: &mut [u8]) -> usize {
info!("get {}", name); debug!("get {}", name);
let mut buf = [0; 64]; let mut buf = [0; 64];
buf[..name.len()].copy_from_slice(name.as_bytes()); buf[..name.len()].copy_from_slice(name.as_bytes());

22
src/runner.rs
View file

@ -80,12 +80,12 @@ where
self.bus self.bus
.write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, BACKPLANE_ALP_AVAIL_REQ) .write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, BACKPLANE_ALP_AVAIL_REQ)
.await; .await;
info!("waiting for clock..."); debug!("waiting for clock...");
while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & BACKPLANE_ALP_AVAIL == 0 {} while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & BACKPLANE_ALP_AVAIL == 0 {}
info!("clock ok"); debug!("clock ok");
let chip_id = self.bus.bp_read16(0x1800_0000).await; let chip_id = self.bus.bp_read16(0x1800_0000).await;
info!("chip ID: {}", chip_id); debug!("chip ID: {}", chip_id);
// Upload firmware. // Upload firmware.
self.core_disable(Core::WLAN).await; self.core_disable(Core::WLAN).await;
@ -95,10 +95,10 @@ where
let ram_addr = CHIP.atcm_ram_base_address; let ram_addr = CHIP.atcm_ram_base_address;
info!("loading fw"); debug!("loading fw");
self.bus.bp_write(ram_addr, firmware).await; self.bus.bp_write(ram_addr, firmware).await;
info!("loading nvram"); debug!("loading nvram");
// Round up to 4 bytes. // Round up to 4 bytes.
let nvram_len = (NVRAM.len() + 3) / 4 * 4; let nvram_len = (NVRAM.len() + 3) / 4 * 4;
self.bus self.bus
@ -112,7 +112,7 @@ where
.await; .await;
// Start core! // Start core!
info!("starting up core..."); debug!("starting up core...");
self.core_reset(Core::WLAN).await; self.core_reset(Core::WLAN).await;
assert!(self.core_is_up(Core::WLAN).await); assert!(self.core_is_up(Core::WLAN).await);
@ -132,7 +132,7 @@ where
.await; .await;
// wait for wifi startup // wait for wifi startup
info!("waiting for wifi init..."); debug!("waiting for wifi init...");
while self.bus.read32(FUNC_BUS, REG_BUS_STATUS).await & STATUS_F2_RX_READY == 0 {} while self.bus.read32(FUNC_BUS, REG_BUS_STATUS).await & STATUS_F2_RX_READY == 0 {}
// Some random configs related to sleep. // Some random configs related to sleep.
@ -158,14 +158,14 @@ where
// start HT clock // start HT clock
//self.bus.write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, 0x10).await; //self.bus.write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, 0x10).await;
//info!("waiting for HT clock..."); //debug!("waiting for HT clock...");
//while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & 0x80 == 0 {} //while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & 0x80 == 0 {}
//info!("clock ok"); //debug!("clock ok");
#[cfg(feature = "firmware-logs")] #[cfg(feature = "firmware-logs")]
self.log_init().await; self.log_init().await;
info!("init done "); debug!("wifi init done");
} }
#[cfg(feature = "firmware-logs")] #[cfg(feature = "firmware-logs")]
@ -174,7 +174,7 @@ where
let addr = CHIP.atcm_ram_base_address + CHIP.chip_ram_size - 4 - CHIP.socram_srmem_size; let addr = CHIP.atcm_ram_base_address + CHIP.chip_ram_size - 4 - CHIP.socram_srmem_size;
let shared_addr = self.bus.bp_read32(addr).await; let shared_addr = self.bus.bp_read32(addr).await;
info!("shared_addr {:08x}", shared_addr); debug!("shared_addr {:08x}", shared_addr);
let mut shared = [0; SharedMemData::SIZE]; let mut shared = [0; SharedMemData::SIZE];
self.bus.bp_read(shared_addr, &mut shared).await; self.bus.bp_read(shared_addr, &mut shared).await;