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Merge #1432

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1432: Support PLLXTPRE switch. r=Dirbaio a=MrOscarLoplate

See figure 2. Clock tree page 12 DS5319 Rev 18
https://www.st.com/resource/en/datasheet/stm32f103cb.pdf

Co-authored-by: Marco Pastrello <marco.pastrello@gmail.com>
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bors[bot] 2023-05-05 17:09:26 +00:00 committed by GitHub
commit a9c7263ba0
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1 changed files with 7 additions and 1 deletions
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8
embassy-stm32/src/rcc/f1.rs
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@ -24,10 +24,13 @@ pub struct Config {
pub pclk1: Option<Hertz>, pub pclk1: Option<Hertz>,
pub pclk2: Option<Hertz>, pub pclk2: Option<Hertz>,
pub adcclk: Option<Hertz>, pub adcclk: Option<Hertz>,
pub pllxtpre: bool,
} }
pub(crate) unsafe fn init(config: Config) { pub(crate) unsafe fn init(config: Config) {
let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0 / 2); let pllxtpre_div = if config.pllxtpre { 2 } else { 1 };
let pllsrcclk = config.hse.map(|hse| hse.0 / pllxtpre_div).unwrap_or(HSI_FREQ.0 / 2);
let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk); let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
let pllmul = sysclk / pllsrcclk; let pllmul = sysclk / pllsrcclk;
@ -143,6 +146,9 @@ pub(crate) unsafe fn init(config: Config) {
} }
if let Some(pllmul_bits) = pllmul_bits { if let Some(pllmul_bits) = pllmul_bits {
let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 };
RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(pllctpre_flag)));
// enable PLL and wait for it to be ready // enable PLL and wait for it to be ready
RCC.cfgr().modify(|w| { RCC.cfgr().modify(|w| {
w.set_pllmul(Pllmul(pllmul_bits)); w.set_pllmul(Pllmul(pllmul_bits));