Merge pull request #1561 from petegibson/stm32-buffereduart-int-flags-fix
Ensure idle & ove flags are cleared in BufferedUart ISR on STM32
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commit
adaed307b4
1 changed files with 22 additions and 16 deletions
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@ -21,9 +21,16 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
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// RX
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unsafe {
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let sr = sr(r).read();
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// On v1 & v2, reading DR clears the rxne, error and idle interrupt
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// flags. Keep this close to the SR read to reduce the chance of a
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// flag being set in-between.
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let dr = if sr.rxne() || cfg!(any(usart_v1, usart_v2)) && (sr.ore() || sr.idle()) {
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Some(rdr(r).read_volatile())
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} else {
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None
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};
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clear_interrupt_flags(r, sr);
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if sr.rxne() {
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if sr.pe() {
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warn!("Parity error");
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}
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@ -36,12 +43,11 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
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if sr.ore() {
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warn!("Overrun error");
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}
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if sr.rxne() {
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let mut rx_writer = state.rx_buf.writer();
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let buf = rx_writer.push_slice();
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if !buf.is_empty() {
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// This read also clears the error and idle interrupt flags on v1.
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buf[0] = rdr(r).read_volatile();
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buf[0] = dr.unwrap();
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rx_writer.push_done(1);
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} else {
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// FIXME: Should we disable any further RX interrupts when the buffer becomes full.
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@ -54,7 +60,7 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
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if sr.idle() {
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state.rx_waker.wake();
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};
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}
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}
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// TX
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