From b0f05e768225ae321cb08a469fa4a384cb8523ab Mon Sep 17 00:00:00 2001 From: Corey Schuhen <cschuhen@gmail.com> Date: Sun, 3 Mar 2024 20:45:51 +1000 Subject: [PATCH] Remove unused. --- embassy-stm32/src/can/bx/interrupt.rs | 130 -------------------------- embassy-stm32/src/can/bx/mod.rs | 72 -------------- 2 files changed, 202 deletions(-) delete mode 100644 embassy-stm32/src/can/bx/interrupt.rs diff --git a/embassy-stm32/src/can/bx/interrupt.rs b/embassy-stm32/src/can/bx/interrupt.rs deleted file mode 100644 index dac4b7b3c..000000000 --- a/embassy-stm32/src/can/bx/interrupt.rs +++ /dev/null @@ -1,130 +0,0 @@ -//! Interrupt types. - -use core::ops; - -#[allow(unused_imports)] // for intra-doc links only -use crate::can::bx::{Can, Rx0}; - -/// bxCAN interrupt sources. -/// -/// These can be individually enabled and disabled in the bxCAN peripheral. Note that the bxCAN -/// peripheral only exposes 4 interrupts to the microcontroller: -/// -/// * TX -/// * RX FIFO 1 -/// * RX FIFO 2 -/// * SCE (Status Change Error) -/// -/// This means that some of the interrupts listed here will result in the same interrupt handler -/// being invoked. -#[derive(Debug, Copy, Clone, Eq, PartialEq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[non_exhaustive] -pub enum Interrupt { - /// Fires the **TX** interrupt when one of the transmit mailboxes returns to empty state. - /// - /// This usually happens because its message was either transmitted successfully, or - /// transmission was aborted successfully. - /// - /// The interrupt handler must clear the interrupt condition by calling - /// [`Can::clear_request_completed_flag`] or [`Can::clear_tx_interrupt`]. - TransmitMailboxEmpty = 1 << 0, - - /// Fires the **RX FIFO 0** interrupt when FIFO 0 holds a message. - /// - /// The interrupt handler must clear the interrupt condition by receiving all messages from the - /// FIFO by calling [`Can::receive`] or [`Rx0::receive`]. - Fifo0MessagePending = 1 << 1, - - /// Fires the **RX FIFO 0** interrupt when FIFO 0 holds 3 incoming messages. - /// - /// The interrupt handler must clear the interrupt condition by receiving at least one message - /// from the FIFO (making it no longer "full"). This can be done by calling [`Can::receive`] or - /// [`Rx0::receive`]. - Fifo0Full = 1 << 2, - - /// Fires the **RX FIFO 0** interrupt when FIFO 0 drops an incoming message. - /// - /// The interrupt handler must clear the interrupt condition by calling [`Can::receive`] or - /// [`Rx0::receive`] (which will return an error). - Fifo0Overrun = 1 << 3, - - /// Fires the **RX FIFO 1** interrupt when FIFO 1 holds a message. - /// - /// Behavior is otherwise identical to [`Self::Fifo0MessagePending`]. - Fifo1MessagePending = 1 << 4, - - /// Fires the **RX FIFO 1** interrupt when FIFO 1 holds 3 incoming messages. - /// - /// Behavior is otherwise identical to [`Self::Fifo0Full`]. - Fifo1Full = 1 << 5, - - /// Fires the **RX FIFO 1** interrupt when FIFO 1 drops an incoming message. - /// - /// Behavior is otherwise identical to [`Self::Fifo0Overrun`]. - Fifo1Overrun = 1 << 6, - - Error = 1 << 15, - - /// Fires the **SCE** interrupt when an incoming CAN frame is detected while the peripheral is - /// in sleep mode. - /// - /// The interrupt handler must clear the interrupt condition by calling - /// [`Can::clear_wakeup_interrupt`]. - Wakeup = 1 << 16, - - /// Fires the **SCE** interrupt when the peripheral enters sleep mode. - /// - /// The interrupt handler must clear the interrupt condition by calling - /// [`Can::clear_sleep_interrupt`]. - Sleep = 1 << 17, -} - -bitflags::bitflags! { - /// A set of bxCAN interrupts. - pub struct Interrupts: u32 { - const TRANSMIT_MAILBOX_EMPTY = 1 << 0; - const FIFO0_MESSAGE_PENDING = 1 << 1; - const FIFO0_FULL = 1 << 2; - const FIFO0_OVERRUN = 1 << 3; - const FIFO1_MESSAGE_PENDING = 1 << 4; - const FIFO1_FULL = 1 << 5; - const FIFO1_OVERRUN = 1 << 6; - const ERROR = 1 << 15; - const WAKEUP = 1 << 16; - const SLEEP = 1 << 17; - } -} - -impl From<Interrupt> for Interrupts { - #[inline] - fn from(i: Interrupt) -> Self { - Self::from_bits_truncate(i as u32) - } -} - -/// Adds an interrupt to the interrupt set. -impl ops::BitOrAssign<Interrupt> for Interrupts { - #[inline] - fn bitor_assign(&mut self, rhs: Interrupt) { - *self |= Self::from(rhs); - } -} - -#[cfg(test)] -mod tests { - use super::*; - - #[test] - fn interrupt_flags() { - assert_eq!(Interrupts::from(Interrupt::Sleep), Interrupts::SLEEP); - assert_eq!( - Interrupts::from(Interrupt::TransmitMailboxEmpty), - Interrupts::TRANSMIT_MAILBOX_EMPTY - ); - - let mut ints = Interrupts::FIFO0_FULL; - ints |= Interrupt::Fifo1Full; - assert_eq!(ints, Interrupts::FIFO0_FULL | Interrupts::FIFO1_FULL); - } -} diff --git a/embassy-stm32/src/can/bx/mod.rs b/embassy-stm32/src/can/bx/mod.rs index d6e023217..c5801abec 100644 --- a/embassy-stm32/src/can/bx/mod.rs +++ b/embassy-stm32/src/can/bx/mod.rs @@ -27,7 +27,6 @@ pub mod filter; mod frame; mod id; -mod interrupt; #[allow(clippy::all)] // generated code mod pac; @@ -43,7 +42,6 @@ pub use id::{ExtendedId, Id, StandardId}; use self::pac::generic::*; use crate::can::bx::filter::MasterFilters; pub use crate::can::bx::frame::{Data, Frame, FramePriority}; -pub use crate::can::bx::interrupt::{Interrupt, Interrupts}; pub use crate::can::bx::pac::can::RegisterBlock; // To make the PAC extraction build /// A bxCAN peripheral instance. @@ -551,76 +549,6 @@ where } } - /// Starts listening for a CAN interrupt. - pub fn enable_interrupt(&mut self, interrupt: Interrupt) { - self.enable_interrupts(Interrupts::from_bits_truncate(interrupt as u32)) - } - - /// Starts listening for a set of CAN interrupts. - pub fn enable_interrupts(&mut self, interrupts: Interrupts) { - self.registers() - .ier - .modify(|r, w| unsafe { w.bits(r.bits() | interrupts.bits()) }) - } - - /// Stops listening for a CAN interrupt. - pub fn disable_interrupt(&mut self, interrupt: Interrupt) { - self.disable_interrupts(Interrupts::from_bits_truncate(interrupt as u32)) - } - - /// Stops listening for a set of CAN interrupts. - pub fn disable_interrupts(&mut self, interrupts: Interrupts) { - self.registers() - .ier - .modify(|r, w| unsafe { w.bits(r.bits() & !interrupts.bits()) }) - } - - /// Clears the pending flag of [`Interrupt::Sleep`]. - pub fn clear_sleep_interrupt(&self) { - let can = self.registers(); - // Read-only register with write-1-to-clear, so `&self` is sufficient. - can.msr.write(|w| w.slaki().set_bit()); - } - - /// Clears the pending flag of [`Interrupt::Wakeup`]. - pub fn clear_wakeup_interrupt(&self) { - let can = self.registers(); - // Read-only register with write-1-to-clear, so `&self` is sufficient. - can.msr.write(|w| w.wkui().set_bit()); - } - - /// Clears the "Request Completed" (RQCP) flag of a transmit mailbox. - /// - /// Returns the [`Mailbox`] whose flag was cleared. If no mailbox has the flag set, returns - /// `None`. - /// - /// Once this function returns `None`, a pending [`Interrupt::TransmitMailboxEmpty`] is - /// considered acknowledged. - pub fn clear_request_completed_flag(&mut self) -> Option<Mailbox> { - let can = self.registers(); - let tsr = can.tsr.read(); - if tsr.rqcp0().bit_is_set() { - can.tsr.modify(|_, w| w.rqcp0().set_bit()); - Some(Mailbox::Mailbox0) - } else if tsr.rqcp1().bit_is_set() { - can.tsr.modify(|_, w| w.rqcp1().set_bit()); - Some(Mailbox::Mailbox1) - } else if tsr.rqcp2().bit_is_set() { - can.tsr.modify(|_, w| w.rqcp2().set_bit()); - Some(Mailbox::Mailbox2) - } else { - None - } - } - - /// Clears a pending TX interrupt ([`Interrupt::TransmitMailboxEmpty`]). - /// - /// This does not return the mailboxes that have finished tranmission. If you need that - /// information, call [`Can::clear_request_completed_flag`] instead. - pub fn clear_tx_interrupt(&mut self) { - while self.clear_request_completed_flag().is_some() {} - } - /// Puts a CAN frame in a free transmit mailbox for transmission on the bus. /// /// Frames are transmitted to the bus based on their priority (see [`FramePriority`]).