Refactor bit search logic when no clock specified
Always search for a enable bit, even when no clock is specified in the yaml. Try to derive the clock name from the register name. This change picked up USART2 for stm32wle which was missing the clock.
This commit is contained in:
Timo Kröger
parent
37536695e1
commit
b36337b3d2
1 changed files with 61 additions and 79 deletions
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@ -423,87 +423,69 @@ pub fn gen(options: Options) {
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}
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if let Some(rcc) = &rcc {
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let clock_prefix: Option<&str> = if let Some(clock) = &p.clock {
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Some(clock)
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} else if name.starts_with("TIM") {
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// Not all peripherals like timers the clock hint due to insufficient information from
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// chip definition. If clock is not specified, the first matching register with the
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// expected field will be used.
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Some("")
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} else {
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None
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};
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// Workaround for clock registers being split on some chip families. Assume fields are
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// named after peripheral and look for first field matching and use that register.
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let mut en = find_reg_for_field(&rcc, "^.+ENR\\d*$", &format!("{}EN", name));
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let mut rst = find_reg_for_field(&rcc, "^.+RSTR\\d*$", &format!("{}RST", name));
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if let Some(clock_prefix) = clock_prefix {
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// Workaround for clock registers being split on some chip families. Assume fields are
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// named after peripheral and look for first field matching and use that register.
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let mut en =
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find_reg_for_field(&rcc, "^.+ENR\\d*$", &format!("{}EN", name));
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let mut rst =
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find_reg_for_field(&rcc, "^.+RSTR\\d*$", &format!("{}RST", name));
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if en.is_none() && name.ends_with("1") {
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en = find_reg_for_field(
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&rcc,
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"^.+ENR\\d*$",
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&format!("{}EN", &name[..name.len() - 1]),
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);
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rst = find_reg_for_field(
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&rcc,
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"^.+RSTR\\d*$",
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&format!("{}RST", &name[..name.len() - 1]),
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);
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}
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if en.is_none() && name.ends_with("1") {
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en = find_reg_for_field(
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&rcc,
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"^.+ENR\\d*$",
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&format!("{}EN", &name[..name.len() - 1]),
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);
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rst = find_reg_for_field(
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&rcc,
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"^.+RSTR\\d*$",
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&format!("{}RST", &name[..name.len() - 1]),
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);
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match (en, rst) {
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(Some((enable_reg, enable_field)), reset_reg_field) => {
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let clock = match &p.clock {
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Some(clock) => clock.as_str(),
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None => {
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// No clock was specified, derive the clock name from the enable register name.
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let re = Regex::new("([A-Z]+\\d*).*").unwrap();
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let caps = re.captures(enable_reg).expect(
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"unable to derive clock name from register name {}",
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);
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caps.get(1).unwrap().as_str()
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}
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};
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let clock = if name.starts_with("TIM") {
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format!("{}_tim", clock.to_ascii_lowercase())
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} else {
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clock.to_ascii_lowercase()
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};
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let mut row = Vec::with_capacity(6);
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row.push(name.clone());
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row.push(clock);
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row.push(enable_reg.to_ascii_lowercase());
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if let Some((reset_reg, reset_field)) = reset_reg_field {
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row.push(reset_reg.to_ascii_lowercase());
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row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
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row.push(format!("set_{}", reset_field.to_ascii_lowercase()));
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} else {
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row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
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}
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if !name.starts_with("GPIO") {
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peripheral_rcc_table.push(row);
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} else {
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gpio_rcc_table.push(row);
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gpio_regs.insert(enable_reg.to_ascii_lowercase());
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}
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}
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match (en, rst) {
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(Some((enable_reg, enable_field)), reset_reg_field) => {
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let clock = if clock_prefix.is_empty() {
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let re = Regex::new("([A-Z]+\\d*).*").unwrap();
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if !re.is_match(enable_reg) {
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panic!(
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"unable to derive clock name from register name {}",
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enable_reg
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);
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} else {
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let caps = re.captures(enable_reg).unwrap();
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caps.get(1).unwrap().as_str()
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}
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} else {
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clock_prefix
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};
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let clock = if name.starts_with("TIM") {
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format!("{}_tim", clock.to_ascii_lowercase())
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} else {
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clock.to_ascii_lowercase()
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};
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let mut row = Vec::with_capacity(6);
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row.push(name.clone());
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row.push(clock);
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row.push(enable_reg.to_ascii_lowercase());
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if let Some((reset_reg, reset_field)) = reset_reg_field {
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row.push(reset_reg.to_ascii_lowercase());
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row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
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row.push(format!("set_{}", reset_field.to_ascii_lowercase()));
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} else {
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row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
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}
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if !name.starts_with("GPIO") {
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peripheral_rcc_table.push(row);
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} else {
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gpio_rcc_table.push(row);
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gpio_regs.insert(enable_reg.to_ascii_lowercase());
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}
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}
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(None, Some(_)) => {
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println!("Unable to find enable register for {}", name)
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}
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(None, None) => {
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println!("Unable to find enable and reset register for {}", name)
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}
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(None, Some(_)) => {
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println!("Unable to find enable register for {}", name)
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}
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(None, None) => {
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println!("Unable to find enable and reset register for {}", name)
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}
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}
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}
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@ -770,6 +752,6 @@ fn gen_memory_x(out_dir: &PathBuf, chip: &Chip) {
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fs::create_dir_all(out_dir.join("memory_x")).unwrap();
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let mut file = File::create(out_dir.join("memory_x").join("memory.x")).unwrap();
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file.write_all( memory_x.as_bytes() ).unwrap();
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file.write_all(memory_x.as_bytes()).unwrap();
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}
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