Restore init order to restore H7.
Previous commit broke H7 support in HIL farm. Restore previous order by moving a bunch of config from new and into_config_mode to apply_config. This is a cleanup that I had considered to move more register access into peripheral.rs.
This commit is contained in:
Corey Schuhen
parent
bf06d10534
commit
b693ab9b34
2 changed files with 113 additions and 112 deletions
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@ -22,6 +22,7 @@ enum LoopbackMode {
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pub struct Registers {
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pub struct Registers {
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pub regs: &'static crate::pac::can::Fdcan,
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pub regs: &'static crate::pac::can::Fdcan,
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pub msgram: &'static crate::pac::fdcanram::Fdcanram,
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pub msgram: &'static crate::pac::fdcanram::Fdcanram,
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pub msg_ram_offset: usize,
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}
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}
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impl Registers {
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impl Registers {
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@ -294,7 +295,6 @@ impl Registers {
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pub fn into_config_mode(mut self, _config: FdCanConfig) {
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pub fn into_config_mode(mut self, _config: FdCanConfig) {
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self.set_power_down_mode(false);
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self.set_power_down_mode(false);
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self.enter_init_mode();
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self.enter_init_mode();
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self.reset_msg_ram();
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self.reset_msg_ram();
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// check the FDCAN core matches our expections
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// check the FDCAN core matches our expections
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@ -307,27 +307,6 @@ impl Registers {
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"Error reading endianness test value from FDCAN core"
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"Error reading endianness test value from FDCAN core"
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);
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);
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// set standard filters list size to 28
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// set extended filters list size to 8
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// REQUIRED: we use the memory map as if these settings are set
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// instead of re-calculating them.
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#[cfg(not(stm32h7))]
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{
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self.regs.rxgfc().modify(|w| {
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w.set_lss(crate::can::fd::message_ram::STANDARD_FILTER_MAX);
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w.set_lse(crate::can::fd::message_ram::EXTENDED_FILTER_MAX);
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});
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}
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#[cfg(stm32h7)]
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{
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self.regs
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.sidfc()
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.modify(|w| w.set_lss(crate::can::fd::message_ram::STANDARD_FILTER_MAX));
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self.regs
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.xidfc()
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.modify(|w| w.set_lse(crate::can::fd::message_ram::EXTENDED_FILTER_MAX));
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}
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/*
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/*
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for fid in 0..crate::can::message_ram::STANDARD_FILTER_MAX {
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for fid in 0..crate::can::message_ram::STANDARD_FILTER_MAX {
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self.set_standard_filter((fid as u8).into(), StandardFilter::disable());
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self.set_standard_filter((fid as u8).into(), StandardFilter::disable());
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@ -353,6 +332,51 @@ impl Registers {
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#[inline]
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#[inline]
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pub fn apply_config(&mut self, config: FdCanConfig) {
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pub fn apply_config(&mut self, config: FdCanConfig) {
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self.set_tx_buffer_mode(config.tx_buffer_mode);
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self.set_tx_buffer_mode(config.tx_buffer_mode);
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// set standard filters list size to 28
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// set extended filters list size to 8
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// REQUIRED: we use the memory map as if these settings are set
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// instead of re-calculating them.
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#[cfg(not(stm32h7))]
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{
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self.regs.rxgfc().modify(|w| {
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w.set_lss(crate::can::fd::message_ram::STANDARD_FILTER_MAX);
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w.set_lse(crate::can::fd::message_ram::EXTENDED_FILTER_MAX);
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});
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}
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#[cfg(stm32h7)]
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{
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self.regs
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.sidfc()
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.modify(|w| w.set_lss(crate::can::fd::message_ram::STANDARD_FILTER_MAX));
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self.regs
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.xidfc()
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.modify(|w| w.set_lse(crate::can::fd::message_ram::EXTENDED_FILTER_MAX));
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}
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self.configure_msg_ram();
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// Enable timestamping
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#[cfg(not(stm32h7))]
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self.regs
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.tscc()
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.write(|w| w.set_tss(stm32_metapac::can::vals::Tss::INCREMENT));
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#[cfg(stm32h7)]
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self.regs.tscc().write(|w| w.set_tss(0x01));
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// this isn't really documented in the reference manual
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// but corresponding txbtie bit has to be set for the TC (TxComplete) interrupt to fire
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self.regs.txbtie().write(|w| w.0 = 0xffff_ffff);
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self.regs.ie().modify(|w| {
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w.set_rfne(0, true); // Rx Fifo 0 New Msg
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w.set_rfne(1, true); // Rx Fifo 1 New Msg
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w.set_tce(true); // Tx Complete
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});
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self.regs.ile().modify(|w| {
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w.set_eint0(true); // Interrupt Line 0
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w.set_eint1(true); // Interrupt Line 1
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});
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self.set_data_bit_timing(config.dbtr);
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self.set_data_bit_timing(config.dbtr);
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self.set_nominal_bit_timing(config.nbtr);
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self.set_nominal_bit_timing(config.nbtr);
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self.set_automatic_retransmit(config.automatic_retransmit);
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self.set_automatic_retransmit(config.automatic_retransmit);
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@ -600,6 +624,71 @@ impl Registers {
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w.set_rrfe(filter.reject_remote_extended_frames);
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w.set_rrfe(filter.reject_remote_extended_frames);
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});
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});
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}
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}
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#[cfg(not(stm32h7))]
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fn configure_msg_ram(&mut self) {}
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#[cfg(stm32h7)]
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fn configure_msg_ram(&mut self) {
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let r = self.regs;
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use crate::can::fd::message_ram::*;
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//use fdcan::message_ram::*;
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let mut offset_words = self.msg_ram_offset as u16;
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// 11-bit filter
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r.sidfc().modify(|w| w.set_flssa(offset_words));
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offset_words += STANDARD_FILTER_MAX as u16;
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// 29-bit filter
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r.xidfc().modify(|w| w.set_flesa(offset_words));
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offset_words += 2 * EXTENDED_FILTER_MAX as u16;
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// Rx FIFO 0 and 1
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for i in 0..=1 {
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r.rxfc(i).modify(|w| {
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w.set_fsa(offset_words);
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w.set_fs(RX_FIFO_MAX);
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w.set_fwm(RX_FIFO_MAX);
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});
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offset_words += 18 * RX_FIFO_MAX as u16;
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}
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// Rx buffer - see below
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// Tx event FIFO
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r.txefc().modify(|w| {
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w.set_efsa(offset_words);
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w.set_efs(TX_EVENT_MAX);
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w.set_efwm(TX_EVENT_MAX);
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});
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offset_words += 2 * TX_EVENT_MAX as u16;
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// Tx buffers
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r.txbc().modify(|w| {
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w.set_tbsa(offset_words);
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w.set_tfqs(TX_FIFO_MAX);
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});
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offset_words += 18 * TX_FIFO_MAX as u16;
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// Rx Buffer - not used
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r.rxbc().modify(|w| {
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w.set_rbsa(offset_words);
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});
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// TX event FIFO?
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// Trigger memory?
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// Set the element sizes to 16 bytes
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r.rxesc().modify(|w| {
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w.set_rbds(0b111);
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for i in 0..=1 {
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w.set_fds(i, 0b111);
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}
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});
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r.txesc().modify(|w| {
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w.set_tbds(0b111);
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})
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}
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}
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}
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fn make_id(id: u32, extended: bool) -> embedded_can::Id {
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fn make_id(id: u32, extended: bool) -> embedded_can::Id {
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@ -184,43 +184,20 @@ impl<'d, T: Instance> FdcanConfigurator<'d, T> {
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T::enable_and_reset();
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T::enable_and_reset();
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let mut config = crate::can::fd::config::FdCanConfig::default();
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let mut config = crate::can::fd::config::FdCanConfig::default();
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config.timestamp_source = TimestampSource::Prescaler(TimestampPrescaler::_1);
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T::registers().into_config_mode(config);
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T::registers().into_config_mode(config);
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rx.set_as_af(rx.af_num(), AFType::Input);
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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T::configure_msg_ram();
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unsafe {
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unsafe {
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// Enable timestamping
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#[cfg(not(stm32h7))]
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T::regs()
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.tscc()
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.write(|w| w.set_tss(stm32_metapac::can::vals::Tss::INCREMENT));
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#[cfg(stm32h7)]
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T::regs().tscc().write(|w| w.set_tss(0x01));
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config.timestamp_source = TimestampSource::Prescaler(TimestampPrescaler::_1);
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T::IT0Interrupt::unpend(); // Not unsafe
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T::IT0Interrupt::unpend(); // Not unsafe
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T::IT0Interrupt::enable();
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T::IT0Interrupt::enable();
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T::IT1Interrupt::unpend(); // Not unsafe
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T::IT1Interrupt::unpend(); // Not unsafe
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T::IT1Interrupt::enable();
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T::IT1Interrupt::enable();
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// this isn't really documented in the reference manual
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// but corresponding txbtie bit has to be set for the TC (TxComplete) interrupt to fire
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T::regs().txbtie().write(|w| w.0 = 0xffff_ffff);
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}
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}
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T::regs().ie().modify(|w| {
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w.set_rfne(0, true); // Rx Fifo 0 New Msg
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w.set_rfne(1, true); // Rx Fifo 1 New Msg
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w.set_tce(true); // Tx Complete
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});
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T::regs().ile().modify(|w| {
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w.set_eint0(true); // Interrupt Line 0
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w.set_eint1(true); // Interrupt Line 1
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});
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Self {
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Self {
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config,
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config,
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instance: FdcanInstance(peri),
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instance: FdcanInstance(peri),
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@ -869,71 +846,6 @@ pub(crate) mod sealed {
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fn state() -> &'static State;
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fn state() -> &'static State;
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unsafe fn mut_state() -> &'static mut State;
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unsafe fn mut_state() -> &'static mut State;
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fn calc_timestamp(ns_per_timer_tick: u64, ts_val: u16) -> Timestamp;
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fn calc_timestamp(ns_per_timer_tick: u64, ts_val: u16) -> Timestamp;
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#[cfg(not(stm32h7))]
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fn configure_msg_ram() {}
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#[cfg(stm32h7)]
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fn configure_msg_ram() {
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let r = Self::regs();
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use crate::can::fd::message_ram::*;
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//use fdcan::message_ram::*;
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let mut offset_words = Self::MSG_RAM_OFFSET as u16;
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// 11-bit filter
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r.sidfc().modify(|w| w.set_flssa(offset_words));
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offset_words += STANDARD_FILTER_MAX as u16;
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// 29-bit filter
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r.xidfc().modify(|w| w.set_flesa(offset_words));
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offset_words += 2 * EXTENDED_FILTER_MAX as u16;
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// Rx FIFO 0 and 1
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for i in 0..=1 {
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r.rxfc(i).modify(|w| {
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w.set_fsa(offset_words);
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w.set_fs(RX_FIFO_MAX);
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w.set_fwm(RX_FIFO_MAX);
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});
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offset_words += 18 * RX_FIFO_MAX as u16;
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}
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// Rx buffer - see below
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// Tx event FIFO
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r.txefc().modify(|w| {
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w.set_efsa(offset_words);
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w.set_efs(TX_EVENT_MAX);
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w.set_efwm(TX_EVENT_MAX);
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});
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offset_words += 2 * TX_EVENT_MAX as u16;
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// Tx buffers
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r.txbc().modify(|w| {
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w.set_tbsa(offset_words);
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w.set_tfqs(TX_FIFO_MAX);
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});
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offset_words += 18 * TX_FIFO_MAX as u16;
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// Rx Buffer - not used
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r.rxbc().modify(|w| {
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w.set_rbsa(offset_words);
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});
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// TX event FIFO?
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// Trigger memory?
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// Set the element sizes to 16 bytes
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r.rxesc().modify(|w| {
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w.set_rbds(0b111);
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for i in 0..=1 {
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w.set_fds(i, 0b111);
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}
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});
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r.txesc().modify(|w| {
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w.set_tbds(0b111);
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})
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}
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}
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}
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}
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}
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@ -957,7 +869,7 @@ macro_rules! impl_fdcan {
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&crate::pac::$inst
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&crate::pac::$inst
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}
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}
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fn registers() -> Registers {
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fn registers() -> Registers {
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Registers{regs: &crate::pac::$inst, msgram: &crate::pac::$msg_ram_inst}
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Registers{regs: &crate::pac::$inst, msgram: &crate::pac::$msg_ram_inst, msg_ram_offset: Self::MSG_RAM_OFFSET}
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}
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}
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fn ram() -> &'static crate::pac::fdcanram::Fdcanram {
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fn ram() -> &'static crate::pac::fdcanram::Fdcanram {
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&crate::pac::$msg_ram_inst
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&crate::pac::$msg_ram_inst
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