diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index 2c620798d..fb72422bd 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -377,7 +377,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
         });
 
         // Enable UARTE instance
-        apply_workaround_for_enable_anomaly(&r);
+        apply_workaround_for_enable_anomaly(r);
         r.enable.write(|w| w.enable().enabled());
 
         // Configure byte counter.
diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs
index e0583b770..bfcff60a1 100644
--- a/embassy-nrf/src/pwm.rs
+++ b/embassy-nrf/src/pwm.rs
@@ -697,7 +697,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
         // Enable
         r.enable.write(|w| w.enable().enabled());
 
-        r.seq0.ptr.write(|w| unsafe { w.bits((&pwm.duty).as_ptr() as u32) });
+        r.seq0.ptr.write(|w| unsafe { w.bits((pwm.duty).as_ptr() as u32) });
 
         r.seq0.cnt.write(|w| unsafe { w.bits(4) });
         r.seq0.refresh.write(|w| unsafe { w.bits(0) });
@@ -748,7 +748,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
         self.duty[channel] = duty & 0x7FFF;
 
         // reload ptr in case self was moved
-        r.seq0.ptr.write(|w| unsafe { w.bits((&self.duty).as_ptr() as u32) });
+        r.seq0.ptr.write(|w| unsafe { w.bits((self.duty).as_ptr() as u32) });
 
         // defensive before seqstart
         compiler_fence(Ordering::SeqCst);
diff --git a/embassy-nrf/src/twim.rs b/embassy-nrf/src/twim.rs
index 83971463f..30699283f 100644
--- a/embassy-nrf/src/twim.rs
+++ b/embassy-nrf/src/twim.rs
@@ -469,7 +469,7 @@ impl<'d, T: Instance> Twim<'d, T> {
                 trace!("Copying TWIM tx buffer into RAM for DMA");
                 let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
                 tx_ram_buf.copy_from_slice(wr_buffer);
-                self.setup_write_read_from_ram(address, &tx_ram_buf, rd_buffer, inten)
+                self.setup_write_read_from_ram(address, tx_ram_buf, rd_buffer, inten)
             }
             Err(error) => Err(error),
         }
@@ -482,7 +482,7 @@ impl<'d, T: Instance> Twim<'d, T> {
                 trace!("Copying TWIM tx buffer into RAM for DMA");
                 let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
                 tx_ram_buf.copy_from_slice(wr_buffer);
-                self.setup_write_from_ram(address, &tx_ram_buf, inten)
+                self.setup_write_from_ram(address, tx_ram_buf, inten)
             }
             Err(error) => Err(error),
         }
diff --git a/embassy-nrf/src/twis.rs b/embassy-nrf/src/twis.rs
index c6c020557..415150447 100644
--- a/embassy-nrf/src/twis.rs
+++ b/embassy-nrf/src/twis.rs
@@ -577,7 +577,7 @@ impl<'d, T: Instance> Twis<'d, T> {
                 trace!("Copying TWIS tx buffer into RAM for DMA");
                 let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
                 tx_ram_buf.copy_from_slice(wr_buffer);
-                self.setup_respond_from_ram(&tx_ram_buf, inten)
+                self.setup_respond_from_ram(tx_ram_buf, inten)
             }
             Err(error) => Err(error),
         }
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 3d486452f..67b3feae7 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -308,7 +308,7 @@ fn configure(r: &RegisterBlock, config: Config, hardware_flow_control: bool) {
     r.events_txstarted.reset();
 
     // Enable
-    apply_workaround_for_enable_anomaly(&r);
+    apply_workaround_for_enable_anomaly(r);
     r.enable.write(|w| w.enable().enabled());
 }
 
@@ -378,7 +378,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
                 trace!("Copying UARTE tx buffer into RAM for DMA");
                 let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()];
                 ram_buf.copy_from_slice(buffer);
-                self.write_from_ram(&ram_buf).await
+                self.write_from_ram(ram_buf).await
             }
             Err(error) => Err(error),
         }
@@ -448,7 +448,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
                 trace!("Copying UARTE tx buffer into RAM for DMA");
                 let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()];
                 ram_buf.copy_from_slice(buffer);
-                self.blocking_write_from_ram(&ram_buf)
+                self.blocking_write_from_ram(ram_buf)
             }
             Err(error) => Err(error),
         }
@@ -504,7 +504,7 @@ impl<'a, T: Instance> Drop for UarteTx<'a, T> {
 
         let s = T::state();
 
-        drop_tx_rx(&r, &s);
+        drop_tx_rx(r, s);
     }
 }
 
@@ -744,7 +744,7 @@ impl<'a, T: Instance> Drop for UarteRx<'a, T> {
 
         let s = T::state();
 
-        drop_tx_rx(&r, &s);
+        drop_tx_rx(r, s);
     }
 }