NaxdyOrg/embassy
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

nrf: add support for nrf52805, nrf52811, nrf52820

Browse source
This commit is contained in:
Dario Nieuwenhuis 2021-05-11 03:04:59 +02:00
parent cd4111736c
commit bd9589d0ce
21 changed files with 1600 additions and 602 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
.github/workflows/rust.yml vendored
View file

@ -30,22 +30,31 @@ jobs:
target: thumbv7em-none-eabi
- package: embassy-nrf
target: thumbv7em-none-eabi
features: 52810
features: nrf52805
- package: embassy-nrf
target: thumbv7em-none-eabi
features: 52832
features: nrf52810
- package: embassy-nrf
target: thumbv7em-none-eabi
features: 52833
features: nrf52811
- package: embassy-nrf
target: thumbv7em-none-eabi
features: 52840
features: nrf52820
- package: embassy-nrf
target: thumbv7em-none-eabi
features: 52840,log
features: nrf52832
- package: embassy-nrf
target: thumbv7em-none-eabi
features: 52840,defmt
features: nrf52833
- package: embassy-nrf
target: thumbv7em-none-eabi
features: nrf52840
- package: embassy-nrf
target: thumbv7em-none-eabi
features: nrf52840,log
- package: embassy-nrf
target: thumbv7em-none-eabi
features: nrf52840,defmt
- package: embassy-stm32-examples
target: thumbv7em-none-eabi
features: stm32f405

2
embassy-macros/src/lib.rs
View file

@ -130,7 +130,7 @@ pub fn interrupt_declare(item: TokenStream) -> TokenStream {
let result = quote! {
#[allow(non_camel_case_types)]
pub struct #name_interrupt(());
unsafe impl Interrupt for #name_interrupt {
unsafe impl ::embassy::interrupt::Interrupt for #name_interrupt {
type Priority = crate::interrupt::Priority;
fn number(&self) -> u16 {
use cortex_m::interrupt::InterruptNumber;

2
embassy-nrf-examples/Cargo.toml
View file

@ -19,7 +19,7 @@ defmt-error = []
[dependencies]
embassy = { version = "0.1.0", path = "../embassy", features = ["defmt", "defmt-trace"] }
embassy-traits = { version = "0.1.0", path = "../embassy-traits", features = ["defmt"] }
embassy-nrf = { version = "0.1.0", path = "../embassy-nrf", features = ["defmt", "defmt-trace", "52840"] }
embassy-nrf = { version = "0.1.0", path = "../embassy-nrf", features = ["defmt", "defmt-trace", "nrf52840"] }
defmt = "0.2.0"
defmt-rtt = "0.2.0"

9
embassy-nrf-examples/src/bin/spim.rs
View file

@ -24,14 +24,11 @@ async fn main(spawner: Spawner) {
let p = unsafe { Peripherals::steal() };
let config = spim::Config {
frequency: spim::Frequency::M16,
mode: spim::MODE_0,
orc: 0x00,
};
let mut config = spim::Config::default();
config.frequency = spim::Frequency::M16;
let irq = interrupt::take!(SPIM3);
let mut spim = spim::Spim::new(p.SPIM3, irq, p.P0_29, p.P0_28, p.P0_30, config);
let mut spim = spim::Spim::new(p.SPI3, irq, p.P0_29, p.P0_28, p.P0_30, config);
let mut ncs = Output::new(p.P0_31, Level::High, OutputDrive::Standard);

16
embassy-nrf/Cargo.toml
View file

@ -11,11 +11,13 @@ defmt-info = [ ]
defmt-warn = [ ]
defmt-error = [ ]
52810 = ["nrf52810-pac"]
52811 = ["nrf52811-pac"]
52832 = ["nrf52832-pac"]
52833 = ["nrf52833-pac"]
52840 = ["nrf52840-pac"]
nrf52805 = ["nrf52805-pac"]
nrf52810 = ["nrf52810-pac"]
nrf52811 = ["nrf52811-pac"]
nrf52820 = ["nrf52820-pac"]
nrf52832 = ["nrf52832-pac"]
nrf52833 = ["nrf52833-pac"]
nrf52840 = ["nrf52840-pac"]
[dependencies]
@ -30,10 +32,12 @@ cortex-m = "0.7.1"
embedded-hal = { version = "0.2.4" }
embedded-dma = { version = "0.1.2" }
futures = { version = "0.3.5", default-features = false }
critical-section = "0.2.1"
nrf52805-pac = { version = "0.1.0", optional = true, features = [ "rt" ], git = "https://github.com/Dirbaio/nrf52805-pac"}
nrf52810-pac = { version = "0.9.0", optional = true, features = [ "rt" ]}
nrf52811-pac = { version = "0.9.1", optional = true, features = [ "rt" ]}
nrf52820-pac = { version = "0.1.0", optional = true, features = [ "rt" ], git = "https://github.com/Dirbaio/nrf52820-pac"}
nrf52832-pac = { version = "0.9.0", optional = true, features = [ "rt" ]}
nrf52833-pac = { version = "0.9.0", optional = true, features = [ "rt" ]}
nrf52840-pac = { version = "0.9.0", optional = true, features = [ "rt" ]}
critical-section = "0.2.1"

182
embassy-nrf/src/chips/nrf52805.rs Normal file
View file

@ -0,0 +1,182 @@
pub use nrf52805_pac as pac;
pub const EASY_DMA_SIZE: usize = (1 << 14) - 1;
pub const FORCE_COPY_BUFFER_SIZE: usize = 256;
embassy_extras::peripherals! {
// RTC
RTC0,
RTC1,
// UARTE
UARTE0,
// SPI/TWI
TWI0,
SPI0,
// SAADC
SAADC,
// TIMER
TIMER0,
TIMER1,
TIMER2,
// GPIOTE
GPIOTE,
GPIOTE_CH0,
GPIOTE_CH1,
GPIOTE_CH2,
GPIOTE_CH3,
GPIOTE_CH4,
GPIOTE_CH5,
GPIOTE_CH6,
GPIOTE_CH7,
// PPI
PPI_CH0,
PPI_CH1,
PPI_CH2,
PPI_CH3,
PPI_CH4,
PPI_CH5,
PPI_CH6,
PPI_CH7,
PPI_CH8,
PPI_CH9,
PPI_CH10,
PPI_CH11,
PPI_CH12,
PPI_CH13,
PPI_CH14,
PPI_CH15,
PPI_CH16,
PPI_CH17,
PPI_CH18,
PPI_CH19,
PPI_CH20,
PPI_CH21,
PPI_CH22,
PPI_CH23,
PPI_CH24,
PPI_CH25,
PPI_CH26,
PPI_CH27,
PPI_CH28,
PPI_CH29,
PPI_CH30,
PPI_CH31,
PPI_GROUP0,
PPI_GROUP1,
PPI_GROUP2,
PPI_GROUP3,
PPI_GROUP4,
PPI_GROUP5,
// GPIO port 0
P0_00,
P0_01,
P0_02,
P0_03,
P0_04,
P0_05,
P0_06,
P0_07,
P0_08,
P0_09,
P0_10,
P0_11,
P0_12,
P0_13,
P0_14,
P0_15,
P0_16,
P0_17,
P0_18,
P0_19,
P0_20,
P0_21,
P0_22,
P0_23,
P0_24,
P0_25,
P0_26,
P0_27,
P0_28,
P0_29,
P0_30,
P0_31,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0);
impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0);
impl_timer!(TIMER0, TIMER0, TIMER0);
impl_timer!(TIMER1, TIMER1, TIMER1);
impl_timer!(TIMER2, TIMER2, TIMER2);
impl_pin!(P0_00, 0, 0);
impl_pin!(P0_01, 0, 1);
impl_pin!(P0_02, 0, 2);
impl_pin!(P0_03, 0, 3);
impl_pin!(P0_04, 0, 4);
impl_pin!(P0_05, 0, 5);
impl_pin!(P0_06, 0, 6);
impl_pin!(P0_07, 0, 7);
impl_pin!(P0_08, 0, 8);
impl_pin!(P0_09, 0, 9);
impl_pin!(P0_10, 0, 10);
impl_pin!(P0_11, 0, 11);
impl_pin!(P0_12, 0, 12);
impl_pin!(P0_13, 0, 13);
impl_pin!(P0_14, 0, 14);
impl_pin!(P0_15, 0, 15);
impl_pin!(P0_16, 0, 16);
impl_pin!(P0_17, 0, 17);
impl_pin!(P0_18, 0, 18);
impl_pin!(P0_19, 0, 19);
impl_pin!(P0_20, 0, 20);
impl_pin!(P0_21, 0, 21);
impl_pin!(P0_22, 0, 22);
impl_pin!(P0_23, 0, 23);
impl_pin!(P0_24, 0, 24);
impl_pin!(P0_25, 0, 25);
impl_pin!(P0_26, 0, 26);
impl_pin!(P0_27, 0, 27);
impl_pin!(P0_28, 0, 28);
impl_pin!(P0_29, 0, 29);
impl_pin!(P0_30, 0, 30);
impl_pin!(P0_31, 0, 31);
pub mod irqs {
use embassy_macros::interrupt_declare as declare;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(TWIM0_TWIS0_TWI0);
declare!(SPIM0_SPIS0_SPI0);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2);
declare!(SWI3);
declare!(SWI4);
declare!(SWI5);
}

183
embassy-nrf/src/chips/nrf52810.rs Normal file
View file

@ -0,0 +1,183 @@
pub use nrf52810_pac as pac;
pub const EASY_DMA_SIZE: usize = (1 << 10) - 1;
pub const FORCE_COPY_BUFFER_SIZE: usize = 256;
embassy_extras::peripherals! {
// RTC
RTC0,
RTC1,
// UARTE
UARTE0,
// SPI/TWI
TWI0,
SPI0,
// SAADC
SAADC,
// TIMER
TIMER0,
TIMER1,
TIMER2,
// GPIOTE
GPIOTE,
GPIOTE_CH0,
GPIOTE_CH1,
GPIOTE_CH2,
GPIOTE_CH3,
GPIOTE_CH4,
GPIOTE_CH5,
GPIOTE_CH6,
GPIOTE_CH7,
// PPI
PPI_CH0,
PPI_CH1,
PPI_CH2,
PPI_CH3,
PPI_CH4,
PPI_CH5,
PPI_CH6,
PPI_CH7,
PPI_CH8,
PPI_CH9,
PPI_CH10,
PPI_CH11,
PPI_CH12,
PPI_CH13,
PPI_CH14,
PPI_CH15,
PPI_CH16,
PPI_CH17,
PPI_CH18,
PPI_CH19,
PPI_CH20,
PPI_CH21,
PPI_CH22,
PPI_CH23,
PPI_CH24,
PPI_CH25,
PPI_CH26,
PPI_CH27,
PPI_CH28,
PPI_CH29,
PPI_CH30,
PPI_CH31,
PPI_GROUP0,
PPI_GROUP1,
PPI_GROUP2,
PPI_GROUP3,
PPI_GROUP4,
PPI_GROUP5,
// GPIO port 0
P0_00,
P0_01,
P0_02,
P0_03,
P0_04,
P0_05,
P0_06,
P0_07,
P0_08,
P0_09,
P0_10,
P0_11,
P0_12,
P0_13,
P0_14,
P0_15,
P0_16,
P0_17,
P0_18,
P0_19,
P0_20,
P0_21,
P0_22,
P0_23,
P0_24,
P0_25,
P0_26,
P0_27,
P0_28,
P0_29,
P0_30,
P0_31,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0);
impl_timer!(TIMER0, TIMER0, TIMER0);
impl_timer!(TIMER1, TIMER1, TIMER1);
impl_timer!(TIMER2, TIMER2, TIMER2);
impl_pin!(P0_00, 0, 0);
impl_pin!(P0_01, 0, 1);
impl_pin!(P0_02, 0, 2);
impl_pin!(P0_03, 0, 3);
impl_pin!(P0_04, 0, 4);
impl_pin!(P0_05, 0, 5);
impl_pin!(P0_06, 0, 6);
impl_pin!(P0_07, 0, 7);
impl_pin!(P0_08, 0, 8);
impl_pin!(P0_09, 0, 9);
impl_pin!(P0_10, 0, 10);
impl_pin!(P0_11, 0, 11);
impl_pin!(P0_12, 0, 12);
impl_pin!(P0_13, 0, 13);
impl_pin!(P0_14, 0, 14);
impl_pin!(P0_15, 0, 15);
impl_pin!(P0_16, 0, 16);
impl_pin!(P0_17, 0, 17);
impl_pin!(P0_18, 0, 18);
impl_pin!(P0_19, 0, 19);
impl_pin!(P0_20, 0, 20);
impl_pin!(P0_21, 0, 21);
impl_pin!(P0_22, 0, 22);
impl_pin!(P0_23, 0, 23);
impl_pin!(P0_24, 0, 24);
impl_pin!(P0_25, 0, 25);
impl_pin!(P0_26, 0, 26);
impl_pin!(P0_27, 0, 27);
impl_pin!(P0_28, 0, 28);
impl_pin!(P0_29, 0, 29);
impl_pin!(P0_30, 0, 30);
impl_pin!(P0_31, 0, 31);
pub mod irqs {
use embassy_macros::interrupt_declare as declare;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(TWIM0_TWIS0_TWI0);
declare!(SPIM0_SPIS0_SPI0);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2);
declare!(SWI3);
declare!(SWI4);
declare!(SWI5);
declare!(PWM0);
declare!(PDM);
}

184
embassy-nrf/src/chips/nrf52811.rs Normal file
View file

@ -0,0 +1,184 @@
pub use nrf52811_pac as pac;
pub const EASY_DMA_SIZE: usize = (1 << 14) - 1;
pub const FORCE_COPY_BUFFER_SIZE: usize = 256;
embassy_extras::peripherals! {
// RTC
RTC0,
RTC1,
// UARTE
UARTE0,
// SPI/TWI
TWISPI0,
SPI1,
// SAADC
SAADC,
// TIMER
TIMER0,
TIMER1,
TIMER2,
// GPIOTE
GPIOTE,
GPIOTE_CH0,
GPIOTE_CH1,
GPIOTE_CH2,
GPIOTE_CH3,
GPIOTE_CH4,
GPIOTE_CH5,
GPIOTE_CH6,
GPIOTE_CH7,
// PPI
PPI_CH0,
PPI_CH1,
PPI_CH2,
PPI_CH3,
PPI_CH4,
PPI_CH5,
PPI_CH6,
PPI_CH7,
PPI_CH8,
PPI_CH9,
PPI_CH10,
PPI_CH11,
PPI_CH12,
PPI_CH13,
PPI_CH14,
PPI_CH15,
PPI_CH16,
PPI_CH17,
PPI_CH18,
PPI_CH19,
PPI_CH20,
PPI_CH21,
PPI_CH22,
PPI_CH23,
PPI_CH24,
PPI_CH25,
PPI_CH26,
PPI_CH27,
PPI_CH28,
PPI_CH29,
PPI_CH30,
PPI_CH31,
PPI_GROUP0,
PPI_GROUP1,
PPI_GROUP2,
PPI_GROUP3,
PPI_GROUP4,
PPI_GROUP5,
// GPIO port 0
P0_00,
P0_01,
P0_02,
P0_03,
P0_04,
P0_05,
P0_06,
P0_07,
P0_08,
P0_09,
P0_10,
P0_11,
P0_12,
P0_13,
P0_14,
P0_15,
P0_16,
P0_17,
P0_18,
P0_19,
P0_20,
P0_21,
P0_22,
P0_23,
P0_24,
P0_25,
P0_26,
P0_27,
P0_28,
P0_29,
P0_30,
P0_31,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_spim!(TWISPI0, SPIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
impl_spim!(SPI1, SPIM1, SPIM1_SPIS1_SPI1);
impl_timer!(TIMER0, TIMER0, TIMER0);
impl_timer!(TIMER1, TIMER1, TIMER1);
impl_timer!(TIMER2, TIMER2, TIMER2);
impl_pin!(P0_00, 0, 0);
impl_pin!(P0_01, 0, 1);
impl_pin!(P0_02, 0, 2);
impl_pin!(P0_03, 0, 3);
impl_pin!(P0_04, 0, 4);
impl_pin!(P0_05, 0, 5);
impl_pin!(P0_06, 0, 6);
impl_pin!(P0_07, 0, 7);
impl_pin!(P0_08, 0, 8);
impl_pin!(P0_09, 0, 9);
impl_pin!(P0_10, 0, 10);
impl_pin!(P0_11, 0, 11);
impl_pin!(P0_12, 0, 12);
impl_pin!(P0_13, 0, 13);
impl_pin!(P0_14, 0, 14);
impl_pin!(P0_15, 0, 15);
impl_pin!(P0_16, 0, 16);
impl_pin!(P0_17, 0, 17);
impl_pin!(P0_18, 0, 18);
impl_pin!(P0_19, 0, 19);
impl_pin!(P0_20, 0, 20);
impl_pin!(P0_21, 0, 21);
impl_pin!(P0_22, 0, 22);
impl_pin!(P0_23, 0, 23);
impl_pin!(P0_24, 0, 24);
impl_pin!(P0_25, 0, 25);
impl_pin!(P0_26, 0, 26);
impl_pin!(P0_27, 0, 27);
impl_pin!(P0_28, 0, 28);
impl_pin!(P0_29, 0, 29);
impl_pin!(P0_30, 0, 30);
impl_pin!(P0_31, 0, 31);
pub mod irqs {
use embassy_macros::interrupt_declare as declare;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
declare!(SPIM1_SPIS1_SPI1);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2);
declare!(SWI3);
declare!(SWI4);
declare!(SWI5);
declare!(PWM0);
declare!(PDM);
}

185
embassy-nrf/src/chips/nrf52820.rs Normal file
View file

@ -0,0 +1,185 @@
pub use nrf52820_pac as pac;
pub const EASY_DMA_SIZE: usize = (1 << 15) - 1;
pub const FORCE_COPY_BUFFER_SIZE: usize = 512;
embassy_extras::peripherals! {
// RTC
RTC0,
RTC1,
// UARTE
UARTE0,
// SPI/TWI
TWISPI0,
TWISPI1,
// SAADC
SAADC,
// TIMER
TIMER0,
TIMER1,
TIMER2,
TIMER3,
// GPIOTE
GPIOTE,
GPIOTE_CH0,
GPIOTE_CH1,
GPIOTE_CH2,
GPIOTE_CH3,
GPIOTE_CH4,
GPIOTE_CH5,
GPIOTE_CH6,
GPIOTE_CH7,
// PPI
PPI_CH0,
PPI_CH1,
PPI_CH2,
PPI_CH3,
PPI_CH4,
PPI_CH5,
PPI_CH6,
PPI_CH7,
PPI_CH8,
PPI_CH9,
PPI_CH10,
PPI_CH11,
PPI_CH12,
PPI_CH13,
PPI_CH14,
PPI_CH15,
PPI_CH16,
PPI_CH17,
PPI_CH18,
PPI_CH19,
PPI_CH20,
PPI_CH21,
PPI_CH22,
PPI_CH23,
PPI_CH24,
PPI_CH25,
PPI_CH26,
PPI_CH27,
PPI_CH28,
PPI_CH29,
PPI_CH30,
PPI_CH31,
PPI_GROUP0,
PPI_GROUP1,
PPI_GROUP2,
PPI_GROUP3,
PPI_GROUP4,
PPI_GROUP5,
// GPIO port 0
P0_00,
P0_01,
P0_02,
P0_03,
P0_04,
P0_05,
P0_06,
P0_07,
P0_08,
P0_09,
P0_10,
P0_11,
P0_12,
P0_13,
P0_14,
P0_15,
P0_16,
P0_17,
P0_18,
P0_19,
P0_20,
P0_21,
P0_22,
P0_23,
P0_24,
P0_25,
P0_26,
P0_27,
P0_28,
P0_29,
P0_30,
P0_31,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_timer!(TIMER0, TIMER0, TIMER0);
impl_timer!(TIMER1, TIMER1, TIMER1);
impl_timer!(TIMER2, TIMER2, TIMER2);
impl_timer!(TIMER3, TIMER3, TIMER3, extended);
impl_pin!(P0_00, 0, 0);
impl_pin!(P0_01, 0, 1);
impl_pin!(P0_02, 0, 2);
impl_pin!(P0_03, 0, 3);
impl_pin!(P0_04, 0, 4);
impl_pin!(P0_05, 0, 5);
impl_pin!(P0_06, 0, 6);
impl_pin!(P0_07, 0, 7);
impl_pin!(P0_08, 0, 8);
impl_pin!(P0_09, 0, 9);
impl_pin!(P0_10, 0, 10);
impl_pin!(P0_11, 0, 11);
impl_pin!(P0_12, 0, 12);
impl_pin!(P0_13, 0, 13);
impl_pin!(P0_14, 0, 14);
impl_pin!(P0_15, 0, 15);
impl_pin!(P0_16, 0, 16);
impl_pin!(P0_17, 0, 17);
impl_pin!(P0_18, 0, 18);
impl_pin!(P0_19, 0, 19);
impl_pin!(P0_20, 0, 20);
impl_pin!(P0_21, 0, 21);
impl_pin!(P0_22, 0, 22);
impl_pin!(P0_23, 0, 23);
impl_pin!(P0_24, 0, 24);
impl_pin!(P0_25, 0, 25);
impl_pin!(P0_26, 0, 26);
impl_pin!(P0_27, 0, 27);
impl_pin!(P0_28, 0, 28);
impl_pin!(P0_29, 0, 29);
impl_pin!(P0_30, 0, 30);
impl_pin!(P0_31, 0, 31);
pub mod irqs {
use embassy_macros::interrupt_declare as declare;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(GPIOTE);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(USBD);
}

202
embassy-nrf/src/chips/nrf52832.rs Normal file
View file

@ -0,0 +1,202 @@
pub use nrf52832_pac as pac;
pub const EASY_DMA_SIZE: usize = (1 << 8) - 1;
pub const FORCE_COPY_BUFFER_SIZE: usize = 255;
embassy_extras::peripherals! {
// RTC
RTC0,
RTC1,
RTC2,
// UARTE
UARTE0,
// SPI/TWI
TWISPI0,
TWISPI1,
SPI2,
SPI3,
// SAADC
SAADC,
// TIMER
TIMER0,
TIMER1,
TIMER2,
TIMER3,
TIMER4,
// GPIOTE
GPIOTE,
GPIOTE_CH0,
GPIOTE_CH1,
GPIOTE_CH2,
GPIOTE_CH3,
GPIOTE_CH4,
GPIOTE_CH5,
GPIOTE_CH6,
GPIOTE_CH7,
// PPI
PPI_CH0,
PPI_CH1,
PPI_CH2,
PPI_CH3,
PPI_CH4,
PPI_CH5,
PPI_CH6,
PPI_CH7,
PPI_CH8,
PPI_CH9,
PPI_CH10,
PPI_CH11,
PPI_CH12,
PPI_CH13,
PPI_CH14,
PPI_CH15,
PPI_CH16,
PPI_CH17,
PPI_CH18,
PPI_CH19,
PPI_CH20,
PPI_CH21,
PPI_CH22,
PPI_CH23,
PPI_CH24,
PPI_CH25,
PPI_CH26,
PPI_CH27,
PPI_CH28,
PPI_CH29,
PPI_CH30,
PPI_CH31,
PPI_GROUP0,
PPI_GROUP1,
PPI_GROUP2,
PPI_GROUP3,
PPI_GROUP4,
PPI_GROUP5,
// GPIO port 0
P0_00,
P0_01,
P0_02,
P0_03,
P0_04,
P0_05,
P0_06,
P0_07,
P0_08,
P0_09,
P0_10,
P0_11,
P0_12,
P0_13,
P0_14,
P0_15,
P0_16,
P0_17,
P0_18,
P0_19,
P0_20,
P0_21,
P0_22,
P0_23,
P0_24,
P0_25,
P0_26,
P0_27,
P0_28,
P0_29,
P0_30,
P0_31,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
impl_timer!(TIMER0, TIMER0, TIMER0);
impl_timer!(TIMER1, TIMER1, TIMER1);
impl_timer!(TIMER2, TIMER2, TIMER2);
impl_timer!(TIMER3, TIMER3, TIMER3, extended);
impl_timer!(TIMER4, TIMER4, TIMER4, extended);
impl_pin!(P0_00, 0, 0);
impl_pin!(P0_01, 0, 1);
impl_pin!(P0_02, 0, 2);
impl_pin!(P0_03, 0, 3);
impl_pin!(P0_04, 0, 4);
impl_pin!(P0_05, 0, 5);
impl_pin!(P0_06, 0, 6);
impl_pin!(P0_07, 0, 7);
impl_pin!(P0_08, 0, 8);
impl_pin!(P0_09, 0, 9);
impl_pin!(P0_10, 0, 10);
impl_pin!(P0_11, 0, 11);
impl_pin!(P0_12, 0, 12);
impl_pin!(P0_13, 0, 13);
impl_pin!(P0_14, 0, 14);
impl_pin!(P0_15, 0, 15);
impl_pin!(P0_16, 0, 16);
impl_pin!(P0_17, 0, 17);
impl_pin!(P0_18, 0, 18);
impl_pin!(P0_19, 0, 19);
impl_pin!(P0_20, 0, 20);
impl_pin!(P0_21, 0, 21);
impl_pin!(P0_22, 0, 22);
impl_pin!(P0_23, 0, 23);
impl_pin!(P0_24, 0, 24);
impl_pin!(P0_25, 0, 25);
impl_pin!(P0_26, 0, 26);
impl_pin!(P0_27, 0, 27);
impl_pin!(P0_28, 0, 28);
impl_pin!(P0_29, 0, 29);
impl_pin!(P0_30, 0, 30);
impl_pin!(P0_31, 0, 31);
pub mod irqs {
use embassy_macros::interrupt_declare as declare;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(I2S);
declare!(FPU);
}

244
embassy-nrf/src/chips/nrf52833.rs Normal file
View file

@ -0,0 +1,244 @@
pub use nrf52833_pac as pac;
pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
pub const FORCE_COPY_BUFFER_SIZE: usize = 512;
embassy_extras::peripherals! {
// RTC
RTC0,
RTC1,
RTC2,
// UARTE
UARTE0,
UARTE1,
// SPI/TWI
TWISPI0,
TWISPI1,
SPI2,
SPI3,
// SAADC
SAADC,
// TIMER
TIMER0,
TIMER1,
TIMER2,
TIMER3,
TIMER4,
// GPIOTE
GPIOTE,
GPIOTE_CH0,
GPIOTE_CH1,
GPIOTE_CH2,
GPIOTE_CH3,
GPIOTE_CH4,
GPIOTE_CH5,
GPIOTE_CH6,
GPIOTE_CH7,
// PPI
PPI_CH0,
PPI_CH1,
PPI_CH2,
PPI_CH3,
PPI_CH4,
PPI_CH5,
PPI_CH6,
PPI_CH7,
PPI_CH8,
PPI_CH9,
PPI_CH10,
PPI_CH11,
PPI_CH12,
PPI_CH13,
PPI_CH14,
PPI_CH15,
PPI_CH16,
PPI_CH17,
PPI_CH18,
PPI_CH19,
PPI_CH20,
PPI_CH21,
PPI_CH22,
PPI_CH23,
PPI_CH24,
PPI_CH25,
PPI_CH26,
PPI_CH27,
PPI_CH28,
PPI_CH29,
PPI_CH30,
PPI_CH31,
PPI_GROUP0,
PPI_GROUP1,
PPI_GROUP2,
PPI_GROUP3,
PPI_GROUP4,
PPI_GROUP5,
// GPIO port 0
P0_00,
P0_01,
P0_02,
P0_03,
P0_04,
P0_05,
P0_06,
P0_07,
P0_08,
P0_09,
P0_10,
P0_11,
P0_12,
P0_13,
P0_14,
P0_15,
P0_16,
P0_17,
P0_18,
P0_19,
P0_20,
P0_21,
P0_22,
P0_23,
P0_24,
P0_25,
P0_26,
P0_27,
P0_28,
P0_29,
P0_30,
P0_31,
// GPIO port 1
P1_00,
P1_01,
P1_02,
P1_03,
P1_04,
P1_05,
P1_06,
P1_07,
P1_08,
P1_09,
P1_10,
P1_11,
P1_12,
P1_13,
P1_14,
P1_15,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_uarte!(UARTE1, UARTE1, UARTE1);
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
impl_spim!(SPI3, SPIM3, SPIM3);
impl_timer!(TIMER0, TIMER0, TIMER0);
impl_timer!(TIMER1, TIMER1, TIMER1);
impl_timer!(TIMER2, TIMER2, TIMER2);
impl_timer!(TIMER3, TIMER3, TIMER3, extended);
impl_timer!(TIMER4, TIMER4, TIMER4, extended);
impl_pin!(P0_00, 0, 0);
impl_pin!(P0_01, 0, 1);
impl_pin!(P0_02, 0, 2);
impl_pin!(P0_03, 0, 3);
impl_pin!(P0_04, 0, 4);
impl_pin!(P0_05, 0, 5);
impl_pin!(P0_06, 0, 6);
impl_pin!(P0_07, 0, 7);
impl_pin!(P0_08, 0, 8);
impl_pin!(P0_09, 0, 9);
impl_pin!(P0_10, 0, 10);
impl_pin!(P0_11, 0, 11);
impl_pin!(P0_12, 0, 12);
impl_pin!(P0_13, 0, 13);
impl_pin!(P0_14, 0, 14);
impl_pin!(P0_15, 0, 15);
impl_pin!(P0_16, 0, 16);
impl_pin!(P0_17, 0, 17);
impl_pin!(P0_18, 0, 18);
impl_pin!(P0_19, 0, 19);
impl_pin!(P0_20, 0, 20);
impl_pin!(P0_21, 0, 21);
impl_pin!(P0_22, 0, 22);
impl_pin!(P0_23, 0, 23);
impl_pin!(P0_24, 0, 24);
impl_pin!(P0_25, 0, 25);
impl_pin!(P0_26, 0, 26);
impl_pin!(P0_27, 0, 27);
impl_pin!(P0_28, 0, 28);
impl_pin!(P0_29, 0, 29);
impl_pin!(P0_30, 0, 30);
impl_pin!(P0_31, 0, 31);
impl_pin!(P1_00, 1, 0);
impl_pin!(P1_01, 1, 1);
impl_pin!(P1_02, 1, 2);
impl_pin!(P1_03, 1, 3);
impl_pin!(P1_04, 1, 4);
impl_pin!(P1_05, 1, 5);
impl_pin!(P1_06, 1, 6);
impl_pin!(P1_07, 1, 7);
impl_pin!(P1_08, 1, 8);
impl_pin!(P1_09, 1, 9);
impl_pin!(P1_10, 1, 10);
impl_pin!(P1_11, 1, 11);
impl_pin!(P1_12, 1, 12);
impl_pin!(P1_13, 1, 13);
impl_pin!(P1_14, 1, 14);
impl_pin!(P1_15, 1, 15);
pub mod irqs {
use embassy_macros::interrupt_declare as declare;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(I2S);
declare!(FPU);
declare!(USBD);
declare!(UARTE1);
declare!(PWM3);
declare!(SPIM3);
}

251
embassy-nrf/src/chips/nrf52840.rs Normal file
View file

@ -0,0 +1,251 @@
pub use nrf52840_pac as pac;
pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
pub const FORCE_COPY_BUFFER_SIZE: usize = 512;
embassy_extras::peripherals! {
// RTC
RTC0,
RTC1,
RTC2,
// QSPI
QSPI,
// UARTE
UARTE0,
UARTE1,
// SPI/TWI
TWISPI0,
TWISPI1,
SPI2,
SPI3,
// SAADC
SAADC,
// TIMER
TIMER0,
TIMER1,
TIMER2,
TIMER3,
TIMER4,
// GPIOTE
GPIOTE,
GPIOTE_CH0,
GPIOTE_CH1,
GPIOTE_CH2,
GPIOTE_CH3,
GPIOTE_CH4,
GPIOTE_CH5,
GPIOTE_CH6,
GPIOTE_CH7,
// PPI
PPI_CH0,
PPI_CH1,
PPI_CH2,
PPI_CH3,
PPI_CH4,
PPI_CH5,
PPI_CH6,
PPI_CH7,
PPI_CH8,
PPI_CH9,
PPI_CH10,
PPI_CH11,
PPI_CH12,
PPI_CH13,
PPI_CH14,
PPI_CH15,
PPI_CH16,
PPI_CH17,
PPI_CH18,
PPI_CH19,
PPI_CH20,
PPI_CH21,
PPI_CH22,
PPI_CH23,
PPI_CH24,
PPI_CH25,
PPI_CH26,
PPI_CH27,
PPI_CH28,
PPI_CH29,
PPI_CH30,
PPI_CH31,
PPI_GROUP0,
PPI_GROUP1,
PPI_GROUP2,
PPI_GROUP3,
PPI_GROUP4,
PPI_GROUP5,
// GPIO port 0
P0_00,
P0_01,
P0_02,
P0_03,
P0_04,
P0_05,
P0_06,
P0_07,
P0_08,
P0_09,
P0_10,
P0_11,
P0_12,
P0_13,
P0_14,
P0_15,
P0_16,
P0_17,
P0_18,
P0_19,
P0_20,
P0_21,
P0_22,
P0_23,
P0_24,
P0_25,
P0_26,
P0_27,
P0_28,
P0_29,
P0_30,
P0_31,
// GPIO port 1
P1_00,
P1_01,
P1_02,
P1_03,
P1_04,
P1_05,
P1_06,
P1_07,
P1_08,
P1_09,
P1_10,
P1_11,
P1_12,
P1_13,
P1_14,
P1_15,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
impl_uarte!(UARTE1, UARTE1, UARTE1);
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
impl_spim!(SPI3, SPIM3, SPIM3);
impl_timer!(TIMER0, TIMER0, TIMER0);
impl_timer!(TIMER1, TIMER1, TIMER1);
impl_timer!(TIMER2, TIMER2, TIMER2);
impl_timer!(TIMER3, TIMER3, TIMER3, extended);
impl_timer!(TIMER4, TIMER4, TIMER4, extended);
impl_qspi!(QSPI, QSPI, QSPI);
impl_pin!(P0_00, 0, 0);
impl_pin!(P0_01, 0, 1);
impl_pin!(P0_02, 0, 2);
impl_pin!(P0_03, 0, 3);
impl_pin!(P0_04, 0, 4);
impl_pin!(P0_05, 0, 5);
impl_pin!(P0_06, 0, 6);
impl_pin!(P0_07, 0, 7);
impl_pin!(P0_08, 0, 8);
impl_pin!(P0_09, 0, 9);
impl_pin!(P0_10, 0, 10);
impl_pin!(P0_11, 0, 11);
impl_pin!(P0_12, 0, 12);
impl_pin!(P0_13, 0, 13);
impl_pin!(P0_14, 0, 14);
impl_pin!(P0_15, 0, 15);
impl_pin!(P0_16, 0, 16);
impl_pin!(P0_17, 0, 17);
impl_pin!(P0_18, 0, 18);
impl_pin!(P0_19, 0, 19);
impl_pin!(P0_20, 0, 20);
impl_pin!(P0_21, 0, 21);
impl_pin!(P0_22, 0, 22);
impl_pin!(P0_23, 0, 23);
impl_pin!(P0_24, 0, 24);
impl_pin!(P0_25, 0, 25);
impl_pin!(P0_26, 0, 26);
impl_pin!(P0_27, 0, 27);
impl_pin!(P0_28, 0, 28);
impl_pin!(P0_29, 0, 29);
impl_pin!(P0_30, 0, 30);
impl_pin!(P0_31, 0, 31);
impl_pin!(P1_00, 1, 0);
impl_pin!(P1_01, 1, 1);
impl_pin!(P1_02, 1, 2);
impl_pin!(P1_03, 1, 3);
impl_pin!(P1_04, 1, 4);
impl_pin!(P1_05, 1, 5);
impl_pin!(P1_06, 1, 6);
impl_pin!(P1_07, 1, 7);
impl_pin!(P1_08, 1, 8);
impl_pin!(P1_09, 1, 9);
impl_pin!(P1_10, 1, 10);
impl_pin!(P1_11, 1, 11);
impl_pin!(P1_12, 1, 12);
impl_pin!(P1_13, 1, 13);
impl_pin!(P1_14, 1, 14);
impl_pin!(P1_15, 1, 15);
pub mod irqs {
use embassy_macros::interrupt_declare as declare;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(I2S);
declare!(FPU);
declare!(USBD);
declare!(UARTE1);
declare!(QSPI);
declare!(CRYPTOCELL);
declare!(PWM3);
declare!(SPIM3);
}

70
embassy-nrf/src/gpio.rs
View file

@ -1,3 +1,5 @@
#![macro_use]
use core::convert::Infallible;
use core::hint::unreachable_unchecked;
use core::marker::PhantomData;
@ -18,7 +20,7 @@ pub enum Port {
Port0,
/// Port 1, only available on some nRF52 MCUs.
#[cfg(any(feature = "52833", feature = "52840"))]
#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
Port1,
}
@ -281,12 +283,12 @@ pub(crate) mod sealed {
#[inline]
fn _pin(&self) -> u8 {
#[cfg(any(feature = "52833", feature = "52840"))]
#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
{
self.pin_port() % 32
}
#[cfg(not(any(feature = "52833", feature = "52840")))]
#[cfg(not(any(feature = "nrf52833", feature = "nrf52840")))]
{
self.pin_port()
}
@ -297,7 +299,7 @@ pub(crate) mod sealed {
unsafe {
match self.pin_port() / 32 {
0 => &*pac::P0::ptr(),
#[cfg(any(feature = "52833", feature = "52840"))]
#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
1 => &*pac::P1::ptr(),
_ => unreachable_unchecked(),
}
@ -341,7 +343,7 @@ pub trait Pin: sealed::Pin + Sized {
fn port(&self) -> Port {
match self.pin_port() / 32 {
0 => Port::Port0,
#[cfg(any(feature = "52833", feature = "52840"))]
#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
1 => Port::Port1,
_ => unsafe { unreachable_unchecked() },
}
@ -488,8 +490,8 @@ impl OptionalPin for NoPin {
macro_rules! impl_pin {
($type:ident, $port_num:expr, $pin_num:expr) => {
impl Pin for peripherals::$type {}
impl sealed::Pin for peripherals::$type {
impl crate::gpio::Pin for peripherals::$type {}
impl crate::gpio::sealed::Pin for peripherals::$type {
#[inline]
fn pin_port(&self) -> u8 {
$port_num * 32 + $pin_num
@ -497,57 +499,3 @@ macro_rules! impl_pin {
}
};
}
impl_pin!(P0_00, 0, 0);
impl_pin!(P0_01, 0, 1);
impl_pin!(P0_02, 0, 2);
impl_pin!(P0_03, 0, 3);
impl_pin!(P0_04, 0, 4);
impl_pin!(P0_05, 0, 5);
impl_pin!(P0_06, 0, 6);
impl_pin!(P0_07, 0, 7);
impl_pin!(P0_08, 0, 8);
impl_pin!(P0_09, 0, 9);
impl_pin!(P0_10, 0, 10);
impl_pin!(P0_11, 0, 11);
impl_pin!(P0_12, 0, 12);
impl_pin!(P0_13, 0, 13);
impl_pin!(P0_14, 0, 14);
impl_pin!(P0_15, 0, 15);
impl_pin!(P0_16, 0, 16);
impl_pin!(P0_17, 0, 17);
impl_pin!(P0_18, 0, 18);
impl_pin!(P0_19, 0, 19);
impl_pin!(P0_20, 0, 20);
impl_pin!(P0_21, 0, 21);
impl_pin!(P0_22, 0, 22);
impl_pin!(P0_23, 0, 23);
impl_pin!(P0_24, 0, 24);
impl_pin!(P0_25, 0, 25);
impl_pin!(P0_26, 0, 26);
impl_pin!(P0_27, 0, 27);
impl_pin!(P0_28, 0, 28);
impl_pin!(P0_29, 0, 29);
impl_pin!(P0_30, 0, 30);
impl_pin!(P0_31, 0, 31);
#[cfg(any(feature = "52833", feature = "52840"))]
mod _p1 {
use super::*;
impl_pin!(P1_00, 1, 0);
impl_pin!(P1_01, 1, 1);
impl_pin!(P1_02, 1, 2);
impl_pin!(P1_03, 1, 3);
impl_pin!(P1_04, 1, 4);
impl_pin!(P1_05, 1, 5);
impl_pin!(P1_06, 1, 6);
impl_pin!(P1_07, 1, 7);
impl_pin!(P1_08, 1, 8);
impl_pin!(P1_09, 1, 9);
impl_pin!(P1_10, 1, 10);
impl_pin!(P1_11, 1, 11);
impl_pin!(P1_12, 1, 12);
impl_pin!(P1_13, 1, 13);
impl_pin!(P1_14, 1, 14);
impl_pin!(P1_15, 1, 15);
}

16
embassy-nrf/src/gpiote.rs
View file

@ -17,9 +17,9 @@ use crate::{interrupt, peripherals};
pub const CHANNEL_COUNT: usize = 8;
#[cfg(any(feature = "52833", feature = "52840"))]
#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
pub const PIN_COUNT: usize = 48;
#[cfg(not(any(feature = "52833", feature = "52840")))]
#[cfg(not(any(feature = "nrf52833", feature = "nrf52840")))]
pub const PIN_COUNT: usize = 32;
const NEW_AW: AtomicWaker = AtomicWaker::new();
@ -49,9 +49,9 @@ pub struct Initialized {
}
pub fn initialize(_gpiote: peripherals::GPIOTE, irq: interrupt::GPIOTE) -> Initialized {
#[cfg(any(feature = "52833", feature = "52840"))]
#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
let ports = unsafe { &[&*pac::P0::ptr(), &*pac::P1::ptr()] };
#[cfg(not(any(feature = "52833", feature = "52840")))]
#[cfg(not(any(feature = "nrf52833", feature = "nrf52840")))]
let ports = unsafe { &[&*pac::P0::ptr()] };
for &p in ports {
@ -85,9 +85,9 @@ unsafe fn on_irq(_ctx: *mut ()) {
if g.events_port.read().bits() != 0 {
g.events_port.write(|w| w);
#[cfg(any(feature = "52833", feature = "52840"))]
#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
let ports = &[&*pac::P0::ptr(), &*pac::P1::ptr()];
#[cfg(not(any(feature = "52833", feature = "52840")))]
#[cfg(not(any(feature = "nrf52833", feature = "nrf52840")))]
let ports = &[&*pac::P0::ptr()];
for (port, &p) in ports.iter().enumerate() {
@ -149,7 +149,7 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
InputChannelPolarity::None => w.mode().event().polarity().none(),
InputChannelPolarity::Toggle => w.mode().event().polarity().toggle(),
};
#[cfg(any(feature = "52833", feature = "52840"))]
#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
w.port().bit(match pin.pin.port() {
Port::Port0 => false,
Port::Port1 => true,
@ -237,7 +237,7 @@ impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> {
OutputChannelPolarity::Clear => w.polarity().hi_to_lo(),
OutputChannelPolarity::Toggle => w.polarity().toggle(),
};
#[cfg(any(feature = "52833", feature = "52840"))]
#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
w.port().bit(match pin.pin.port() {
Port::Port0 => false,
Port::Port1 => true,

210
embassy-nrf/src/interrupt.rs
View file

@ -1,210 +0,0 @@
//! Interrupt management
//!
//! This module implements an API for managing interrupts compatible with
//! nrf_softdevice::interrupt. Intended for switching between the two at compile-time.
// Re-exports
pub use embassy::interrupt::{declare, take, Interrupt};
pub use embassy_extras::interrupt::Priority3 as Priority;
#[cfg(feature = "52810")]
mod irqs {
use super::*;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(TWIM0_TWIS0_TWI0);
declare!(SPIM0_SPIS0_SPI0);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2);
declare!(SWI3);
declare!(SWI4);
declare!(SWI5);
declare!(PWM0);
declare!(PDM);
}
#[cfg(feature = "52811")]
mod irqs {
use super::*;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1);
declare!(SPIM0_SPIS0_SPI0);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2);
declare!(SWI3);
declare!(SWI4);
declare!(SWI5);
declare!(PWM0);
declare!(PDM);
}
#[cfg(feature = "52832")]
mod irqs {
use super::*;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(I2S);
declare!(FPU);
}
#[cfg(feature = "52833")]
mod irqs {
use super::*;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(I2S);
declare!(FPU);
declare!(USBD);
declare!(UARTE1);
declare!(PWM3);
declare!(SPIM3);
}
#[cfg(feature = "52840")]
mod irqs {
use super::*;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(I2S);
declare!(FPU);
declare!(USBD);
declare!(UARTE1);
declare!(QSPI);
declare!(CRYPTOCELL);
declare!(PWM3);
declare!(SPIM3);
}
pub use irqs::*;

278
embassy-nrf/src/lib.rs
View file

@ -7,257 +7,67 @@
#![allow(incomplete_features)]
#[cfg(not(any(
feature = "52810",
feature = "52811",
feature = "52832",
feature = "52833",
feature = "52840",
feature = "nrf51",
feature = "nrf52805",
feature = "nrf52810",
feature = "nrf52811",
feature = "nrf52820",
feature = "nrf52832",
feature = "nrf52833",
feature = "nrf52840",
feature = "nrf5340-app",
feature = "nrf5340-net",
feature = "nrf9160",
)))]
compile_error!("No chip feature activated. You must activate exactly one of the following features: 52810, 52811, 52832, 52833, 52840");
#[cfg(any(
all(feature = "52810", feature = "52811"),
all(feature = "52810", feature = "52832"),
all(feature = "52810", feature = "52833"),
all(feature = "52810", feature = "52840"),
all(feature = "52811", feature = "52832"),
all(feature = "52811", feature = "52833"),
all(feature = "52811", feature = "52840"),
all(feature = "52832", feature = "52833"),
all(feature = "52832", feature = "52840"),
all(feature = "52833", feature = "52840"),
))]
compile_error!("Multile chip features activated. You must activate exactly one of the following features: 52810, 52811, 52832, 52833, 52840");
#[cfg(feature = "52810")]
pub use nrf52810_pac as pac;
#[cfg(feature = "52811")]
pub use nrf52811_pac as pac;
#[cfg(feature = "52832")]
pub use nrf52832_pac as pac;
#[cfg(feature = "52833")]
pub use nrf52833_pac as pac;
#[cfg(feature = "52840")]
pub use nrf52840_pac as pac;
/// Length of Nordic EasyDMA differs for MCUs
#[cfg(any(
feature = "52810",
feature = "52811",
feature = "52832",
feature = "51"
))]
pub mod target_constants {
// NRF52832 8 bits1..0xFF
pub const EASY_DMA_SIZE: usize = 255;
// Easy DMA can only read from data ram
pub const SRAM_LOWER: usize = 0x2000_0000;
pub const SRAM_UPPER: usize = 0x3000_0000;
}
#[cfg(any(feature = "52840", feature = "52833", feature = "9160"))]
pub mod target_constants {
// NRF52840 and NRF9160 16 bits 1..0xFFFF
pub const EASY_DMA_SIZE: usize = 65535;
// Limits for Easy DMA - it can only read from data ram
pub const SRAM_LOWER: usize = 0x2000_0000;
pub const SRAM_UPPER: usize = 0x3000_0000;
}
/// Does this slice reside entirely within RAM?
pub(crate) fn slice_in_ram(slice: &[u8]) -> bool {
let ptr = slice.as_ptr() as usize;
ptr >= target_constants::SRAM_LOWER && (ptr + slice.len()) < target_constants::SRAM_UPPER
}
/// Return an error if slice is not in RAM.
#[cfg(not(feature = "51"))]
pub(crate) fn slice_in_ram_or<T>(slice: &[u8], err: T) -> Result<(), T> {
if slice.len() == 0 || slice_in_ram(slice) {
Ok(())
} else {
Err(err)
}
}
compile_error!("No chip feature activated. You must activate exactly one of the following features: nrf52810, nrf52811, nrf52832, nrf52833, nrf52840");
// This mod MUST go first, so that the others see its macros.
pub(crate) mod fmt;
pub(crate) mod util;
pub mod buffered_uarte;
pub mod gpio;
pub mod gpiote;
pub mod interrupt;
pub mod ppi;
#[cfg(feature = "52840")]
#[cfg(feature = "nrf52840")]
pub mod qspi;
pub mod rtc;
#[cfg(not(feature = "nrf52820"))]
pub mod saadc;
pub mod spim;
pub mod system;
pub mod timer;
pub mod uarte;
embassy_extras::peripherals! {
// RTC
RTC0,
RTC1,
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
RTC2,
// This mod MUST go last, so that it sees all the `impl_foo!` macros
#[cfg(feature = "nrf52805")]
#[path = "chips/nrf52805.rs"]
mod chip;
#[cfg(feature = "nrf52810")]
#[path = "chips/nrf52810.rs"]
mod chip;
#[cfg(feature = "nrf52811")]
#[path = "chips/nrf52811.rs"]
mod chip;
#[cfg(feature = "nrf52820")]
#[path = "chips/nrf52820.rs"]
mod chip;
#[cfg(feature = "nrf52832")]
#[path = "chips/nrf52832.rs"]
mod chip;
#[cfg(feature = "nrf52833")]
#[path = "chips/nrf52833.rs"]
mod chip;
#[cfg(feature = "nrf52840")]
#[path = "chips/nrf52840.rs"]
mod chip;
// QSPI
#[cfg(feature = "52840")]
QSPI,
pub(crate) use chip::pac;
pub use chip::{peripherals, Peripherals};
// UARTE
UARTE0,
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
UARTE1,
// SPIM
// TODO this is actually shared with SPI, SPIM, SPIS, TWI, TWIS, TWIS.
// When they're all implemented, they should be only one peripheral here.
SPIM0,
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
SPIM1,
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
SPIM2,
#[cfg(any(feature = "52833", feature = "52840"))]
SPIM3,
// SAADC
SAADC,
// TIMER
TIMER0,
TIMER1,
TIMER2,
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
TIMER3,
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
TIMER4,
// GPIOTE
GPIOTE,
GPIOTE_CH0,
GPIOTE_CH1,
GPIOTE_CH2,
GPIOTE_CH3,
GPIOTE_CH4,
GPIOTE_CH5,
GPIOTE_CH6,
GPIOTE_CH7,
// PPI
PPI_CH0,
PPI_CH1,
PPI_CH2,
PPI_CH3,
PPI_CH4,
PPI_CH5,
PPI_CH6,
PPI_CH7,
PPI_CH8,
PPI_CH9,
PPI_CH10,
PPI_CH11,
PPI_CH12,
PPI_CH13,
PPI_CH14,
PPI_CH15,
#[cfg(not(feature = "51"))]
PPI_CH16,
#[cfg(not(feature = "51"))]
PPI_CH17,
#[cfg(not(feature = "51"))]
PPI_CH18,
#[cfg(not(feature = "51"))]
PPI_CH19,
PPI_CH20,
PPI_CH21,
PPI_CH22,
PPI_CH23,
PPI_CH24,
PPI_CH25,
PPI_CH26,
PPI_CH27,
PPI_CH28,
PPI_CH29,
PPI_CH30,
PPI_CH31,
PPI_GROUP0,
PPI_GROUP1,
PPI_GROUP2,
PPI_GROUP3,
#[cfg(not(feature = "51"))]
PPI_GROUP4,
#[cfg(not(feature = "51"))]
PPI_GROUP5,
// GPIO port 0
P0_00,
P0_01,
P0_02,
P0_03,
P0_04,
P0_05,
P0_06,
P0_07,
P0_08,
P0_09,
P0_10,
P0_11,
P0_12,
P0_13,
P0_14,
P0_15,
P0_16,
P0_17,
P0_18,
P0_19,
P0_20,
P0_21,
P0_22,
P0_23,
P0_24,
P0_25,
P0_26,
P0_27,
P0_28,
P0_29,
P0_30,
P0_31,
// GPIO port 1
#[cfg(any(feature = "52833", feature = "52840"))]
P1_00,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_01,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_02,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_03,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_04,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_05,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_06,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_07,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_08,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_09,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_10,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_11,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_12,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_13,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_14,
#[cfg(any(feature = "52833", feature = "52840"))]
P1_15,
pub mod interrupt {
pub use crate::chip::irqs::*;
pub use cortex_m::interrupt::{CriticalSection, Mutex};
pub use embassy::interrupt::{declare, take, Interrupt};
pub use embassy_extras::interrupt::Priority3 as Priority;
}

22
embassy-nrf/src/qspi.rs
View file

@ -1,3 +1,5 @@
#![macro_use]
use core::future::Future;
use core::marker::PhantomData;
use core::task::Poll;
@ -361,7 +363,7 @@ impl<'d, T: Instance> Flash for Qspi<'d, T> {
}
}
mod sealed {
pub(crate) mod sealed {
use super::*;
pub struct State {
@ -385,21 +387,19 @@ pub trait Instance: sealed::Instance + 'static {
type Interrupt: Interrupt;
}
macro_rules! impl_instance {
($type:ident, $irq:ident) => {
impl sealed::Instance for peripherals::$type {
macro_rules! impl_qspi {
($type:ident, $pac_type:ident, $irq:ident) => {
impl crate::qspi::sealed::Instance for peripherals::$type {
fn regs() -> &'static pac::qspi::RegisterBlock {
unsafe { &*pac::$type::ptr() }
unsafe { &*pac::$pac_type::ptr() }
}
fn state() -> &'static sealed::State {
static STATE: sealed::State = sealed::State::new();
fn state() -> &'static crate::qspi::sealed::State {
static STATE: crate::qspi::sealed::State = crate::qspi::sealed::State::new();
&STATE
}
}
impl Instance for peripherals::$type {
type Interrupt = interrupt::$irq;
impl crate::qspi::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
}
};
}
impl_instance!(QSPI, QSPI);

47
embassy-nrf/src/spim.rs
View file

@ -1,3 +1,5 @@
#![macro_use]
use core::future::Future;
use core::marker::PhantomData;
use core::sync::atomic::{compiler_fence, Ordering};
@ -12,7 +14,7 @@ use traits::spi::FullDuplex;
use crate::gpio::sealed::Pin as _;
use crate::gpio::{OptionalPin, Pin as GpioPin};
use crate::interrupt::{self, Interrupt};
use crate::{pac, peripherals, slice_in_ram_or};
use crate::{pac, peripherals, util::slice_in_ram_or};
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
pub use pac::spim0::frequency::FREQUENCY_A as Frequency;
@ -33,12 +35,23 @@ pub struct Spim<'d, T: Instance> {
phantom: PhantomData<&'d mut T>,
}
#[non_exhaustive]
pub struct Config {
pub frequency: Frequency,
pub mode: Mode,
pub orc: u8,
}
impl Default for Config {
fn default() -> Self {
Self {
frequency: Frequency::M1,
mode: MODE_0,
orc: 0x00,
}
}
}
impl<'d, T: Instance> Spim<'d, T> {
pub fn new(
spim: impl Unborrow<Target = T> + 'd,
@ -315,7 +328,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spim<'d, T> {
}
}
mod sealed {
pub(crate) mod sealed {
use super::*;
pub struct State {
@ -340,33 +353,19 @@ pub trait Instance: sealed::Instance + 'static {
type Interrupt: Interrupt;
}
macro_rules! impl_instance {
($type:ident, $irq:ident) => {
impl sealed::Instance for peripherals::$type {
macro_rules! impl_spim {
($type:ident, $pac_type:ident, $irq:ident) => {
impl crate::spim::sealed::Instance for peripherals::$type {
fn regs() -> &'static pac::spim0::RegisterBlock {
unsafe { &*pac::$type::ptr() }
unsafe { &*pac::$pac_type::ptr() }
}
fn state() -> &'static sealed::State {
static STATE: sealed::State = sealed::State::new();
fn state() -> &'static crate::spim::sealed::State {
static STATE: crate::spim::sealed::State = crate::spim::sealed::State::new();
&STATE
}
}
impl Instance for peripherals::$type {
type Interrupt = interrupt::$irq;
impl crate::spim::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
}
};
}
#[cfg(feature = "52810")]
impl_instance!(SPIM0, SPIM0_SPIS0_SPI0);
#[cfg(not(feature = "52810"))]
impl_instance!(SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
impl_instance!(SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
impl_instance!(SPIM2, SPIM2_SPIS2_SPI2);
#[cfg(any(feature = "52833", feature = "52840"))]
impl_instance!(SPIM3, SPIM3);

34
embassy-nrf/src/timer.rs
View file

@ -1,8 +1,10 @@
#![macro_use]
use embassy::interrupt::Interrupt;
use crate::{interrupt, pac, peripherals};
use crate::pac;
mod sealed {
pub(crate) mod sealed {
use super::*;
pub trait Instance {
@ -16,28 +18,20 @@ pub trait Instance: sealed::Instance + 'static {
}
pub trait ExtendedInstance: Instance + sealed::ExtendedInstance {}
macro_rules! impl_instance {
($type:ident, $irq:ident) => {
impl sealed::Instance for peripherals::$type {
macro_rules! impl_timer {
($type:ident, $pac_type:ident, $irq:ident) => {
impl crate::timer::sealed::Instance for peripherals::$type {
fn regs(&self) -> &pac::timer0::RegisterBlock {
unsafe { &*(pac::$type::ptr() as *const pac::timer0::RegisterBlock) }
unsafe { &*(pac::$pac_type::ptr() as *const pac::timer0::RegisterBlock) }
}
}
impl Instance for peripherals::$type {
type Interrupt = interrupt::$irq;
impl crate::timer::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
}
};
($type:ident, $irq:ident, extended) => {
impl_instance!($type, $irq);
impl sealed::ExtendedInstance for peripherals::$type {}
impl ExtendedInstance for peripherals::$type {}
($type:ident, $pac_type:ident, $irq:ident, extended) => {
impl_timer!($type, $pac_type, $irq);
impl crate::timer::sealed::ExtendedInstance for peripherals::$type {}
impl crate::timer::ExtendedInstance for peripherals::$type {}
};
}
impl_instance!(TIMER0, TIMER0);
impl_instance!(TIMER1, TIMER1);
impl_instance!(TIMER2, TIMER2);
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
impl_instance!(TIMER3, TIMER3, extended);
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
impl_instance!(TIMER4, TIMER4, extended);

26
embassy-nrf/src/uarte.rs
View file

@ -1,3 +1,5 @@
#![macro_use]
//! Async UART
use core::future::Future;
@ -10,6 +12,7 @@ use embassy::util::{AtomicWaker, OnDrop, Unborrow};
use embassy_extras::unborrow;
use futures::future::poll_fn;
use crate::chip::EASY_DMA_SIZE;
use crate::fmt::{assert, panic, *};
use crate::gpio::sealed::Pin as _;
use crate::gpio::{OptionalPin as GpioOptionalPin, Pin as GpioPin};
@ -18,7 +21,6 @@ use crate::interrupt::Interrupt;
use crate::pac;
use crate::peripherals;
use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task};
use crate::target_constants::EASY_DMA_SIZE;
use crate::timer::Instance as TimerInstance;
// Re-export SVD variants to allow user to directly set values.
@ -445,7 +447,7 @@ impl<'d, U: Instance, T: TimerInstance> Write for UarteWithIdle<'d, U, T> {
}
}
mod sealed {
pub(crate) mod sealed {
use super::*;
pub struct State {
@ -471,23 +473,19 @@ pub trait Instance: sealed::Instance + 'static {
type Interrupt: Interrupt;
}
macro_rules! impl_instance {
($type:ident, $irq:ident) => {
impl sealed::Instance for peripherals::$type {
macro_rules! impl_uarte {
($type:ident, $pac_type:ident, $irq:ident) => {
impl crate::uarte::sealed::Instance for peripherals::$type {
fn regs() -> &'static pac::uarte0::RegisterBlock {
unsafe { &*pac::$type::ptr() }
unsafe { &*pac::$pac_type::ptr() }
}
fn state() -> &'static sealed::State {
static STATE: sealed::State = sealed::State::new();
fn state() -> &'static crate::uarte::sealed::State {
static STATE: crate::uarte::sealed::State = crate::uarte::sealed::State::new();
&STATE
}
}
impl Instance for peripherals::$type {
type Interrupt = interrupt::$irq;
impl crate::uarte::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
}
};
}
impl_instance!(UARTE0, UARTE0_UART0);
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
impl_instance!(UARTE1, UARTE1);

18
embassy-nrf/src/util.rs Normal file
View file

@ -0,0 +1,18 @@
const SRAM_LOWER: usize = 0x2000_0000;
const SRAM_UPPER: usize = 0x3000_0000;
/// Does this slice reside entirely within RAM?
pub(crate) fn slice_in_ram(slice: &[u8]) -> bool {
let ptr = slice.as_ptr() as usize;
ptr >= SRAM_LOWER && (ptr + slice.len()) < SRAM_UPPER
}
/// Return an error if slice is not in RAM.
#[cfg(not(feature = "51"))]
pub(crate) fn slice_in_ram_or<T>(slice: &[u8], err: T) -> Result<(), T> {
if slice.len() == 0 || slice_in_ram(slice) {
Ok(())
} else {
Err(err)
}
}