consolidate ExtiPin into stm32 package
This commit is contained in:
xoviat
parent
6719da3b6e
commit
bf39822092
5 changed files with 296 additions and 324 deletions
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@ -3,35 +3,33 @@ use core::mem;
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use core::pin::Pin;
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use cortex_m;
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use embassy::traits::gpio::{WaitForFallingEdge, WaitForRisingEdge};
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use crate::hal::gpio;
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use embassy::traits::gpio::{
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WaitForAnyEdge, WaitForFallingEdge, WaitForHigh, WaitForLow, WaitForRisingEdge,
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};
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use embassy::util::InterruptFuture;
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use crate::hal::gpio;
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use crate::hal::gpio::Edge;
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use crate::hal::syscfg::SysCfg;
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use crate::pac::EXTI;
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use embedded_hal::digital::v2 as digital;
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use crate::interrupt;
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pub struct ExtiPin<T: gpio::ExtiPin + WithInterrupt> {
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pub struct ExtiPin<T: Instance> {
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pin: T,
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interrupt: T::Interrupt,
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}
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impl<T: gpio::ExtiPin + WithInterrupt> ExtiPin<T> {
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impl<T: Instance> ExtiPin<T> {
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pub fn new(mut pin: T, interrupt: T::Interrupt) -> Self {
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let mut syscfg: SysCfg = unsafe { mem::transmute(()) };
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cortex_m::interrupt::free(|_| {
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pin.make_interrupt_source(&mut syscfg);
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pin.make_source();
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});
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Self { pin, interrupt }
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}
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}
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impl<T: gpio::ExtiPin + WithInterrupt + digital::OutputPin> digital::OutputPin for ExtiPin<T> {
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impl<T: Instance + digital::OutputPin> digital::OutputPin for ExtiPin<T> {
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type Error = T::Error;
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fn set_low(&mut self) -> Result<(), Self::Error> {
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@ -43,9 +41,7 @@ impl<T: gpio::ExtiPin + WithInterrupt + digital::OutputPin> digital::OutputPin f
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}
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}
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impl<T: gpio::ExtiPin + WithInterrupt + digital::StatefulOutputPin> digital::StatefulOutputPin
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for ExtiPin<T>
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{
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impl<T: Instance + digital::StatefulOutputPin> digital::StatefulOutputPin for ExtiPin<T> {
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fn is_set_low(&self) -> Result<bool, Self::Error> {
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self.pin.is_set_low()
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}
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@ -55,9 +51,7 @@ impl<T: gpio::ExtiPin + WithInterrupt + digital::StatefulOutputPin> digital::Sta
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}
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}
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impl<T: gpio::ExtiPin + WithInterrupt + digital::ToggleableOutputPin> digital::ToggleableOutputPin
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for ExtiPin<T>
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{
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impl<T: Instance + digital::ToggleableOutputPin> digital::ToggleableOutputPin for ExtiPin<T> {
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type Error = T::Error;
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fn toggle(&mut self) -> Result<(), Self::Error> {
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@ -65,7 +59,7 @@ impl<T: gpio::ExtiPin + WithInterrupt + digital::ToggleableOutputPin> digital::T
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}
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}
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impl<T: gpio::ExtiPin + WithInterrupt + digital::InputPin> digital::InputPin for ExtiPin<T> {
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impl<T: Instance + digital::InputPin> digital::InputPin for ExtiPin<T> {
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type Error = T::Error;
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fn is_high(&self) -> Result<bool, Self::Error> {
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@ -77,6 +71,73 @@ impl<T: gpio::ExtiPin + WithInterrupt + digital::InputPin> digital::InputPin for
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}
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}
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impl<T: Instance + digital::InputPin + 'static> ExtiPin<T> {
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fn wait_for_state<'a>(self: Pin<&'a mut Self>, state: bool) -> impl Future<Output = ()> + 'a {
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let s = unsafe { self.get_unchecked_mut() };
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s.pin.clear_pending_bit();
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async move {
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let fut = InterruptFuture::new(&mut s.interrupt);
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let pin = &mut s.pin;
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cortex_m::interrupt::free(|_| {
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pin.trigger_edge(if state {
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EdgeOption::Rising
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} else {
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EdgeOption::Falling
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});
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});
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if (state && s.pin.is_high().unwrap_or(false))
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|| (!state && s.pin.is_low().unwrap_or(false))
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{
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return;
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}
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fut.await;
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s.pin.clear_pending_bit();
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}
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}
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}
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impl<T: Instance + 'static> ExtiPin<T> {
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fn wait_for_edge<'a>(
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self: Pin<&'a mut Self>,
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state: EdgeOption,
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) -> impl Future<Output = ()> + 'a {
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let s = unsafe { self.get_unchecked_mut() };
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s.pin.clear_pending_bit();
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async move {
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let fut = InterruptFuture::new(&mut s.interrupt);
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let pin = &mut s.pin;
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cortex_m::interrupt::free(|_| {
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pin.trigger_edge(state);
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});
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fut.await;
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s.pin.clear_pending_bit();
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}
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}
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}
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impl<T: Instance + digital::InputPin + 'static> WaitForHigh for ExtiPin<T> {
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type Future<'a> = impl Future<Output = ()> + 'a;
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fn wait_for_high<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
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self.wait_for_state(true)
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}
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}
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impl<T: Instance + digital::InputPin + 'static> WaitForLow for ExtiPin<T> {
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type Future<'a> = impl Future<Output = ()> + 'a;
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fn wait_for_low<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
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self.wait_for_state(false)
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}
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}
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/*
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Irq Handler Description
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EXTI0_IRQn EXTI0_IRQHandler Handler for pins connected to line 0
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@ -88,49 +149,27 @@ impl<T: gpio::ExtiPin + WithInterrupt + digital::InputPin> digital::InputPin for
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EXTI15_10_IRQn EXTI15_10_IRQHandler Handler for pins connected to line 10 to 15
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*/
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impl<T: gpio::ExtiPin + WithInterrupt + 'static> WaitForRisingEdge for ExtiPin<T> {
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impl<T: Instance + 'static> WaitForRisingEdge for ExtiPin<T> {
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type Future<'a> = impl Future<Output = ()> + 'a;
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fn wait_for_rising_edge<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
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let s = unsafe { self.get_unchecked_mut() };
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s.pin.clear_interrupt_pending_bit();
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async move {
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let fut = InterruptFuture::new(&mut s.interrupt);
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let pin = &mut s.pin;
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cortex_m::interrupt::free(|_| {
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let mut exti: EXTI = unsafe { mem::transmute(()) };
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pin.trigger_on_edge(&mut exti, Edge::RISING);
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pin.enable_interrupt(&mut exti);
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});
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fut.await;
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s.pin.clear_interrupt_pending_bit();
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}
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self.wait_for_edge(EdgeOption::Rising)
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}
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}
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impl<T: gpio::ExtiPin + WithInterrupt + 'static> WaitForFallingEdge for ExtiPin<T> {
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impl<T: Instance + 'static> WaitForFallingEdge for ExtiPin<T> {
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type Future<'a> = impl Future<Output = ()> + 'a;
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fn wait_for_falling_edge<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
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let s = unsafe { self.get_unchecked_mut() };
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self.wait_for_edge(EdgeOption::Falling)
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}
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}
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s.pin.clear_interrupt_pending_bit();
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async move {
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let fut = InterruptFuture::new(&mut s.interrupt);
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let pin = &mut s.pin;
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cortex_m::interrupt::free(|_| {
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let mut exti: EXTI = unsafe { mem::transmute(()) };
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impl<T: Instance + 'static> WaitForAnyEdge for ExtiPin<T> {
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type Future<'a> = impl Future<Output = ()> + 'a;
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pin.trigger_on_edge(&mut exti, Edge::FALLING);
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pin.enable_interrupt(&mut exti);
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});
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fut.await;
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s.pin.clear_interrupt_pending_bit();
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}
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fn wait_for_any_edge<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
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self.wait_for_edge(EdgeOption::RisingFalling)
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}
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}
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@ -138,10 +177,23 @@ mod private {
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pub trait Sealed {}
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}
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#[derive(Copy, Clone)]
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pub enum EdgeOption {
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Rising,
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Falling,
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RisingFalling,
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}
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pub trait WithInterrupt: private::Sealed {
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type Interrupt: interrupt::Interrupt;
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}
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pub trait Instance: WithInterrupt {
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fn make_source(&mut self);
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fn clear_pending_bit(&mut self);
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fn trigger_edge(&mut self, edge: EdgeOption);
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}
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macro_rules! exti {
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($set:ident, [
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$($INT:ident => $pin:ident,)+
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@ -151,8 +203,90 @@ macro_rules! exti {
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impl<T> WithInterrupt for gpio::$set::$pin<T> {
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type Interrupt = interrupt::$INT;
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}
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)+
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#[cfg(any(
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feature = "stm32f401",
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feature = "stm32f405",
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feature = "stm32f407",
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feature = "stm32f410",
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feature = "stm32f411",
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feature = "stm32f412",
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feature = "stm32f413",
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feature = "stm32f415",
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feature = "stm32f417",
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feature = "stm32f423",
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feature = "stm32f427",
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feature = "stm32f429",
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feature = "stm32f437",
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feature = "stm32f439",
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feature = "stm32f446",
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feature = "stm32f469",
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feature = "stm32f479",
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))]
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impl<T> Instance for gpio::$set::$pin<gpio::Input<T>> {
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fn make_source(&mut self) {
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use crate::hal::{gpio::Edge, gpio::ExtiPin, syscfg::SysCfg};
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use crate::pac::EXTI;
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let mut syscfg: SysCfg = unsafe { mem::transmute(()) };
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self.make_interrupt_source(&mut syscfg);
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}
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fn clear_pending_bit(&mut self) {
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use crate::hal::{gpio::Edge, gpio::ExtiPin, syscfg::SysCfg};
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self.clear_interrupt_pending_bit();
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}
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fn trigger_edge(&mut self, edge: EdgeOption) {
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use crate::hal::{gpio::Edge, gpio::ExtiPin, syscfg::SysCfg};
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use crate::pac::EXTI;
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let mut exti: EXTI = unsafe { mem::transmute(()) };
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let edge = match edge {
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EdgeOption::Falling => Edge::FALLING,
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EdgeOption::Rising => Edge::RISING,
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EdgeOption::RisingFalling => Edge::RISING_FALLING,
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};
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self.trigger_on_edge(&mut exti, edge);
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self.enable_interrupt(&mut exti);
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}
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}
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#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
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impl<T> Instance for gpio::$set::$pin<T> {
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fn make_source(&mut self) {}
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fn clear_pending_bit(&mut self) {
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use crate::hal::{
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exti::{Exti, ExtiLine, GpioLine, TriggerEdge},
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syscfg::SYSCFG,
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};
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Exti::unpend(GpioLine::from_raw_line(self.pin_number()).unwrap());
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}
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fn trigger_edge(&mut self, edge: EdgeOption) {
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use crate::hal::{
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exti::{Exti, ExtiLine, GpioLine, TriggerEdge},
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syscfg::SYSCFG,
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};
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use crate::pac::EXTI;
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let edge = match edge {
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EdgeOption::Falling => TriggerEdge::Falling,
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EdgeOption::Rising => TriggerEdge::Rising,
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EdgeOption::RisingFalling => TriggerEdge::Both,
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};
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let exti: EXTI = unsafe { mem::transmute(()) };
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let mut exti = Exti::new(exti);
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let port = self.port();
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let mut syscfg: SYSCFG = unsafe { mem::transmute(()) };
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let line = GpioLine::from_raw_line(self.pin_number()).unwrap();
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exti.listen_gpio(&mut syscfg, port, line, edge);
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}
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}
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)+
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};
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}
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@ -533,3 +667,111 @@ exti!(gpiok, [
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EXTI9_5 => PK6,
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EXTI9_5 => PK7,
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]);
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#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
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exti!(gpioa, [
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EXTI0_1 => PA0,
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EXTI0_1 => PA1,
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EXTI2_3 => PA2,
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EXTI2_3 => PA3,
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EXTI4_15 => PA4,
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EXTI4_15 => PA5,
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EXTI4_15 => PA6,
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EXTI4_15 => PA7,
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EXTI4_15 => PA8,
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EXTI4_15 => PA9,
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EXTI4_15 => PA10,
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EXTI4_15 => PA11,
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EXTI4_15 => PA12,
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EXTI4_15 => PA13,
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EXTI4_15 => PA14,
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EXTI4_15 => PA15,
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]);
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#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
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exti!(gpiob, [
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EXTI0_1 => PB0,
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EXTI0_1 => PB1,
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EXTI2_3 => PB2,
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EXTI2_3 => PB3,
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EXTI4_15 => PB4,
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EXTI4_15 => PB5,
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EXTI4_15 => PB6,
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EXTI4_15 => PB7,
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EXTI4_15 => PB8,
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EXTI4_15 => PB9,
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EXTI4_15 => PB10,
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EXTI4_15 => PB11,
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EXTI4_15 => PB12,
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EXTI4_15 => PB13,
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EXTI4_15 => PB14,
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EXTI4_15 => PB15,
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]);
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#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
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exti!(gpioc, [
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EXTI0_1 => PC0,
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EXTI0_1 => PC1,
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EXTI2_3 => PC2,
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EXTI2_3 => PC3,
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EXTI4_15 => PC4,
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EXTI4_15 => PC5,
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EXTI4_15 => PC6,
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EXTI4_15 => PC7,
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EXTI4_15 => PC8,
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EXTI4_15 => PC9,
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EXTI4_15 => PC10,
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EXTI4_15 => PC11,
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EXTI4_15 => PC12,
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EXTI4_15 => PC13,
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EXTI4_15 => PC14,
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EXTI4_15 => PC15,
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]);
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#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
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exti!(gpiod, [
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EXTI0_1 => PD0,
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EXTI0_1 => PD1,
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EXTI2_3 => PD2,
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EXTI2_3 => PD3,
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EXTI4_15 => PD4,
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EXTI4_15 => PD5,
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EXTI4_15 => PD6,
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EXTI4_15 => PD7,
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EXTI4_15 => PD8,
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EXTI4_15 => PD9,
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EXTI4_15 => PD10,
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EXTI4_15 => PD11,
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EXTI4_15 => PD12,
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EXTI4_15 => PD13,
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EXTI4_15 => PD14,
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EXTI4_15 => PD15,
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]);
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#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
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exti!(gpioe, [
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EXTI0_1 => PE0,
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EXTI0_1 => PE1,
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EXTI2_3 => PE2,
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EXTI2_3 => PE3,
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EXTI4_15 => PE4,
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EXTI4_15 => PE5,
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EXTI4_15 => PE6,
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EXTI4_15 => PE7,
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EXTI4_15 => PE8,
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EXTI4_15 => PE9,
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EXTI4_15 => PE10,
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EXTI4_15 => PE11,
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EXTI4_15 => PE12,
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EXTI4_15 => PE13,
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EXTI4_15 => PE14,
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EXTI4_15 => PE15,
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]);
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#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
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exti!(gpioh, [
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EXTI0_1 => PH0,
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EXTI0_1 => PH1,
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EXTI4_15 => PH9,
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EXTI4_15 => PH10,
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]);
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@ -32,4 +32,5 @@ pub use {stm32l0xx_hal as hal, stm32l0xx_hal::pac};
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pub mod fmt;
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pub mod exti;
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pub mod interrupt;
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@ -307,11 +307,10 @@ compile_error!(
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"Multile chip features activated. You must activate exactly one of the following features: "
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);
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pub use embassy_stm32::{fmt, hal, interrupt, pac};
|
||||
pub use embassy_stm32::{exti, fmt, hal, interrupt, pac};
|
||||
|
||||
#[cfg(not(any(feature = "stm32f401", feature = "stm32f410", feature = "stm32f411",)))]
|
||||
pub mod can;
|
||||
pub mod exti;
|
||||
#[cfg(not(feature = "stm32f410"))]
|
||||
pub mod qei;
|
||||
pub mod rtc;
|
||||
|
|
|
|||
|
|
@ -1,268 +0,0 @@
|
|||
use core::future::Future;
|
||||
use core::mem;
|
||||
use core::pin::Pin;
|
||||
|
||||
use embassy::traits::gpio::{
|
||||
WaitForAnyEdge, WaitForFallingEdge, WaitForHigh, WaitForLow, WaitForRisingEdge,
|
||||
};
|
||||
use embassy::util::InterruptFuture;
|
||||
|
||||
use crate::hal::{
|
||||
exti::{Exti, ExtiLine, GpioLine, TriggerEdge},
|
||||
gpio,
|
||||
syscfg::SYSCFG,
|
||||
};
|
||||
use crate::interrupt;
|
||||
use crate::pac::EXTI;
|
||||
use embedded_hal::digital::v2::InputPin;
|
||||
|
||||
pub struct ExtiPin<T: PinWithInterrupt> {
|
||||
pin: T,
|
||||
interrupt: T::Interrupt,
|
||||
}
|
||||
|
||||
impl<T: PinWithInterrupt + 'static> ExtiPin<T> {
|
||||
pub fn new(pin: T, interrupt: T::Interrupt) -> ExtiPin<T> {
|
||||
ExtiPin { pin, interrupt }
|
||||
}
|
||||
|
||||
fn wait_for_edge<'a>(
|
||||
self: Pin<&'a mut Self>,
|
||||
edge: TriggerEdge,
|
||||
) -> impl Future<Output = ()> + 'a {
|
||||
let line = self.pin.line();
|
||||
let s = unsafe { self.get_unchecked_mut() };
|
||||
|
||||
Exti::unpend(line);
|
||||
|
||||
async move {
|
||||
let exti: EXTI = unsafe { mem::transmute(()) };
|
||||
let mut exti = Exti::new(exti);
|
||||
|
||||
let fut = InterruptFuture::new(&mut s.interrupt);
|
||||
|
||||
let port = s.pin.port();
|
||||
cortex_m::interrupt::free(|_| {
|
||||
let mut syscfg: SYSCFG = unsafe { mem::transmute(()) };
|
||||
exti.listen_gpio(&mut syscfg, port, line, edge);
|
||||
});
|
||||
|
||||
fut.await;
|
||||
|
||||
Exti::unpend(line);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: InputPin + PinWithInterrupt + 'static> ExtiPin<T> {
|
||||
fn wait_for_state<'a>(self: Pin<&'a mut Self>, state: bool) -> impl Future<Output = ()> + 'a {
|
||||
let line = self.pin.line();
|
||||
let s = unsafe { self.get_unchecked_mut() };
|
||||
|
||||
Exti::unpend(line);
|
||||
|
||||
async move {
|
||||
let exti: EXTI = unsafe { mem::transmute(()) };
|
||||
let mut exti = Exti::new(exti);
|
||||
|
||||
let fut = InterruptFuture::new(&mut s.interrupt);
|
||||
|
||||
let port = s.pin.port();
|
||||
cortex_m::interrupt::free(|_| {
|
||||
let mut syscfg: SYSCFG = unsafe { mem::transmute(()) };
|
||||
let edge = if state {
|
||||
TriggerEdge::Rising
|
||||
} else {
|
||||
TriggerEdge::Falling
|
||||
};
|
||||
exti.listen_gpio(&mut syscfg, port, line, edge);
|
||||
});
|
||||
|
||||
let pin_has_state = if state {
|
||||
s.pin.is_high()
|
||||
} else {
|
||||
s.pin.is_low()
|
||||
}
|
||||
.unwrap_or(false);
|
||||
if pin_has_state {
|
||||
return ();
|
||||
}
|
||||
|
||||
fut.await;
|
||||
|
||||
Exti::unpend(line);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: PinWithInterrupt + 'static> WaitForRisingEdge for ExtiPin<T> {
|
||||
type Future<'a> = impl Future<Output = ()> + 'a;
|
||||
|
||||
fn wait_for_rising_edge<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
|
||||
self.wait_for_edge(TriggerEdge::Rising)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: PinWithInterrupt + 'static> WaitForFallingEdge for ExtiPin<T> {
|
||||
type Future<'a> = impl Future<Output = ()> + 'a;
|
||||
|
||||
fn wait_for_falling_edge<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
|
||||
self.wait_for_edge(TriggerEdge::Falling)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: PinWithInterrupt + 'static> WaitForAnyEdge for ExtiPin<T> {
|
||||
type Future<'a> = impl Future<Output = ()> + 'a;
|
||||
|
||||
fn wait_for_any_edge<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
|
||||
self.wait_for_edge(TriggerEdge::Both)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: InputPin + PinWithInterrupt + 'static> WaitForHigh for ExtiPin<T> {
|
||||
type Future<'a> = impl Future<Output = ()> + 'a;
|
||||
|
||||
fn wait_for_high<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
|
||||
self.wait_for_state(true)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: InputPin + PinWithInterrupt + 'static> WaitForLow for ExtiPin<T> {
|
||||
type Future<'a> = impl Future<Output = ()> + 'a;
|
||||
|
||||
fn wait_for_low<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
|
||||
self.wait_for_state(false)
|
||||
}
|
||||
}
|
||||
|
||||
mod private {
|
||||
pub trait Sealed {}
|
||||
}
|
||||
|
||||
pub trait PinWithInterrupt: private::Sealed {
|
||||
type Interrupt: interrupt::Interrupt;
|
||||
fn port(&self) -> gpio::Port;
|
||||
fn line(&self) -> GpioLine;
|
||||
}
|
||||
|
||||
macro_rules! exti {
|
||||
($set:ident, [
|
||||
$($INT:ident => $pin:ident,)+
|
||||
]) => {
|
||||
$(
|
||||
impl<T> private::Sealed for gpio::$set::$pin<T> {}
|
||||
impl<T> PinWithInterrupt for gpio::$set::$pin<T> {
|
||||
type Interrupt = interrupt::$INT;
|
||||
fn port(&self) -> gpio::Port {
|
||||
self.port()
|
||||
}
|
||||
fn line(&self) -> GpioLine {
|
||||
GpioLine::from_raw_line(self.pin_number()).unwrap()
|
||||
}
|
||||
}
|
||||
)+
|
||||
|
||||
};
|
||||
}
|
||||
|
||||
exti!(gpioa, [
|
||||
EXTI0_1 => PA0,
|
||||
EXTI0_1 => PA1,
|
||||
EXTI2_3 => PA2,
|
||||
EXTI2_3 => PA3,
|
||||
EXTI4_15 => PA4,
|
||||
EXTI4_15 => PA5,
|
||||
EXTI4_15 => PA6,
|
||||
EXTI4_15 => PA7,
|
||||
EXTI4_15 => PA8,
|
||||
EXTI4_15 => PA9,
|
||||
EXTI4_15 => PA10,
|
||||
EXTI4_15 => PA11,
|
||||
EXTI4_15 => PA12,
|
||||
EXTI4_15 => PA13,
|
||||
EXTI4_15 => PA14,
|
||||
EXTI4_15 => PA15,
|
||||
]);
|
||||
|
||||
exti!(gpiob, [
|
||||
EXTI0_1 => PB0,
|
||||
EXTI0_1 => PB1,
|
||||
EXTI2_3 => PB2,
|
||||
EXTI2_3 => PB3,
|
||||
EXTI4_15 => PB4,
|
||||
EXTI4_15 => PB5,
|
||||
EXTI4_15 => PB6,
|
||||
EXTI4_15 => PB7,
|
||||
EXTI4_15 => PB8,
|
||||
EXTI4_15 => PB9,
|
||||
EXTI4_15 => PB10,
|
||||
EXTI4_15 => PB11,
|
||||
EXTI4_15 => PB12,
|
||||
EXTI4_15 => PB13,
|
||||
EXTI4_15 => PB14,
|
||||
EXTI4_15 => PB15,
|
||||
]);
|
||||
|
||||
exti!(gpioc, [
|
||||
EXTI0_1 => PC0,
|
||||
EXTI0_1 => PC1,
|
||||
EXTI2_3 => PC2,
|
||||
EXTI2_3 => PC3,
|
||||
EXTI4_15 => PC4,
|
||||
EXTI4_15 => PC5,
|
||||
EXTI4_15 => PC6,
|
||||
EXTI4_15 => PC7,
|
||||
EXTI4_15 => PC8,
|
||||
EXTI4_15 => PC9,
|
||||
EXTI4_15 => PC10,
|
||||
EXTI4_15 => PC11,
|
||||
EXTI4_15 => PC12,
|
||||
EXTI4_15 => PC13,
|
||||
EXTI4_15 => PC14,
|
||||
EXTI4_15 => PC15,
|
||||
]);
|
||||
|
||||
exti!(gpiod, [
|
||||
EXTI0_1 => PD0,
|
||||
EXTI0_1 => PD1,
|
||||
EXTI2_3 => PD2,
|
||||
EXTI2_3 => PD3,
|
||||
EXTI4_15 => PD4,
|
||||
EXTI4_15 => PD5,
|
||||
EXTI4_15 => PD6,
|
||||
EXTI4_15 => PD7,
|
||||
EXTI4_15 => PD8,
|
||||
EXTI4_15 => PD9,
|
||||
EXTI4_15 => PD10,
|
||||
EXTI4_15 => PD11,
|
||||
EXTI4_15 => PD12,
|
||||
EXTI4_15 => PD13,
|
||||
EXTI4_15 => PD14,
|
||||
EXTI4_15 => PD15,
|
||||
]);
|
||||
|
||||
exti!(gpioe, [
|
||||
EXTI0_1 => PE0,
|
||||
EXTI0_1 => PE1,
|
||||
EXTI2_3 => PE2,
|
||||
EXTI2_3 => PE3,
|
||||
EXTI4_15 => PE4,
|
||||
EXTI4_15 => PE5,
|
||||
EXTI4_15 => PE6,
|
||||
EXTI4_15 => PE7,
|
||||
EXTI4_15 => PE8,
|
||||
EXTI4_15 => PE9,
|
||||
EXTI4_15 => PE10,
|
||||
EXTI4_15 => PE11,
|
||||
EXTI4_15 => PE12,
|
||||
EXTI4_15 => PE13,
|
||||
EXTI4_15 => PE14,
|
||||
EXTI4_15 => PE15,
|
||||
]);
|
||||
|
||||
exti!(gpioh, [
|
||||
EXTI0_1 => PH0,
|
||||
EXTI0_1 => PH1,
|
||||
EXTI4_15 => PH9,
|
||||
EXTI4_15 => PH10,
|
||||
]);
|
||||
|
|
@ -19,6 +19,4 @@ compile_error!(
|
|||
"Multile chip features activated. You must activate exactly one of the following features: "
|
||||
);
|
||||
|
||||
pub use embassy_stm32::{fmt, hal, interrupt, pac};
|
||||
|
||||
pub mod exti;
|
||||
pub use embassy_stm32::{exti, fmt, hal, interrupt, pac};
|
||||
|
|
|
|||
Loading…
Reference in a new issue