diff --git a/embassy-stm32/src/hash/v1.rs b/embassy-stm32/src/hash/v1.rs
index 50f9adc83..36beb7c3e 100644
--- a/embassy-stm32/src/hash/v1.rs
+++ b/embassy-stm32/src/hash/v1.rs
@@ -215,7 +215,7 @@ impl<'d, T: Instance> Hash<'d, T> {
             }
             // Register waker, then enable interrupts.
             HASH_WAKER.register(cx.waker());
-            T::regs().imr().modify(|reg| reg.set_dinie(true));
+            T::regs().imr().modify(|reg| reg.set_dcie(true));
             // Check for completion.
             let bits = T::regs().sr().read();
             if bits.dcis() {
diff --git a/embassy-stm32/src/hash/v2v3.rs b/embassy-stm32/src/hash/v2v3.rs
index 058864568..ba1e05f0c 100644
--- a/embassy-stm32/src/hash/v2v3.rs
+++ b/embassy-stm32/src/hash/v2v3.rs
@@ -244,7 +244,7 @@ impl<'d, T: Instance, D: Dma<T>> Hash<'d, T, D> {
             }
             // Register waker, then enable interrupts.
             HASH_WAKER.register(cx.waker());
-            T::regs().imr().modify(|reg| reg.set_dinie(true));
+            T::regs().imr().modify(|reg| reg.set_dcie(true));
             // Check for completion.
             let bits = T::regs().sr().read();
             if bits.dcis() {