NaxdyOrg/embassy
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Fix digest interrupt enable.

Browse source
This commit is contained in:
Caleb Garrett 2024-02-06 18:37:48 -05:00
parent b7db75adff
commit bfa67c2993
2 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
embassy-stm32/src/hash/v1.rs
View file

@ -215,7 +215,7 @@ impl<'d, T: Instance> Hash<'d, T> {
} }
// Register waker, then enable interrupts. // Register waker, then enable interrupts.
HASH_WAKER.register(cx.waker()); HASH_WAKER.register(cx.waker());
T::regs().imr().modify(|reg| reg.set_dinie(true)); T::regs().imr().modify(|reg| reg.set_dcie(true));
// Check for completion. // Check for completion.
let bits = T::regs().sr().read(); let bits = T::regs().sr().read();
if bits.dcis() { if bits.dcis() {

2
embassy-stm32/src/hash/v2v3.rs
View file

@ -244,7 +244,7 @@ impl<'d, T: Instance, D: Dma<T>> Hash<'d, T, D> {
} }
// Register waker, then enable interrupts. // Register waker, then enable interrupts.
HASH_WAKER.register(cx.waker()); HASH_WAKER.register(cx.waker());
T::regs().imr().modify(|reg| reg.set_dinie(true)); T::regs().imr().modify(|reg| reg.set_dcie(true));
// Check for completion. // Check for completion.
let bits = T::regs().sr().read(); let bits = T::regs().sr().read();
if bits.dcis() { if bits.dcis() {