From a168b9ef51999e09b18c23453e24d3980cfaccb0 Mon Sep 17 00:00:00 2001
From: xoviat <xoviat@users.noreply.github.com>
Date: Wed, 6 Jan 2021 21:02:02 -0600
Subject: [PATCH] restrict unsafe block

---
 embassy-stm32f4-examples/src/serial.rs | 14 ++--
 embassy-stm32f4/src/serial.rs          | 96 ++++++++++++--------------
 2 files changed, 53 insertions(+), 57 deletions(-)

diff --git a/embassy-stm32f4-examples/src/serial.rs b/embassy-stm32f4-examples/src/serial.rs
index 11a5b8904..ea0497016 100644
--- a/embassy-stm32f4-examples/src/serial.rs
+++ b/embassy-stm32f4-examples/src/serial.rs
@@ -28,8 +28,8 @@ async fn run(dp: stm32::Peripherals, cp: cortex_m::Peripherals) {
         .pclk1(24.mhz())
         .freeze();
 
-    unsafe {
-        let mut serial = serial::Serial::new(
+    let mut serial = unsafe {
+        serial::Serial::new(
             gpioa.pa9.into_alternate_af7(),
             gpioa.pa10.into_alternate_af7(),
             interrupt::take!(DMA2_STREAM7),
@@ -40,12 +40,12 @@ async fn run(dp: stm32::Peripherals, cp: cortex_m::Peripherals) {
             config::Parity::ParityNone,
             9600.bps(),
             clocks,
-        );
-        let buf = singleton!(: [u8; 30] = [0; 30]).unwrap();
+        )
+    };
+    let buf = singleton!(: [u8; 30] = [0; 30]).unwrap();
 
-        buf[5] = 0x01;
-        serial.send(buf).await;
-    }
+    buf[5] = 0x01;
+    serial.send(buf).await;
 }
 
 static EXECUTOR: Forever<Executor> = Forever::new();
diff --git a/embassy-stm32f4/src/serial.rs b/embassy-stm32f4/src/serial.rs
index b13438272..c430ee95f 100644
--- a/embassy-stm32f4/src/serial.rs
+++ b/embassy-stm32f4/src/serial.rs
@@ -152,37 +152,35 @@ impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
     fn send<'a>(&'a mut self, buf: &'a [u8]) -> Self::SendFuture<'a> {
         unsafe { INSTANCE = self };
 
-        unsafe {
-            let static_buf = core::mem::transmute::<&'a [u8], &'static mut [u8]>(buf);
+        let static_buf = unsafe { core::mem::transmute::<&'a [u8], &'static mut [u8]>(buf) };
 
-            let tx_stream = self.tx_stream.take().unwrap();
-            let usart = self.usart.take().unwrap();
-            STATE.tx_int.reset();
+        let tx_stream = self.tx_stream.take().unwrap();
+        let usart = self.usart.take().unwrap();
+        STATE.tx_int.reset();
 
-            async move {
-                let mut tx_transfer = Transfer::init(
-                    tx_stream,
-                    usart,
-                    static_buf,
-                    None,
-                    DmaConfig::default()
-                        .transfer_complete_interrupt(true)
-                        .memory_increment(true)
-                        .double_buffer(false),
-                );
+        async move {
+            let mut tx_transfer = Transfer::init(
+                tx_stream,
+                usart,
+                static_buf,
+                None,
+                DmaConfig::default()
+                    .transfer_complete_interrupt(true)
+                    .memory_increment(true)
+                    .double_buffer(false),
+            );
 
-                self.tx_int.unpend();
-                self.tx_int.enable();
-                tx_transfer.start(|_usart| {});
+            self.tx_int.unpend();
+            self.tx_int.enable();
+            tx_transfer.start(|_usart| {});
 
-                STATE.tx_int.wait().await;
+            STATE.tx_int.wait().await;
 
-                let (tx_stream, usart, _buf, _) = tx_transfer.free();
-                self.tx_stream.replace(tx_stream);
-                self.usart.replace(usart);
+            let (tx_stream, usart, _buf, _) = tx_transfer.free();
+            self.tx_stream.replace(tx_stream);
+            self.usart.replace(usart);
 
-                Ok(())
-            }
+            Ok(())
         }
     }
 
@@ -199,31 +197,29 @@ impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
     fn receive<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReceiveFuture<'a> {
         unsafe { INSTANCE = self };
 
-        unsafe {
-            let static_buf = core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf);
-            let rx_stream = self.rx_stream.take().unwrap();
-            let usart = self.usart.take().unwrap();
-            STATE.rx_int.reset();
-            async move {
-                let mut rx_transfer = Transfer::init(
-                    rx_stream,
-                    usart,
-                    static_buf,
-                    None,
-                    DmaConfig::default()
-                        .transfer_complete_interrupt(true)
-                        .memory_increment(true)
-                        .double_buffer(false),
-                );
-                self.rx_int.unpend();
-                self.rx_int.enable();
-                rx_transfer.start(|_usart| {});
-                STATE.rx_int.wait().await;
-                let (rx_stream, usart, buf, _) = rx_transfer.free();
-                self.rx_stream.replace(rx_stream);
-                self.usart.replace(usart);
-                Ok(())
-            }
+        let static_buf = unsafe { core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf) };
+        let rx_stream = self.rx_stream.take().unwrap();
+        let usart = self.usart.take().unwrap();
+        STATE.rx_int.reset();
+        async move {
+            let mut rx_transfer = Transfer::init(
+                rx_stream,
+                usart,
+                static_buf,
+                None,
+                DmaConfig::default()
+                    .transfer_complete_interrupt(true)
+                    .memory_increment(true)
+                    .double_buffer(false),
+            );
+            self.rx_int.unpend();
+            self.rx_int.enable();
+            rx_transfer.start(|_usart| {});
+            STATE.rx_int.wait().await;
+            let (rx_stream, usart, _, _) = rx_transfer.free();
+            self.rx_stream.replace(rx_stream);
+            self.usart.replace(usart);
+            Ok(())
         }
     }
 }