Enable clock by default for stm32l0
Modify init function to return a Clock instance defined by a per-chip SystemClock type and use this in macro setup A proof of concept implementation for STM32 L0 chips. This allows using embassy::main macros for STM32 devices that have the clock setup logic.
This commit is contained in:
Ulf Lilleengen
parent
a126e17fb2
commit
c501b162fc
7 changed files with 614 additions and 25 deletions
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@ -7,20 +7,17 @@ pub fn generate(embassy_prefix: &ModulePrefix, config: syn::Expr) -> TokenStream
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let embassy_stm32_path = embassy_prefix.append("embassy_stm32").path();
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quote!(
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use #embassy_stm32_path::{clock::Clock};
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use #embassy_stm32_path::{interrupt, peripherals, clock::Clock, time::Hertz};
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let p = #embassy_stm32_path::init(#config);
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let (p, mut c) = #embassy_stm32_path::init(#config);
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/*
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let mut rtc = #embass::RTC::new(unsafe { <peripherals::TIM2 as #embassy_path::util::Steal>::steal() }, interrupt::take!(TIM2));
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let rtc = unsafe { make_static(&mut rtc) };
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rtc.start();
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let mut alarm = rtc.alarm0();
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let clock = unsafe { make_static(&mut c) };
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clock.start();
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unsafe { #embassy_path::time::set_clock(rtc) };
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let mut alarm = clock.alarm1();
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unsafe { #embassy_path::time::set_clock(clock) };
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let alarm = unsafe { make_static(&mut alarm) };
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executor.set_alarm(alarm);
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*/
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)
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}
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@ -350,6 +350,13 @@ pub fn main(args: TokenStream, item: TokenStream) -> TokenStream {
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#[cortex_m_rt::entry]
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fn main() -> ! {
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rtt_init_print!();
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unsafe {
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log::set_logger_racy(&LOGGER).unwrap();
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}
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log::set_max_level(log::LevelFilter::Trace);
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log::info!("Hello World!");
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unsafe fn make_static<T>(t: &mut T) -> &'static mut T {
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::core::mem::transmute(t)
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}
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@ -59,6 +59,8 @@ const ALARM_COUNT: usize = 3;
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pub struct Clock<T: Instance> {
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_inner: T,
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irq: T::Interrupt,
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/// Clock frequency
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frequency: Hertz,
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/// Number of 2^23 periods elapsed since boot.
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period: AtomicU32,
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/// Timestamp at which to fire alarm. u64::MAX if no alarm is scheduled.
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@ -66,22 +68,23 @@ pub struct Clock<T: Instance> {
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}
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impl<T: Instance> Clock<T> {
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pub fn new(peripheral: T, irq: T::Interrupt) -> Self {
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pub fn new(peripheral: T, irq: T::Interrupt, frequency: Hertz) -> Self {
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Self {
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_inner: peripheral,
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irq,
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frequency,
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period: AtomicU32::new(0),
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alarms: Mutex::new([AlarmState::new(), AlarmState::new(), AlarmState::new()]),
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}
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}
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pub fn start(&'static self, timer_freq: Hertz) {
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pub fn start(&'static self) {
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let inner = T::inner();
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// NOTE(unsafe) Critical section to use the unsafe methods
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critical_section::with(|_| {
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unsafe {
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inner.prepare(timer_freq);
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inner.prepare(self.frequency);
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}
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self.irq.set_handler_context(self as *const _ as *mut _);
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@ -36,6 +36,7 @@ pub mod time;
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pub use embassy_macros::interrupt;
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pub use pac::{interrupt, peripherals, Peripherals};
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pub use rcc::SystemClock;
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// workaround for svd2rust-generated code using `use crate::generic::*;`
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pub(crate) use pac::regs::generic;
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@ -45,6 +46,12 @@ pub struct Config {
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rcc: rcc::Config,
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}
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impl Config {
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pub fn new(rcc: rcc::Config) -> Self {
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Self { rcc }
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}
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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@ -54,14 +61,12 @@ impl Default for Config {
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}
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/// Initialize embassy.
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pub fn init(config: Config) -> Peripherals {
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pub fn init(config: Config) -> (Peripherals, SystemClock) {
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let p = Peripherals::take();
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unsafe {
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dma::init();
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pac::init_exti();
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rcc::init(config.rcc);
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(p, rcc::init(config.rcc))
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}
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p
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}
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@ -528,6 +528,6 @@ impl<'d> Rcc<'d> {
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}
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}
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pub unsafe fn init(config: Config) {
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// TODO
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}
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pub type SystemClock = ();
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pub unsafe fn init(_config: Config) -> SystemClock {}
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@ -1,11 +1,574 @@
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use crate::clock::Clock;
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use crate::interrupt;
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use crate::pac;
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use embassy::util::Steal;
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use pac::rcc::{self, vals};
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use crate::pac::peripherals::{self, TIM2};
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use crate::time::Hertz;
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use crate::time::U32Ext;
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use pac::rcc::vals;
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use vals::{Hpre, Lptimen, Msirange, Plldiv, Pllmul, Pllon, Pllsrc, Ppre, Sw};
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#[derive(Default)]
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pub struct Config {}
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/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
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/// and with the addition of the init function to configure a system clock.
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pub unsafe fn init(config: Config) {
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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MSI(MSIRange),
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PLL(PLLSource, PLLMul, PLLDiv),
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HSE(Hertz),
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HSI16,
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}
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/// MSI Clock Range
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///
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/// These ranges control the frequency of the MSI. Internally, these ranges map
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/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
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#[derive(Clone, Copy)]
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pub enum MSIRange {
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/// Around 65.536 kHz
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Range0,
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/// Around 131.072 kHz
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Range1,
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/// Around 262.144 kHz
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Range2,
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/// Around 524.288 kHz
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Range3,
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/// Around 1.048 MHz
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Range4,
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/// Around 2.097 MHz (reset value)
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Range5,
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/// Around 4.194 MHz
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Range6,
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}
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impl Default for MSIRange {
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fn default() -> MSIRange {
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MSIRange::Range5
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}
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}
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/// PLL divider
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#[derive(Clone, Copy)]
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pub enum PLLDiv {
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Div2,
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Div3,
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Div4,
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}
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/// PLL multiplier
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#[derive(Clone, Copy)]
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pub enum PLLMul {
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Mul3,
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Mul4,
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Mul6,
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Mul8,
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Mul12,
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Mul16,
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Mul24,
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Mul32,
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Mul48,
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}
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/// AHB prescaler
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#[derive(Clone, Copy)]
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pub enum AHBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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Div64,
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Div128,
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Div256,
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Div512,
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}
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/// APB prescaler
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#[derive(Clone, Copy)]
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pub enum APBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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}
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/// PLL clock input source
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#[derive(Clone, Copy)]
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pub enum PLLSource {
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HSI16,
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HSE(Hertz),
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}
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/// HSI speed
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pub const HSI_FREQ: u32 = 16_000_000;
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/// Clocks configutation
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pub struct Config {
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mux: ClockSrc,
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ahb_pre: AHBPrescaler,
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apb1_pre: APBPrescaler,
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apb2_pre: APBPrescaler,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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mux: ClockSrc::MSI(MSIRange::default()),
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ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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}
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}
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}
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impl Config {
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#[inline]
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pub fn clock_src(mut self, mux: ClockSrc) -> Self {
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self.mux = mux;
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self
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}
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#[inline]
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pub fn ahb_pre(mut self, pre: AHBPrescaler) -> Self {
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self.ahb_pre = pre;
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self
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}
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#[inline]
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pub fn apb1_pre(mut self, pre: APBPrescaler) -> Self {
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self.apb1_pre = pre;
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self
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}
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#[inline]
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pub fn apb2_pre(mut self, pre: APBPrescaler) -> Self {
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self.apb2_pre = pre;
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self
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}
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#[inline]
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pub fn hsi16() -> Config {
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Config {
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mux: ClockSrc::HSI16,
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ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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}
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}
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#[inline]
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pub fn msi(range: MSIRange) -> Config {
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Config {
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mux: ClockSrc::MSI(range),
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ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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}
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}
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#[inline]
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pub fn pll(pll_src: PLLSource, pll_mul: PLLMul, pll_div: PLLDiv) -> Config {
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Config {
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mux: ClockSrc::PLL(pll_src, pll_mul, pll_div),
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ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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}
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}
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#[inline]
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pub fn hse<T>(freq: T) -> Config
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where
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T: Into<Hertz>,
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{
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Config {
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mux: ClockSrc::HSE(freq.into()),
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ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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}
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}
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}
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/// RCC peripheral
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pub struct Rcc {
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clocks: Clocks,
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rb: pac::rcc::Rcc,
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}
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/*
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impl Rcc {
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pub fn enable_lse(&mut self, _: &PWR) -> LSE {
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self.rb.csr.modify(|_, w| {
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// Enable LSE clock
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w.lseon().set_bit()
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});
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while self.rb.csr.read().lserdy().bit_is_clear() {}
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LSE(())
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}
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}
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impl Rcc {
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pub fn enable_hsi48(&mut self, syscfg: &mut SYSCFG, crs: CRS) -> HSI48 {
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// Reset CRS peripheral
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self.rb.apb1rstr.modify(|_, w| w.crsrst().set_bit());
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self.rb.apb1rstr.modify(|_, w| w.crsrst().clear_bit());
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// Enable CRS peripheral
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self.rb.apb1enr.modify(|_, w| w.crsen().set_bit());
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// Initialize CRS
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crs.cfgr.write(|w|
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// Select LSE as synchronization source
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unsafe { w.syncsrc().bits(0b01) });
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crs.cr
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.modify(|_, w| w.autotrimen().set_bit().cen().set_bit());
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// Enable VREFINT reference for HSI48 oscillator
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syscfg
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.syscfg
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.cfgr3
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.modify(|_, w| w.enref_hsi48().set_bit().en_vrefint().set_bit());
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// Select HSI48 as USB clock
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self.rb.ccipr.modify(|_, w| w.hsi48msel().set_bit());
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// Enable dedicated USB clock
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self.rb.crrcr.modify(|_, w| w.hsi48on().set_bit());
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while self.rb.crrcr.read().hsi48rdy().bit_is_clear() {}
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HSI48(())
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}
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}
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impl Rcc {
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/// Configure MCO (Microcontroller Clock Output).
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pub fn configure_mco<P>(
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&mut self,
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source: MCOSEL_A,
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prescaler: MCOPRE_A,
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output_pin: P,
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) -> MCOEnabled
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where
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P: mco::Pin,
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{
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output_pin.into_mco();
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self.rb.cfgr.modify(|_, w| {
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w.mcosel().variant(source);
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w.mcopre().variant(prescaler)
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});
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MCOEnabled(())
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}
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}
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*/
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/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
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pub trait RccExt {
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unsafe fn freeze(self, config: Config) -> Rcc;
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}
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impl RccExt for pac::rcc::Rcc {
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// `cfgr` is almost always a constant, so make sure it can be constant-propagated properly by
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// marking this function and all `Config` constructors and setters as `#[inline]`.
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// This saves ~900 Bytes for the `pwr.rs` example.
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#[inline]
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unsafe fn freeze(self, cfgr: Config) -> Rcc {
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let (sys_clk, sw) = match cfgr.mux {
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ClockSrc::MSI(range) => {
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// Set MSI range
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self.icscr().write(|w| w.set_msirange(range.into()));
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// Enable MSI
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self.cr().write(|w| w.set_msion(Pllon::ENABLED));
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while !self.cr().read().msirdy() {}
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let freq = 32_768 * (1 << (range as u8 + 1));
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(freq, Sw::MSI)
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}
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ClockSrc::HSI16 => {
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// Enable HSI16
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self.cr().write(|w| w.set_hsi16on(Pllon::ENABLED));
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while !self.cr().read().hsi16rdyf() {}
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(HSI_FREQ, Sw::HSI16)
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}
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ClockSrc::HSE(freq) => {
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// Enable HSE
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self.cr().write(|w| w.set_hseon(Pllon::ENABLED));
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while !self.cr().read().hserdy() {}
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(freq.0, Sw::HSE)
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}
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ClockSrc::PLL(src, mul, div) => {
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let freq = match src {
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PLLSource::HSE(freq) => {
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// Enable HSE
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self.cr().write(|w| w.set_hseon(Pllon::ENABLED));
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while !self.cr().read().hserdy() {}
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freq.0
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}
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PLLSource::HSI16 => {
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// Enable HSI
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self.cr().write(|w| w.set_hsi16on(Pllon::ENABLED));
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while !self.cr().read().hsi16rdyf() {}
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HSI_FREQ
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}
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};
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// Disable PLL
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self.cr().modify(|w| w.set_pllon(Pllon::DISABLED));
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while self.cr().read().pllrdy() {}
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let freq = match mul {
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PLLMul::Mul3 => freq * 3,
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PLLMul::Mul4 => freq * 4,
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PLLMul::Mul6 => freq * 6,
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PLLMul::Mul8 => freq * 8,
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PLLMul::Mul12 => freq * 12,
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PLLMul::Mul16 => freq * 16,
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PLLMul::Mul24 => freq * 24,
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PLLMul::Mul32 => freq * 32,
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PLLMul::Mul48 => freq * 48,
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};
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let freq = match div {
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PLLDiv::Div2 => freq / 2,
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PLLDiv::Div3 => freq / 3,
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PLLDiv::Div4 => freq / 4,
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};
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assert!(freq <= 32_u32.mhz().0);
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self.cfgr().write(move |w| {
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w.set_pllmul(mul.into());
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w.set_plldiv(div.into());
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w.set_pllsrc(src.into());
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});
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// Enable PLL
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self.cr().modify(|w| w.set_pllon(Pllon::ENABLED));
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while !self.cr().read().pllrdy() {}
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(freq, Sw::PLL)
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}
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};
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self.cfgr().modify(|w| {
|
||||
w.set_sw(sw.into());
|
||||
w.set_hpre(cfgr.ahb_pre.into());
|
||||
w.set_ppre(0, cfgr.apb1_pre.into());
|
||||
w.set_ppre(1, cfgr.apb2_pre.into());
|
||||
});
|
||||
|
||||
let ahb_freq: u32 = match cfgr.ahb_pre {
|
||||
AHBPrescaler::NotDivided => sys_clk,
|
||||
pre => {
|
||||
let pre: Hpre = pre.into();
|
||||
let pre = 1 << (pre.0 as u32 - 7);
|
||||
sys_clk / pre
|
||||
}
|
||||
};
|
||||
|
||||
let (apb1_freq, apb1_tim_freq, apb1_pre) = match cfgr.apb1_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq, 1),
|
||||
pre => {
|
||||
let pre: Ppre = pre.into();
|
||||
let pre: u8 = 1 << (pre.0 - 3);
|
||||
let freq = ahb_freq / pre as u32;
|
||||
(freq, freq * 2, pre as u8)
|
||||
}
|
||||
};
|
||||
|
||||
let (apb2_freq, apb2_tim_freq, apb2_pre) = match cfgr.apb2_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq, 1),
|
||||
pre => {
|
||||
let pre: Ppre = pre.into();
|
||||
let pre: u8 = 1 << (pre.0 - 3);
|
||||
let freq = ahb_freq / (1 << (pre as u8 - 3));
|
||||
(freq, freq * 2, pre as u8)
|
||||
}
|
||||
};
|
||||
|
||||
let clocks = Clocks {
|
||||
source: cfgr.mux,
|
||||
sys_clk: sys_clk.hz(),
|
||||
ahb_clk: ahb_freq.hz(),
|
||||
apb1_clk: apb1_freq.hz(),
|
||||
apb2_clk: apb2_freq.hz(),
|
||||
apb1_tim_clk: apb1_tim_freq.hz(),
|
||||
apb2_tim_clk: apb2_tim_freq.hz(),
|
||||
apb1_pre,
|
||||
apb2_pre,
|
||||
};
|
||||
|
||||
Rcc { rb: self, clocks }
|
||||
}
|
||||
}
|
||||
|
||||
/// Frozen clock frequencies
|
||||
///
|
||||
/// The existence of this value indicates that the clock configuration can no longer be changed
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct Clocks {
|
||||
source: ClockSrc,
|
||||
sys_clk: Hertz,
|
||||
ahb_clk: Hertz,
|
||||
apb1_clk: Hertz,
|
||||
apb1_tim_clk: Hertz,
|
||||
apb2_clk: Hertz,
|
||||
apb2_tim_clk: Hertz,
|
||||
apb1_pre: u8,
|
||||
apb2_pre: u8,
|
||||
}
|
||||
|
||||
impl Clocks {
|
||||
/// Returns the clock source
|
||||
pub fn source(&self) -> &ClockSrc {
|
||||
&self.source
|
||||
}
|
||||
|
||||
/// Returns the system (core) frequency
|
||||
pub fn sys_clk(&self) -> Hertz {
|
||||
self.sys_clk
|
||||
}
|
||||
|
||||
/// Returns the frequency of the AHB
|
||||
pub fn ahb_clk(&self) -> Hertz {
|
||||
self.ahb_clk
|
||||
}
|
||||
|
||||
/// Returns the frequency of the APB1
|
||||
pub fn apb1_clk(&self) -> Hertz {
|
||||
self.apb1_clk
|
||||
}
|
||||
|
||||
/// Returns the frequency of the APB1 timers
|
||||
pub fn apb1_tim_clk(&self) -> Hertz {
|
||||
self.apb1_tim_clk
|
||||
}
|
||||
|
||||
/// Returns the prescaler of the APB1
|
||||
pub fn apb1_pre(&self) -> u8 {
|
||||
self.apb1_pre
|
||||
}
|
||||
|
||||
/// Returns the frequency of the APB2
|
||||
pub fn apb2_clk(&self) -> Hertz {
|
||||
self.apb2_clk
|
||||
}
|
||||
|
||||
/// Returns the frequency of the APB2 timers
|
||||
pub fn apb2_tim_clk(&self) -> Hertz {
|
||||
self.apb2_tim_clk
|
||||
}
|
||||
|
||||
/// Returns the prescaler of the APB2
|
||||
pub fn apb2_pre(&self) -> u8 {
|
||||
self.apb2_pre
|
||||
}
|
||||
}
|
||||
|
||||
/// Token that exists only, if the HSI48 clock has been enabled
|
||||
///
|
||||
/// You can get an instance of this struct by calling [`Rcc::enable_hsi48`].
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct HSI48(());
|
||||
|
||||
/// Token that exists only if MCO (Microcontroller Clock Out) has been enabled.
|
||||
///
|
||||
/// You can get an instance of this struct by calling [`Rcc::configure_mco`].
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct MCOEnabled(());
|
||||
|
||||
/// Token that exists only, if the LSE clock has been enabled
|
||||
///
|
||||
/// You can get an instance of this struct by calling [`Rcc::enable_lse`].
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct LSE(());
|
||||
|
||||
impl Into<Pllmul> for PLLMul {
|
||||
fn into(self) -> Pllmul {
|
||||
match self {
|
||||
PLLMul::Mul3 => Pllmul::MUL3,
|
||||
PLLMul::Mul4 => Pllmul::MUL4,
|
||||
PLLMul::Mul6 => Pllmul::MUL6,
|
||||
PLLMul::Mul8 => Pllmul::MUL8,
|
||||
PLLMul::Mul12 => Pllmul::MUL12,
|
||||
PLLMul::Mul16 => Pllmul::MUL16,
|
||||
PLLMul::Mul24 => Pllmul::MUL24,
|
||||
PLLMul::Mul32 => Pllmul::MUL32,
|
||||
PLLMul::Mul48 => Pllmul::MUL48,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Into<Plldiv> for PLLDiv {
|
||||
fn into(self) -> Plldiv {
|
||||
match self {
|
||||
PLLDiv::Div2 => Plldiv::DIV2,
|
||||
PLLDiv::Div3 => Plldiv::DIV3,
|
||||
PLLDiv::Div4 => Plldiv::DIV4,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Into<Pllsrc> for PLLSource {
|
||||
fn into(self) -> Pllsrc {
|
||||
match self {
|
||||
PLLSource::HSI16 => Pllsrc::HSI16,
|
||||
PLLSource::HSE(_) => Pllsrc::HSE,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Into<Ppre> for APBPrescaler {
|
||||
fn into(self) -> Ppre {
|
||||
match self {
|
||||
APBPrescaler::NotDivided => Ppre::DIV1,
|
||||
APBPrescaler::Div2 => Ppre::DIV2,
|
||||
APBPrescaler::Div4 => Ppre::DIV4,
|
||||
APBPrescaler::Div8 => Ppre::DIV8,
|
||||
APBPrescaler::Div16 => Ppre::DIV16,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Into<Hpre> for AHBPrescaler {
|
||||
fn into(self) -> Hpre {
|
||||
match self {
|
||||
AHBPrescaler::NotDivided => Hpre::DIV1,
|
||||
AHBPrescaler::Div2 => Hpre::DIV2,
|
||||
AHBPrescaler::Div4 => Hpre::DIV4,
|
||||
AHBPrescaler::Div8 => Hpre::DIV8,
|
||||
AHBPrescaler::Div16 => Hpre::DIV16,
|
||||
AHBPrescaler::Div64 => Hpre::DIV64,
|
||||
AHBPrescaler::Div128 => Hpre::DIV128,
|
||||
AHBPrescaler::Div256 => Hpre::DIV256,
|
||||
AHBPrescaler::Div512 => Hpre::DIV512,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Into<Msirange> for MSIRange {
|
||||
fn into(self) -> Msirange {
|
||||
match self {
|
||||
MSIRange::Range0 => Msirange::RANGE0,
|
||||
MSIRange::Range1 => Msirange::RANGE1,
|
||||
MSIRange::Range2 => Msirange::RANGE2,
|
||||
MSIRange::Range3 => Msirange::RANGE3,
|
||||
MSIRange::Range4 => Msirange::RANGE4,
|
||||
MSIRange::Range5 => Msirange::RANGE5,
|
||||
MSIRange::Range6 => Msirange::RANGE6,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// We use TIM2 as SystemClock
|
||||
pub type SystemClock = Clock<TIM2>;
|
||||
|
||||
pub unsafe fn init(config: Config) -> SystemClock {
|
||||
let rcc = pac::RCC;
|
||||
|
||||
let enabled = vals::Iophen::ENABLED;
|
||||
|
|
@ -17,4 +580,16 @@ pub unsafe fn init(config: Config) {
|
|||
w.set_iopeen(enabled);
|
||||
w.set_iophen(enabled);
|
||||
});
|
||||
|
||||
let r = rcc.freeze(config);
|
||||
|
||||
rcc.apb1enr().modify(|w| w.set_tim2en(Lptimen::ENABLED));
|
||||
rcc.apb1rstr().modify(|w| w.set_tim2rst(true));
|
||||
rcc.apb1rstr().modify(|w| w.set_tim2rst(false));
|
||||
|
||||
Clock::new(
|
||||
<peripherals::TIM2 as embassy::util::Steal>::steal(),
|
||||
interrupt::take!(TIM2),
|
||||
r.clocks.apb1_clk(),
|
||||
)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,8 +6,10 @@ cfg_if::cfg_if! {
|
|||
mod l0;
|
||||
pub use l0::*;
|
||||
} else {
|
||||
pub type SystemClock = ();
|
||||
#[derive(Default)]
|
||||
pub struct Config {}
|
||||
pub fn init(_config: Config) {}
|
||||
pub unsafe fn init(_config: Config) -> SystemClock {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue