stm32/rcc: port g0 to new api.
This commit is contained in:
Dario Nieuwenhuis
parent
b4567bb8c5
commit
c8c4b0b701
3 changed files with 264 additions and 276 deletions
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@ -1,7 +1,8 @@
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use crate::pac::flash::vals::Latency;
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use crate::pac::rcc::vals::{self, Sw};
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pub use crate::pac::pwr::vals::Vos as VoltageRange;
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pub use crate::pac::rcc::vals::{
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Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Pllm, Plln, Pllp, Pllq, Pllr, Ppre as APBPrescaler,
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Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
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Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
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};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::time::Hertz;
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@ -9,6 +10,7 @@ use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// HSE Mode
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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@ -17,69 +19,71 @@ pub enum HseMode {
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Bypass,
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}
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum Sysclk {
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HSE(Hertz, HseMode),
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HSI(HSIPrescaler),
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PLL(PllConfig),
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LSI,
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}
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/// The PLL configuration.
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///
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/// * `VCOCLK = source / m * n`
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/// * `PLLRCLK = VCOCLK / r`
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/// * `PLLQCLK = VCOCLK / q`
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/// * `PLLPCLK = VCOCLK / p`
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#[derive(Clone, Copy)]
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pub struct PllConfig {
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/// The source from which the PLL receives a clock signal
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pub source: PllSource,
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/// The initial divisor of that clock signal
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pub m: Pllm,
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/// The PLL VCO multiplier, which must be in the range `8..=86`.
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pub n: Plln,
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/// The final divisor for `PLLRCLK` output which drives the system clock
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pub r: Pllr,
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/// The divisor for the `PLLQCLK` output, if desired
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pub q: Option<Pllq>,
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/// The divisor for the `PLLPCLK` output, if desired
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pub p: Option<Pllp>,
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}
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impl Default for PllConfig {
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#[inline]
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fn default() -> PllConfig {
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// HSI / 1 * 8 / 2 = 64 MHz
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PllConfig {
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source: PllSource::HSI,
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m: Pllm::DIV1,
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n: Plln::MUL8,
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r: Pllr::DIV2,
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q: None,
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p: None,
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}
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}
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}
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/// HSE Configuration
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum PllSource {
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HSI,
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HSE(Hertz, HseMode),
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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}
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/// PLL Configuration
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///
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/// Use this struct to configure the PLL source, input frequency, multiplication factor, and output
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/// dividers. Be sure to keep check the datasheet for your specific part for the appropriate
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/// frequency ranges for each of these settings.
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pub struct Pll {
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/// PLL Source clock selection.
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pub source: PllSource,
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/// PLL pre-divider
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pub prediv: PllPreDiv,
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/// PLL multiplication factor for VCO
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pub mul: PllMul,
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/// PLL division factor for P clock (ADC Clock)
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pub divp: Option<PllPDiv>,
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/// PLL division factor for Q clock (USB, I2S23, SAI1, FDCAN, QSPI)
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pub divq: Option<PllQDiv>,
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/// PLL division factor for R clock (SYSCLK)
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pub divr: Option<PllRDiv>,
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}
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/// Clocks configutation
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#[non_exhaustive]
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pub struct Config {
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/// HSI Enable
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pub hsi: bool,
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/// HSE Configuration
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pub hse: Option<Hse>,
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/// System Clock Configuration
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pub sys: Sysclk,
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pub ahb_pre: AHBPrescaler,
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pub apb_pre: APBPrescaler,
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pub low_power_run: bool,
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pub ls: super::LsConfig,
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/// HSI48 Configuration
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#[cfg(crs)]
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pub hsi48: Option<super::Hsi48Config>,
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/// PLL Configuration
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pub pll: Option<Pll>,
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/// If PLL is requested as the main clock source in the `sys` field then the PLL configuration
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/// MUST turn on the PLLR output.
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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/// Low-Speed Clock Configuration
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pub ls: super::LsConfig,
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pub low_power_run: bool,
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pub voltage_range: VoltageRange,
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/// Per-peripheral kernel clock selection muxes
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pub mux: super::mux::ClockMux,
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}
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@ -88,248 +92,218 @@ impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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sys: Sysclk::HSI(HSIPrescaler::DIV1),
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ahb_pre: AHBPrescaler::DIV1,
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apb_pre: APBPrescaler::DIV1,
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low_power_run: false,
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ls: Default::default(),
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hsi: true,
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hse: None,
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sys: Sysclk::HSI,
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#[cfg(crs)]
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hsi48: Some(Default::default()),
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pll: None,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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low_power_run: false,
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ls: Default::default(),
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voltage_range: VoltageRange::RANGE1,
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mux: Default::default(),
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}
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}
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}
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impl PllConfig {
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pub(crate) fn init(self) -> (Hertz, Option<Hertz>, Option<Hertz>) {
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let (src, input_freq) = match self.source {
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PllSource::HSI => (vals::Pllsrc::HSI, HSI_FREQ),
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PllSource::HSE(freq, _) => (vals::Pllsrc::HSE, freq),
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};
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let m_freq = input_freq / self.m;
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// RM0454 § 5.4.4:
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// > Caution: The software must set these bits so that the PLL input frequency after the
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// > /M divider is between 2.66 and 16 MHz.
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debug_assert!(m_freq.0 >= 2_660_000 && m_freq.0 <= 16_000_000);
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let n_freq = m_freq * self.n as u32;
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// RM0454 § 5.4.4:
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// > Caution: The software must set these bits so that the VCO output frequency is between
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// > 64 and 344 MHz.
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debug_assert!(n_freq.0 >= 64_000_000 && n_freq.0 <= 344_000_000);
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let r_freq = n_freq / self.r;
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// RM0454 § 5.4.4:
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// > Caution: The software must set this bitfield so as not to exceed 64 MHz on this clock.
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debug_assert!(r_freq.0 <= 64_000_000);
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let q_freq = self.q.map(|q| n_freq / q);
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let p_freq = self.p.map(|p| n_freq / p);
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// RM0454 § 5.2.3:
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// > To modify the PLL configuration, proceed as follows:
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// > 1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR).
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RCC.cr().modify(|w| w.set_pllon(false));
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// > 2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
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while RCC.cr().read().pllrdy() {}
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// > 3. Change the desired parameter.
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// Enable whichever clock source we're using, and wait for it to become ready
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match self.source {
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PllSource::HSI => {
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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}
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PllSource::HSE(_, mode) => {
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RCC.cr().write(|w| {
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w.set_hsebyp(mode != HseMode::Oscillator);
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w.set_hseon(true);
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});
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while !RCC.cr().read().hserdy() {}
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}
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}
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// Configure PLLCFGR
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RCC.pllcfgr().modify(|w| {
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w.set_pllr(self.r);
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w.set_pllren(false);
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w.set_pllq(self.q.unwrap_or(Pllq::DIV2));
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w.set_pllqen(false);
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w.set_pllp(self.p.unwrap_or(Pllp::DIV2));
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w.set_pllpen(false);
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w.set_plln(self.n);
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w.set_pllm(self.m);
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w.set_pllsrc(src)
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});
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// > 4. Enable the PLL again by setting PLLON to 1.
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RCC.cr().modify(|w| w.set_pllon(true));
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// Wait for the PLL to become ready
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while !RCC.cr().read().pllrdy() {}
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// > 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, and PLLREN in PLL
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// > configuration register (RCC_PLLCFGR).
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RCC.pllcfgr().modify(|w| {
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// We'll use R for system clock, so enable that unconditionally
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w.set_pllren(true);
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// We may also use Q or P
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w.set_pllqen(self.q.is_some());
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w.set_pllpen(self.p.is_some());
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});
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(r_freq, q_freq, p_freq)
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}
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#[derive(Default)]
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pub struct PllFreq {
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pub pll_p: Option<Hertz>,
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pub pll_q: Option<Hertz>,
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pub pll_r: Option<Hertz>,
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}
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pub(crate) unsafe fn init(config: Config) {
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let mut pll1_q_freq = None;
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let mut pll1_p_freq = None;
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let (sys_clk, sw) = match config.sys {
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Sysclk::HSI(div) => {
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// Enable HSI
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RCC.cr().write(|w| {
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w.set_hsidiv(div);
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w.set_hsion(true)
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});
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// Configure HSI
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let hsi = match config.hsi {
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false => {
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RCC.cr().modify(|w| w.set_hsion(false));
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None
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}
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true => {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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(HSI_FREQ / div, Sw::HSI)
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}
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Sysclk::HSE(freq, mode) => {
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// Enable HSE
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RCC.cr().write(|w| {
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w.set_hseon(true);
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w.set_hsebyp(mode != HseMode::Oscillator);
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});
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while !RCC.cr().read().hserdy() {}
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(freq, Sw::HSE)
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}
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Sysclk::PLL(pll) => {
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let (r_freq, q_freq, p_freq) = pll.init();
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pll1_q_freq = q_freq;
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pll1_p_freq = p_freq;
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(r_freq, Sw::PLL1_R)
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}
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Sysclk::LSI => {
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// Enable LSI
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RCC.csr().write(|w| w.set_lsion(true));
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while !RCC.csr().read().lsirdy() {}
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(super::LSI_FREQ, Sw::LSI)
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Some(HSI_FREQ)
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}
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};
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// Determine the flash latency implied by the target clock speed
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// RM0454 § 3.3.4:
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let target_flash_latency = if sys_clk.0 <= 24_000_000 {
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Latency::WS0
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} else if sys_clk.0 <= 48_000_000 {
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Latency::WS1
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} else {
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Latency::WS2
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};
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// Increase the number of cycles we wait for flash if the new value is higher
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// There's no harm in waiting a little too much before the clock change, but we'll
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// crash immediately if we don't wait enough after the clock change
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let mut set_flash_latency_after = false;
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FLASH.acr().modify(|w| {
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// Is the current flash latency less than what we need at the new SYSCLK?
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if w.latency().to_bits() <= target_flash_latency.to_bits() {
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// We must increase the number of wait states now
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w.set_latency(target_flash_latency)
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} else {
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// We may decrease the number of wait states later
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set_flash_latency_after = true;
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// Configure HSE
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let hse = match config.hse {
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None => {
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RCC.cr().modify(|w| w.set_hseon(false));
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None
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}
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// RM0454 § 3.3.5:
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// > Prefetch is enabled by setting the PRFTEN bit of the FLASH access control register
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// > (FLASH_ACR). This feature is useful if at least one wait state is needed to access the
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// > Flash memory.
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//
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// Enable flash prefetching if we have at least one wait state, and disable it otherwise.
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w.set_prften(target_flash_latency.to_bits() > 0);
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});
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if !set_flash_latency_after {
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// Spin until the effective flash latency is compatible with the clock change
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while FLASH.acr().read().latency().to_bits() < target_flash_latency.to_bits() {}
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}
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// Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once
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let (sw, hpre, ppre) = (sw.into(), config.ahb_pre, config.apb_pre);
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RCC.cfgr().modify(|w| {
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w.set_sw(sw);
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w.set_hpre(hpre);
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w.set_ppre(ppre);
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});
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if set_flash_latency_after {
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// We can make the flash require fewer wait states
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// Spin until the SYSCLK changes have taken effect
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loop {
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let cfgr = RCC.cfgr().read();
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if cfgr.sw() == sw && cfgr.hpre() == hpre && cfgr.ppre() == ppre {
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break;
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Some(hse) => {
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match hse.mode {
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HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
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HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
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}
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}
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// Set the flash latency to require fewer wait states
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FLASH.acr().modify(|w| w.set_latency(target_flash_latency));
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}
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let ahb_freq = sys_clk / config.ahb_pre;
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let (apb_freq, apb_tim_freq) = match config.apb_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let freq = ahb_freq / pre;
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(freq, freq * 2u32)
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RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
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RCC.cr().modify(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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Some(hse.freq)
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}
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};
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// Configure HSI48 if required
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#[cfg(crs)]
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let hsi48 = config.hsi48.map(super::init_hsi48);
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let pll = config
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.pll
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.map(|pll_config| {
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let src_freq = match pll_config.source {
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PllSource::HSI => unwrap!(hsi),
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PllSource::HSE => unwrap!(hse),
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_ => unreachable!(),
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};
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// Disable PLL before configuration
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RCC.cr().modify(|w| w.set_pllon(false));
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while RCC.cr().read().pllrdy() {}
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let in_freq = src_freq / pll_config.prediv;
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assert!(max::PLL_IN.contains(&in_freq));
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let internal_freq = in_freq * pll_config.mul;
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assert!(max::PLL_VCO.contains(&internal_freq));
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RCC.pllcfgr().write(|w| {
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w.set_plln(pll_config.mul);
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w.set_pllm(pll_config.prediv);
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w.set_pllsrc(pll_config.source.into());
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});
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let pll_p_freq = pll_config.divp.map(|div_p| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllp(div_p);
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w.set_pllpen(true);
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});
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let freq = internal_freq / div_p;
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assert!(max::PLL_P.contains(&freq));
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freq
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});
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let pll_q_freq = pll_config.divq.map(|div_q| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllq(div_q);
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w.set_pllqen(true);
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});
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let freq = internal_freq / div_q;
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assert!(max::PLL_Q.contains(&freq));
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freq
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});
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let pll_r_freq = pll_config.divr.map(|div_r| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllr(div_r);
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w.set_pllren(true);
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});
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let freq = internal_freq / div_r;
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assert!(max::PLL_R.contains(&freq));
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freq
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});
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// Enable the PLL
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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PllFreq {
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pll_p: pll_p_freq,
|
||||
pll_q: pll_q_freq,
|
||||
pll_r: pll_r_freq,
|
||||
}
|
||||
})
|
||||
.unwrap_or_default();
|
||||
|
||||
let sys = match config.sys {
|
||||
Sysclk::HSI => unwrap!(hsi),
|
||||
Sysclk::HSE => unwrap!(hse),
|
||||
Sysclk::PLL1_R => unwrap!(pll.pll_r),
|
||||
_ => unreachable!(),
|
||||
};
|
||||
|
||||
assert!(max::SYSCLK.contains(&sys));
|
||||
|
||||
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
|
||||
let hclk = sys / config.ahb_pre;
|
||||
assert!(max::HCLK.contains(&hclk));
|
||||
|
||||
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
|
||||
assert!(max::PCLK.contains(&pclk1));
|
||||
|
||||
let latency = match (config.voltage_range, hclk.0) {
|
||||
(VoltageRange::RANGE1, ..=24_000_000) => Latency::WS0,
|
||||
(VoltageRange::RANGE1, ..=48_000_000) => Latency::WS1,
|
||||
(VoltageRange::RANGE1, _) => Latency::WS2,
|
||||
(VoltageRange::RANGE2, ..=8_000_000) => Latency::WS0,
|
||||
(VoltageRange::RANGE2, ..=16_000_000) => Latency::WS1,
|
||||
(VoltageRange::RANGE2, _) => Latency::WS2,
|
||||
_ => unreachable!(),
|
||||
};
|
||||
|
||||
// Configure flash read access latency based on voltage scale and frequency (RM0444 3.3.4)
|
||||
FLASH.acr().modify(|w| {
|
||||
w.set_latency(latency);
|
||||
});
|
||||
|
||||
// Spin until the effective flash latency is set.
|
||||
while FLASH.acr().read().latency() != latency {}
|
||||
|
||||
// Now that boost mode and flash read access latency are configured, set up SYSCLK
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_sw(config.sys);
|
||||
w.set_hpre(config.ahb_pre);
|
||||
w.set_ppre(config.apb1_pre);
|
||||
});
|
||||
|
||||
if config.low_power_run {
|
||||
assert!(sys_clk.0 <= 2_000_000);
|
||||
assert!(sys <= Hertz(2_000_000));
|
||||
PWR.cr1().modify(|w| w.set_lpr(true));
|
||||
}
|
||||
|
||||
let rtc = config.ls.init();
|
||||
let lse_freq = config.ls.lse.map(|lse| lse.frequency);
|
||||
|
||||
let hsi_freq = (sw == Sw::HSI).then_some(HSI_FREQ);
|
||||
let hsi_div_8_freq = hsi_freq.map(|f| f / 8u32);
|
||||
let lsi_freq = (sw == Sw::LSI).then_some(super::LSI_FREQ);
|
||||
let hse_freq = (sw == Sw::HSE).then_some(sys_clk);
|
||||
|
||||
#[cfg(crs)]
|
||||
let hsi48 = config.hsi48.map(super::init_hsi48);
|
||||
#[cfg(not(crs))]
|
||||
let hsi48: Option<Hertz> = None;
|
||||
|
||||
config.mux.init();
|
||||
|
||||
set_clocks!(
|
||||
sys: Some(sys_clk),
|
||||
hclk1: Some(ahb_freq),
|
||||
pclk1: Some(apb_freq),
|
||||
pclk1_tim: Some(apb_tim_freq),
|
||||
hsi: hsi_freq,
|
||||
sys: Some(sys),
|
||||
hclk1: Some(hclk),
|
||||
pclk1: Some(pclk1),
|
||||
pclk1_tim: Some(pclk1_tim),
|
||||
pll1_p: pll.pll_p,
|
||||
pll1_q: pll.pll_q,
|
||||
pll1_r: pll.pll_r,
|
||||
hsi: hsi,
|
||||
hse: hse,
|
||||
#[cfg(crs)]
|
||||
hsi48: hsi48,
|
||||
hsi_div_8: hsi_div_8_freq,
|
||||
hse: hse_freq,
|
||||
lse: lse_freq,
|
||||
lsi: lsi_freq,
|
||||
pll1_q: pll1_q_freq,
|
||||
pll1_p: pll1_p_freq,
|
||||
rtc: rtc,
|
||||
hsi_div_488: None,
|
||||
hsi_div_8: hsi.map(|h| h / 8u32),
|
||||
hsi_div_488: hsi.map(|h| h / 488u32),
|
||||
|
||||
// TODO
|
||||
lsi: None,
|
||||
lse: None,
|
||||
);
|
||||
}
|
||||
|
||||
mod max {
|
||||
use core::ops::RangeInclusive;
|
||||
|
||||
use crate::time::Hertz;
|
||||
|
||||
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(48_000_000);
|
||||
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
|
||||
pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(64_000_000);
|
||||
pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(8)..=Hertz(64_000_000);
|
||||
pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(64_000_000);
|
||||
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(2_660_000)..=Hertz(16_000_000);
|
||||
pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(96_000_000)..=Hertz(344_000_000);
|
||||
pub(crate) const PLL_P: RangeInclusive<Hertz> = Hertz(3_090_000)..=Hertz(122_000_000);
|
||||
pub(crate) const PLL_Q: RangeInclusive<Hertz> = Hertz(12_000_000)..=Hertz(128_000_000);
|
||||
pub(crate) const PLL_R: RangeInclusive<Hertz> = Hertz(12_000_000)..=Hertz(64_000_000);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,15 +16,16 @@ async fn main(_spawner: Spawner) {
|
|||
let mut config = PeripheralConfig::default();
|
||||
{
|
||||
use embassy_stm32::rcc::*;
|
||||
|
||||
config.rcc.sys = Sysclk::PLL(PllConfig {
|
||||
config.rcc.hsi = true;
|
||||
config.rcc.pll = Some(Pll {
|
||||
source: PllSource::HSI,
|
||||
m: Pllm::DIV1,
|
||||
n: Plln::MUL16,
|
||||
r: Pllr::DIV4, // CPU clock comes from PLLR (HSI (16MHz) / 1 * 16 / 4 = 64MHz)
|
||||
q: Some(Pllq::DIV2), // TIM1 or TIM15 can be sourced from PLLQ (HSI (16MHz) / 1 * 16 / 2 = 128MHz)
|
||||
p: None,
|
||||
prediv: PllPreDiv::DIV1,
|
||||
mul: PllMul::MUL16,
|
||||
divp: None,
|
||||
divq: Some(PllQDiv::DIV2), // 16 / 1 * 16 / 2 = 128 Mhz
|
||||
divr: Some(PllRDiv::DIV4), // 16 / 1 * 16 / 4 = 64 Mhz
|
||||
});
|
||||
config.rcc.sys = Sysclk::PLL1_R;
|
||||
|
||||
// configure TIM1 mux to select PLLQ as clock source
|
||||
// https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
|
||||
|
|
|
|||
|
|
@ -260,6 +260,19 @@ pub fn config() -> Config {
|
|||
#[allow(unused_mut)]
|
||||
let mut config = Config::default();
|
||||
|
||||
#[cfg(feature = "stm32g071rb")]
|
||||
{
|
||||
config.rcc.hsi = true;
|
||||
config.rcc.pll = Some(Pll {
|
||||
source: PllSource::HSI,
|
||||
prediv: PllPreDiv::DIV1,
|
||||
mul: PllMul::MUL16,
|
||||
divp: None,
|
||||
divq: None,
|
||||
divr: Some(PllRDiv::DIV4), // 16 / 1 * 16 / 4 = 64 Mhz
|
||||
});
|
||||
config.rcc.sys = Sysclk::PLL1_R;
|
||||
}
|
||||
#[cfg(feature = "stm32wb55rg")]
|
||||
{
|
||||
config.rcc = embassy_stm32::rcc::WPAN_DEFAULT;
|
||||
|
|
|
|||
Loading…
Reference in a new issue