diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs index d2db0a257..7de223455 100644 --- a/embassy-stm32/src/gpio.rs +++ b/embassy-stm32/src/gpio.rs @@ -680,7 +680,6 @@ pub(crate) trait SealedPin { self.block().ospeedr().modify(|w| w.set_ospeedr(pin, speed.into())); } - /// Get the pull-up configuration. #[inline] fn pull(&self) -> Pull { @@ -692,12 +691,14 @@ pub(crate) trait SealedPin { let crlh = if n < 8 { 0 } else { 1 }; match r.cr(crlh).cnf(n % 8) { vals::CnfIn::FLOATING => Pull::None, - _ => if r.bsrr().read().bs(n % 8) { - Pull::Up - } else if r.bsrr().read().br(n % 8) { - Pull::Down - } else { - Pull::None + _ => { + if r.bsrr().read().bs(n % 8) { + Pull::Up + } else if r.bsrr().read().br(n % 8) { + Pull::Down + } else { + Pull::None + } } } } diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index bcd6b0bf4..76d58def6 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -283,11 +283,12 @@ impl<'d, T: Instance, M: PeriMode> Spi<'d, T, M> { let miso_pullup = match &self.miso { None => false, - Some(pin) => - if pin.pull() == Pull::Up { - true - } else { - false + Some(pin) => { + if pin.pull() == Pull::Up { + true + } else { + false + } } }; @@ -426,11 +427,15 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), new_pin!(mosi, AFType::OutputPushPull, Speed::VeryHigh), - new_pin!(miso, AFType::Input, Speed::Input, + new_pin!( + miso, + AFType::Input, + Speed::Input, match config.miso_pullup { true => Pull::Up, false => Pull::None, - }), + } + ), None, None, config, @@ -448,11 +453,15 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> { peri, new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), None, - new_pin!(miso, AFType::Input, Speed::Input, + new_pin!( + miso, + AFType::Input, + Speed::Input, match config.miso_pullup { true => Pull::Up, false => Pull::None, - }), + } + ), None, None, config,