Dario Nieuwenhuis
GitHub
commit
ceb13def19
5 changed files with 675 additions and 3 deletions
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@ -21,6 +21,8 @@ pub enum AbortReason {
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NoAcknowledge,
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/// The arbitration was lost, e.g. electrical problems with the clock signal
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ArbitrationLoss,
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/// Transmit ended with data still in fifo
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TxNotEmpty(u16),
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Other(u32),
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}
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@ -52,7 +54,7 @@ impl Default for Config {
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}
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}
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const FIFO_SIZE: u8 = 16;
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pub const FIFO_SIZE: u8 = 16;
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pub struct I2c<'d, T: Instance, M: Mode> {
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phantom: PhantomData<(&'d mut T, M)>,
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@ -636,6 +638,7 @@ mod eh1 {
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Self::Abort(AbortReason::NoAcknowledge) => {
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embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Address)
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}
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Self::Abort(AbortReason::TxNotEmpty(_)) => embedded_hal_1::i2c::ErrorKind::Other,
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Self::Abort(AbortReason::Other(_)) => embedded_hal_1::i2c::ErrorKind::Other,
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Self::InvalidReadBufferLength => embedded_hal_1::i2c::ErrorKind::Other,
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Self::InvalidWriteBufferLength => embedded_hal_1::i2c::ErrorKind::Other,
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@ -738,8 +741,8 @@ mod nightly {
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}
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}
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fn i2c_reserved_addr(addr: u16) -> bool {
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(addr & 0x78) == 0 || (addr & 0x78) == 0x78
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pub fn i2c_reserved_addr(addr: u16) -> bool {
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((addr & 0x78) == 0 || (addr & 0x78) == 0x78) && addr != 0
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}
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mod sealed {
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338
embassy-rp/src/i2c_slave.rs
Normal file
338
embassy-rp/src/i2c_slave.rs
Normal file
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@ -0,0 +1,338 @@
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use core::future;
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use core::marker::PhantomData;
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use core::task::Poll;
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use embassy_hal_internal::into_ref;
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use pac::i2c;
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use crate::i2c::{i2c_reserved_addr, AbortReason, Instance, InterruptHandler, SclPin, SdaPin, FIFO_SIZE};
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use crate::interrupt::typelevel::{Binding, Interrupt};
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use crate::{pac, Peripheral};
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/// I2C error
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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/// I2C abort with error
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Abort(AbortReason),
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/// User passed in a response buffer that was 0 length
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InvalidResponseBufferLength,
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}
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/// Received command
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Command {
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/// General Call
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GeneralCall(usize),
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/// Read
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Read,
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/// Write+read
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WriteRead(usize),
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/// Write
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Write(usize),
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}
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/// Possible responses to responding to a read
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum ReadStatus {
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/// Transaction Complete, controller naked our last byte
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Done,
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/// Transaction Incomplete, controller trying to read more bytes than were provided
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NeedMoreBytes,
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/// Transaction Complere, but controller stopped reading bytes before we ran out
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LeftoverBytes(u16),
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}
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/// Slave Configuration
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#[non_exhaustive]
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#[derive(Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct Config {
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/// Target Address
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pub addr: u16,
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}
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impl Default for Config {
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fn default() -> Self {
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Self { addr: 0x55 }
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}
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}
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pub struct I2cSlave<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> I2cSlave<'d, T> {
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pub fn new(
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_peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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_irq: impl Binding<T::Interrupt, InterruptHandler<T>>,
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config: Config,
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) -> Self {
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into_ref!(_peri, scl, sda);
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assert!(!i2c_reserved_addr(config.addr));
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assert!(config.addr != 0);
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let p = T::regs();
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let reset = T::reset();
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crate::reset::reset(reset);
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crate::reset::unreset_wait(reset);
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p.ic_enable().write(|w| w.set_enable(false));
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p.ic_sar().write(|w| w.set_ic_sar(config.addr));
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p.ic_con().modify(|w| {
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w.set_master_mode(false);
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w.set_ic_slave_disable(false);
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w.set_tx_empty_ctrl(true);
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});
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// Set FIFO watermarks to 1 to make things simpler. This is encoded
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// by a register value of 0. Rx watermark should never change, but Tx watermark will be
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// adjusted in operation.
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p.ic_tx_tl().write(|w| w.set_tx_tl(0));
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p.ic_rx_tl().write(|w| w.set_rx_tl(0));
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// Configure SCL & SDA pins
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scl.gpio().ctrl().write(|w| w.set_funcsel(3));
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sda.gpio().ctrl().write(|w| w.set_funcsel(3));
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scl.pad_ctrl().write(|w| {
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w.set_schmitt(true);
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w.set_ie(true);
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w.set_od(false);
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w.set_pue(true);
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w.set_pde(false);
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});
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sda.pad_ctrl().write(|w| {
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w.set_schmitt(true);
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w.set_ie(true);
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w.set_od(false);
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w.set_pue(true);
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w.set_pde(false);
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});
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// Clear interrupts
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p.ic_clr_intr().read();
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// Enable I2C block
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p.ic_enable().write(|w| w.set_enable(true));
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// mask everything initially
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p.ic_intr_mask().write_value(i2c::regs::IcIntrMask(0));
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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Self { phantom: PhantomData }
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}
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/// Calls `f` to check if we are ready or not.
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/// If not, `g` is called once the waker is set (to eg enable the required interrupts).
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#[inline(always)]
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async fn wait_on<F, U, G>(&mut self, mut f: F, mut g: G) -> U
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where
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F: FnMut(&mut Self) -> Poll<U>,
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G: FnMut(&mut Self),
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{
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future::poll_fn(|cx| {
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let r = f(self);
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trace!("intr p: {:013b}", T::regs().ic_raw_intr_stat().read().0);
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if r.is_pending() {
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T::waker().register(cx.waker());
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g(self);
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}
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r
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})
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.await
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}
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#[inline(always)]
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fn drain_fifo(&mut self, buffer: &mut [u8], offset: usize) -> usize {
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let p = T::regs();
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let len = p.ic_rxflr().read().rxflr() as usize;
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let end = offset + len;
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for i in offset..end {
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buffer[i] = p.ic_data_cmd().read().dat();
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}
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end
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}
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#[inline(always)]
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fn write_to_fifo(&mut self, buffer: &[u8]) {
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let p = T::regs();
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for byte in buffer {
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p.ic_data_cmd().write(|w| w.set_dat(*byte));
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}
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}
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/// Wait asynchronously for commands from an I2C master.
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/// `buffer` is provided in case master does a 'write' and is unused for 'read'.
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pub async fn listen(&mut self, buffer: &mut [u8]) -> Result<Command, Error> {
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let p = T::regs();
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p.ic_clr_intr().read();
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// set rx fifo watermark to 1 byte
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p.ic_rx_tl().write(|w| w.set_rx_tl(0));
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let mut len = 0;
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let ret = self
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.wait_on(
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|me| {
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let stat = p.ic_raw_intr_stat().read();
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if p.ic_rxflr().read().rxflr() > 0 {
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len = me.drain_fifo(buffer, len);
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// we're recieving data, set rx fifo watermark to 12 bytes to reduce interrupt noise
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p.ic_rx_tl().write(|w| w.set_rx_tl(11));
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}
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if stat.restart_det() && stat.rd_req() {
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Poll::Ready(Ok(Command::WriteRead(len)))
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} else if stat.gen_call() && stat.stop_det() && len > 0 {
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Poll::Ready(Ok(Command::GeneralCall(len)))
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} else if stat.stop_det() {
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Poll::Ready(Ok(Command::Write(len)))
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} else if stat.rd_req() {
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Poll::Ready(Ok(Command::Read))
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} else {
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Poll::Pending
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}
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},
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|_me| {
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p.ic_intr_mask().modify(|w| {
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w.set_m_stop_det(true);
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w.set_m_restart_det(true);
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w.set_m_gen_call(true);
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w.set_m_rd_req(true);
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w.set_m_rx_full(true);
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});
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},
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)
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.await;
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p.ic_clr_intr().read();
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ret
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}
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/// Respond to an I2C master READ command, asynchronously.
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pub async fn respond_to_read(&mut self, buffer: &[u8]) -> Result<ReadStatus, Error> {
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let p = T::regs();
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if buffer.len() == 0 {
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return Err(Error::InvalidResponseBufferLength);
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}
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let mut chunks = buffer.chunks(FIFO_SIZE as usize);
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let ret = self
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.wait_on(
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|me| {
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if let Err(abort_reason) = me.read_and_clear_abort_reason() {
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if let Error::Abort(AbortReason::TxNotEmpty(bytes)) = abort_reason {
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return Poll::Ready(Ok(ReadStatus::LeftoverBytes(bytes)));
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} else {
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return Poll::Ready(Err(abort_reason));
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}
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}
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if let Some(chunk) = chunks.next() {
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me.write_to_fifo(chunk);
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Poll::Pending
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} else {
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let stat = p.ic_raw_intr_stat().read();
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if stat.rx_done() && stat.stop_det() {
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Poll::Ready(Ok(ReadStatus::Done))
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} else if stat.rd_req() {
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Poll::Ready(Ok(ReadStatus::NeedMoreBytes))
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} else {
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Poll::Pending
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}
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}
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},
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|_me| {
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p.ic_intr_mask().modify(|w| {
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w.set_m_stop_det(true);
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w.set_m_rx_done(true);
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w.set_m_tx_empty(true);
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w.set_m_tx_abrt(true);
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})
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},
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)
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.await;
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p.ic_clr_intr().read();
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ret
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}
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/// Respond to reads with the fill byte until the controller stops asking
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pub async fn respond_till_stop(&mut self, fill: u8) -> Result<(), Error> {
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loop {
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match self.respond_to_read(&[fill]).await {
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Ok(ReadStatus::NeedMoreBytes) => (),
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Ok(_) => break Ok(()),
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Err(e) => break Err(e),
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}
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}
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}
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/// Respond to a master read, then fill any remaining read bytes with `fill`
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pub async fn respond_and_fill(&mut self, buffer: &[u8], fill: u8) -> Result<ReadStatus, Error> {
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let resp_stat = self.respond_to_read(buffer).await?;
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if resp_stat == ReadStatus::NeedMoreBytes {
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self.respond_till_stop(fill).await?;
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Ok(ReadStatus::Done)
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} else {
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Ok(resp_stat)
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}
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}
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#[inline(always)]
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fn read_and_clear_abort_reason(&mut self) -> Result<(), Error> {
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let p = T::regs();
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let mut abort_reason = p.ic_tx_abrt_source().read();
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// Mask off fifo flush count
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let tx_flush_cnt = abort_reason.tx_flush_cnt();
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abort_reason.set_tx_flush_cnt(0);
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// Mask off master_dis
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abort_reason.set_abrt_master_dis(false);
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if abort_reason.0 != 0 {
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// Note clearing the abort flag also clears the reason, and this
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// instance of flag is clear-on-read! Note also the
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// IC_CLR_TX_ABRT register always reads as 0.
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p.ic_clr_tx_abrt().read();
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let reason = if abort_reason.abrt_7b_addr_noack()
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| abort_reason.abrt_10addr1_noack()
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| abort_reason.abrt_10addr2_noack()
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{
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AbortReason::NoAcknowledge
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} else if abort_reason.arb_lost() {
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AbortReason::ArbitrationLoss
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} else if abort_reason.abrt_slvflush_txfifo() {
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AbortReason::TxNotEmpty(tx_flush_cnt)
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} else {
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AbortReason::Other(abort_reason.0)
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};
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Err(Error::Abort(reason))
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} else {
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Ok(())
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}
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}
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}
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@ -16,6 +16,7 @@ pub mod flash;
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mod float;
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pub mod gpio;
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pub mod i2c;
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pub mod i2c_slave;
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pub mod multicore;
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pub mod pwm;
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mod reset;
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118
examples/rp/src/bin/i2c_slave.rs
Normal file
118
examples/rp/src/bin/i2c_slave.rs
Normal file
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@ -0,0 +1,118 @@
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//! This example shows how to use the 2040 as an i2c slave.
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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use defmt::*;
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use embassy_executor::Spawner;
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use embassy_rp::peripherals::{I2C0, I2C1};
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use embassy_rp::{bind_interrupts, i2c, i2c_slave};
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use embassy_time::{Duration, Timer};
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use embedded_hal_async::i2c::I2c;
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use {defmt_rtt as _, panic_probe as _};
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bind_interrupts!(struct Irqs {
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I2C0_IRQ => i2c::InterruptHandler<I2C0>;
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I2C1_IRQ => i2c::InterruptHandler<I2C1>;
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});
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const DEV_ADDR: u8 = 0x42;
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#[embassy_executor::task]
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async fn device_task(mut dev: i2c_slave::I2cSlave<'static, I2C1>) -> ! {
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info!("Device start");
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let mut state = 0;
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loop {
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let mut buf = [0u8; 128];
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match dev.listen(&mut buf).await {
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Ok(i2c_slave::Command::GeneralCall(len)) => info!("Device recieved general call write: {}", buf[..len]),
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Ok(i2c_slave::Command::Read) => loop {
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match dev.respond_to_read(&[state]).await {
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Ok(x) => match x {
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i2c_slave::ReadStatus::Done => break,
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i2c_slave::ReadStatus::NeedMoreBytes => (),
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i2c_slave::ReadStatus::LeftoverBytes(x) => {
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info!("tried to write {} extra bytes", x);
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break;
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}
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},
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Err(e) => error!("error while responding {}", e),
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}
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},
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Ok(i2c_slave::Command::Write(len)) => info!("Device recieved write: {}", buf[..len]),
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Ok(i2c_slave::Command::WriteRead(len)) => {
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info!("device recieved write read: {:x}", buf[..len]);
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match buf[0] {
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// Set the state
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0xC2 => {
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state = buf[1];
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match dev.respond_and_fill(&[state], 0x00).await {
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Ok(read_status) => info!("response read status {}", read_status),
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Err(e) => error!("error while responding {}", e),
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}
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}
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// Reset State
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0xC8 => {
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state = 0;
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match dev.respond_and_fill(&[state], 0x00).await {
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Ok(read_status) => info!("response read status {}", read_status),
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Err(e) => error!("error while responding {}", e),
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}
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}
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x => error!("Invalid Write Read {:x}", x),
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}
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}
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Err(e) => error!("{}", e),
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}
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}
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}
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#[embassy_executor::task]
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async fn controller_task(mut con: i2c::I2c<'static, I2C0, i2c::Async>) {
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info!("Controller start");
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loop {
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let mut resp_buff = [0u8; 2];
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for i in 0..10 {
|
||||
match con.write_read(DEV_ADDR, &[0xC2, i], &mut resp_buff).await {
|
||||
Ok(_) => info!("write_read response: {}", resp_buff),
|
||||
Err(e) => error!("Error writing {}", e),
|
||||
}
|
||||
|
||||
Timer::after(Duration::from_millis(100)).await;
|
||||
}
|
||||
match con.read(DEV_ADDR, &mut resp_buff).await {
|
||||
Ok(_) => info!("read response: {}", resp_buff),
|
||||
Err(e) => error!("Error writing {}", e),
|
||||
}
|
||||
match con.write_read(DEV_ADDR, &[0xC8], &mut resp_buff).await {
|
||||
Ok(_) => info!("write_read response: {}", resp_buff),
|
||||
Err(e) => error!("Error writing {}", e),
|
||||
}
|
||||
Timer::after(Duration::from_millis(100)).await;
|
||||
}
|
||||
}
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(spawner: Spawner) {
|
||||
let p = embassy_rp::init(Default::default());
|
||||
info!("Hello World!");
|
||||
|
||||
let d_sda = p.PIN_3;
|
||||
let d_scl = p.PIN_2;
|
||||
let mut config = i2c_slave::Config::default();
|
||||
config.addr = DEV_ADDR as u16;
|
||||
let device = i2c_slave::I2cSlave::new(p.I2C1, d_sda, d_scl, Irqs, config);
|
||||
|
||||
unwrap!(spawner.spawn(device_task(device)));
|
||||
|
||||
let c_sda = p.PIN_1;
|
||||
let c_scl = p.PIN_0;
|
||||
let mut config = i2c::Config::default();
|
||||
config.frequency = 5_000;
|
||||
let controller = i2c::I2c::new_async(p.I2C0, c_sda, c_scl, Irqs, config);
|
||||
|
||||
unwrap!(spawner.spawn(controller_task(controller)));
|
||||
}
|
||||
212
tests/rp/src/bin/i2c.rs
Normal file
212
tests/rp/src/bin/i2c.rs
Normal file
|
|
@ -0,0 +1,212 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
teleprobe_meta::target!(b"rpi-pico");
|
||||
|
||||
use defmt::{assert_eq, info, panic, unwrap};
|
||||
use embassy_executor::Executor;
|
||||
use embassy_executor::_export::StaticCell;
|
||||
use embassy_rp::multicore::{spawn_core1, Stack};
|
||||
use embassy_rp::peripherals::{I2C0, I2C1};
|
||||
use embassy_rp::{bind_interrupts, i2c, i2c_slave};
|
||||
use embedded_hal_1::i2c::Operation;
|
||||
use embedded_hal_async::i2c::I2c;
|
||||
use {defmt_rtt as _, panic_probe as _, panic_probe as _, panic_probe as _};
|
||||
|
||||
static mut CORE1_STACK: Stack<1024> = Stack::new();
|
||||
static EXECUTOR0: StaticCell<Executor> = StaticCell::new();
|
||||
static EXECUTOR1: StaticCell<Executor> = StaticCell::new();
|
||||
|
||||
use crate::i2c::AbortReason;
|
||||
|
||||
bind_interrupts!(struct Irqs {
|
||||
I2C0_IRQ => i2c::InterruptHandler<I2C0>;
|
||||
I2C1_IRQ => i2c::InterruptHandler<I2C1>;
|
||||
});
|
||||
|
||||
const DEV_ADDR: u8 = 0x42;
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn device_task(mut dev: i2c_slave::I2cSlave<'static, I2C1>) -> ! {
|
||||
info!("Device start");
|
||||
|
||||
let mut count = 0xD0;
|
||||
|
||||
loop {
|
||||
let mut buf = [0u8; 128];
|
||||
match dev.listen(&mut buf).await {
|
||||
Ok(i2c_slave::Command::GeneralCall(len)) => {
|
||||
assert_eq!(buf[..len], [0xCA, 0x11], "recieving the general call failed");
|
||||
info!("General Call - OK");
|
||||
}
|
||||
Ok(i2c_slave::Command::Read) => {
|
||||
loop {
|
||||
match dev.respond_to_read(&[count]).await {
|
||||
Ok(x) => match x {
|
||||
i2c_slave::ReadStatus::Done => break,
|
||||
i2c_slave::ReadStatus::NeedMoreBytes => count += 1,
|
||||
i2c_slave::ReadStatus::LeftoverBytes(x) => {
|
||||
info!("tried to write {} extra bytes", x);
|
||||
break;
|
||||
}
|
||||
},
|
||||
Err(e) => match e {
|
||||
embassy_rp::i2c_slave::Error::Abort(AbortReason::Other(n)) => panic!("Other {:b}", n),
|
||||
_ => panic!("{}", e),
|
||||
},
|
||||
}
|
||||
}
|
||||
count += 1;
|
||||
}
|
||||
Ok(i2c_slave::Command::Write(len)) => match len {
|
||||
1 => {
|
||||
assert_eq!(buf[..len], [0xAA], "recieving a single byte failed");
|
||||
info!("Single Byte Write - OK")
|
||||
}
|
||||
4 => {
|
||||
assert_eq!(buf[..len], [0xAA, 0xBB, 0xCC, 0xDD], "recieving 4 bytes failed");
|
||||
info!("4 Byte Write - OK")
|
||||
}
|
||||
32 => {
|
||||
assert_eq!(
|
||||
buf[..len],
|
||||
[
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
|
||||
25, 26, 27, 28, 29, 30, 31
|
||||
],
|
||||
"recieving 32 bytes failed"
|
||||
);
|
||||
info!("32 Byte Write - OK")
|
||||
}
|
||||
_ => panic!("Invalid write length {}", len),
|
||||
},
|
||||
Ok(i2c_slave::Command::WriteRead(len)) => {
|
||||
info!("device recieved write read: {:x}", buf[..len]);
|
||||
match buf[0] {
|
||||
0xC2 => {
|
||||
let resp_buff = [0xD1, 0xD2, 0xD3, 0xD4];
|
||||
dev.respond_to_read(&resp_buff).await.unwrap();
|
||||
}
|
||||
0xC8 => {
|
||||
let mut resp_buff = [0u8; 32];
|
||||
for i in 0..32 {
|
||||
resp_buff[i] = i as u8;
|
||||
}
|
||||
dev.respond_to_read(&resp_buff).await.unwrap();
|
||||
}
|
||||
x => panic!("Invalid Write Read {:x}", x),
|
||||
}
|
||||
}
|
||||
Err(e) => match e {
|
||||
embassy_rp::i2c_slave::Error::Abort(AbortReason::Other(n)) => panic!("Other {:b}", n),
|
||||
_ => panic!("{}", e),
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn controller_task(mut con: i2c::I2c<'static, I2C0, i2c::Async>) {
|
||||
info!("Device start");
|
||||
|
||||
{
|
||||
let buf = [0xCA, 0x11];
|
||||
con.write(0u16, &buf).await.unwrap();
|
||||
info!("Controler general call write");
|
||||
embassy_futures::yield_now().await;
|
||||
}
|
||||
|
||||
{
|
||||
let mut buf = [0u8];
|
||||
con.read(DEV_ADDR, &mut buf).await.unwrap();
|
||||
assert_eq!(buf, [0xD0], "single byte read failed");
|
||||
info!("single byte read - OK");
|
||||
embassy_futures::yield_now().await;
|
||||
}
|
||||
|
||||
{
|
||||
let mut buf = [0u8; 4];
|
||||
con.read(DEV_ADDR, &mut buf).await.unwrap();
|
||||
assert_eq!(buf, [0xD1, 0xD2, 0xD3, 0xD4], "single byte read failed");
|
||||
info!("4 byte read - OK");
|
||||
embassy_futures::yield_now().await;
|
||||
}
|
||||
|
||||
{
|
||||
let buf = [0xAA];
|
||||
con.write(DEV_ADDR, &buf).await.unwrap();
|
||||
info!("Controler single byte write");
|
||||
embassy_futures::yield_now().await;
|
||||
}
|
||||
|
||||
{
|
||||
let buf = [0xAA, 0xBB, 0xCC, 0xDD];
|
||||
con.write(DEV_ADDR, &buf).await.unwrap();
|
||||
info!("Controler 4 byte write");
|
||||
embassy_futures::yield_now().await;
|
||||
}
|
||||
|
||||
{
|
||||
let mut buf = [0u8; 32];
|
||||
for i in 0..32 {
|
||||
buf[i] = i as u8;
|
||||
}
|
||||
con.write(DEV_ADDR, &buf).await.unwrap();
|
||||
info!("Controler 32 byte write");
|
||||
embassy_futures::yield_now().await;
|
||||
}
|
||||
|
||||
{
|
||||
let mut buf = [0u8; 4];
|
||||
let mut ops = [Operation::Write(&[0xC2]), Operation::Read(&mut buf)];
|
||||
con.transaction(DEV_ADDR, &mut ops).await.unwrap();
|
||||
assert_eq!(buf, [0xD1, 0xD2, 0xD3, 0xD4], "write_read failed");
|
||||
info!("write_read - OK");
|
||||
embassy_futures::yield_now().await;
|
||||
}
|
||||
|
||||
{
|
||||
let mut buf = [0u8; 32];
|
||||
let mut ops = [Operation::Write(&[0xC8]), Operation::Read(&mut buf)];
|
||||
con.transaction(DEV_ADDR, &mut ops).await.unwrap();
|
||||
assert_eq!(
|
||||
buf,
|
||||
[
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
|
||||
28, 29, 30, 31
|
||||
],
|
||||
"write_read of 32 bytes failed"
|
||||
);
|
||||
info!("large write_read - OK")
|
||||
}
|
||||
|
||||
info!("Test OK");
|
||||
cortex_m::asm::bkpt();
|
||||
}
|
||||
|
||||
#[cortex_m_rt::entry]
|
||||
fn main() -> ! {
|
||||
let p = embassy_rp::init(Default::default());
|
||||
info!("Hello World!");
|
||||
|
||||
let d_sda = p.PIN_19;
|
||||
let d_scl = p.PIN_18;
|
||||
let mut config = i2c_slave::Config::default();
|
||||
config.addr = DEV_ADDR as u16;
|
||||
let device = i2c_slave::I2cSlave::new(p.I2C1, d_sda, d_scl, Irqs, config);
|
||||
|
||||
spawn_core1(p.CORE1, unsafe { &mut CORE1_STACK }, move || {
|
||||
let executor1 = EXECUTOR1.init(Executor::new());
|
||||
executor1.run(|spawner| unwrap!(spawner.spawn(device_task(device))));
|
||||
});
|
||||
|
||||
let executor0 = EXECUTOR0.init(Executor::new());
|
||||
|
||||
let c_sda = p.PIN_21;
|
||||
let c_scl = p.PIN_20;
|
||||
let mut config = i2c::Config::default();
|
||||
config.frequency = 5_000;
|
||||
let controller = i2c::I2c::new_async(p.I2C0, c_sda, c_scl, Irqs, config);
|
||||
|
||||
executor0.run(|spawner| unwrap!(spawner.spawn(controller_task(controller))));
|
||||
}
|
||||
Loading…
Reference in a new issue