diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index e04b3ea0..530760bd 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -24,8 +24,7 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
             // Reading DR clears the rxne, error and idle interrupt flags on v1.
             let dr = if sr.ore() || sr.idle() || sr.rxne() {
                 Some(rdr(r).read_volatile())
-            }
-            else {
+            } else {
                 None
             };
             clear_interrupt_flags(r, sr);
@@ -48,8 +47,7 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
                 if !buf.is_empty() {
                     buf[0] = dr.unwrap();
                     rx_writer.push_done(1);
-                }
-                else {
+                } else {
                     // FIXME: Should we disable any further RX interrupts when the buffer becomes full.
                 }