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nrf, rp: update set_config

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xoviat 2023-10-01 09:37:42 -05:00
parent 5ad34404af
commit d2a2734752
4 changed files with 19 additions and 7 deletions
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7
embassy-nrf/src/spim.rs
View file

@ -176,7 +176,7 @@ impl<'d, T: Instance> Spim<'d, T> {
let mut spim = Self { _p: spim };
// Apply runtime peripheral configuration
Self::set_config(&mut spim, &config);
Self::set_config(&mut spim, &config).unwrap();
// Disable all events interrupts
r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
@ -566,7 +566,8 @@ mod eha {
impl<'d, T: Instance> SetConfig for Spim<'d, T> {
type Config = Config;
fn set_config(&mut self, config: &Self::Config) {
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
let r = T::regs();
// Configure mode.
let mode = config.mode;
@ -604,5 +605,7 @@ impl<'d, T: Instance> SetConfig for Spim<'d, T> {
// Set over-read character
let orc = config.orc;
r.orc.write(|w| unsafe { w.orc().bits(orc) });
Ok(())
}
}

7
embassy-nrf/src/spis.rs
View file

@ -172,7 +172,7 @@ impl<'d, T: Instance> Spis<'d, T> {
let mut spis = Self { _p: spis };
// Apply runtime peripheral configuration
Self::set_config(&mut spis, &config);
Self::set_config(&mut spis, &config).unwrap();
// Disable all events interrupts.
r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
@ -467,7 +467,8 @@ macro_rules! impl_spis {
impl<'d, T: Instance> SetConfig for Spis<'d, T> {
type Config = Config;
fn set_config(&mut self, config: &Self::Config) {
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
let r = T::regs();
// Configure mode.
let mode = config.mode;
@ -509,5 +510,7 @@ impl<'d, T: Instance> SetConfig for Spis<'d, T> {
// Configure auto-acquire on 'transfer end' event.
let auto_acquire = config.auto_acquire;
r.shorts.write(|w| w.end_acquire().bit(auto_acquire));
Ok(())
}
}

7
embassy-nrf/src/twim.rs
View file

@ -170,7 +170,7 @@ impl<'d, T: Instance> Twim<'d, T> {
let mut twim = Self { _p: twim };
// Apply runtime peripheral configuration
Self::set_config(&mut twim, &config);
Self::set_config(&mut twim, &config).unwrap();
// Disable all events interrupts
r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
@ -890,9 +890,12 @@ mod eha {
impl<'d, T: Instance> SetConfig for Twim<'d, T> {
type Config = Config;
fn set_config(&mut self, config: &Self::Config) {
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
let r = T::regs();
r.frequency
.write(|w| unsafe { w.frequency().bits(config.frequency as u32) });
Ok(())
}
}

5
embassy-rp/src/spi.rs
View file

@ -597,7 +597,8 @@ mod eha {
impl<'d, T: Instance, M: Mode> SetConfig for Spi<'d, T, M> {
type Config = Config;
fn set_config(&mut self, config: &Self::Config) {
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
let p = self.inner.regs();
let (presc, postdiv) = calc_prescs(config.frequency);
p.cpsr().write(|w| w.set_cpsdvsr(presc));
@ -607,5 +608,7 @@ impl<'d, T: Instance, M: Mode> SetConfig for Spi<'d, T, M> {
w.set_sph(config.phase == Phase::CaptureOnSecondTransition);
w.set_scr(postdiv);
});
Ok(())
}
}