diff --git a/stm32-data b/stm32-data
index f5eb7fbb5..5c3d2df91 160000
--- a/stm32-data
+++ b/stm32-data
@@ -1 +1 @@
-Subproject commit f5eb7fbb53e46f7b2995d5f4f0b295a68476f1a3
+Subproject commit 5c3d2df911c8530d4584c731a5de99951858fccd
diff --git a/stm32-metapac-gen/src/lib.rs b/stm32-metapac-gen/src/lib.rs
index 4e0aaf013..570a225c7 100644
--- a/stm32-metapac-gen/src/lib.rs
+++ b/stm32-metapac-gen/src/lib.rs
@@ -393,11 +393,6 @@ pub fn gen(options: Options) {
                         let mut en = find_reg_for_field(&rcc, clock_prefix, &format!("{}EN", name));
                         let mut rst = find_reg_for_field(&rcc, clock_prefix, &format!("{}RST", name));
 
-                        if en.is_none() && rst.is_none() && name.ends_with("1") {
-                            en = find_reg_for_field(&rcc, clock_prefix, &format!("{}EN", name.strip_suffix("1").unwrap()));
-                            rst = find_reg_for_field(&rcc, clock_prefix, &format!("{}RST", name.strip_suffix("1").unwrap()));
-                        }
-
                         match (en, rst) {
                             (Some((enable_reg, enable_field)), Some((reset_reg, reset_field))) => {
                                 let clock = if clock_prefix.is_empty() {