From d372cba266c7a110f314e74dfee589987b892383 Mon Sep 17 00:00:00 2001
From: Adin Ackerman <adinackerman@gmail.com>
Date: Tue, 2 Jan 2024 16:25:51 -0800
Subject: [PATCH] additional chip variants required more clocks
---
embassy-stm32/src/rcc/g0.rs | 5 +++++
embassy-stm32/src/rcc/mod.rs | 6 ++++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index 7f62031e5..aedc95bf3 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -299,7 +299,9 @@ pub(crate) unsafe fn init(config: Config) {
let lse_freq = config.ls.lse.map(|lse| lse.frequency);
let hsi_freq = (sw == Sw::HSI).then_some(HSI_FREQ);
+ let hsi_div_8_freq = hsi_freq.map(|f| f / 8u32);
let lsi_freq = (sw == Sw::LSI).then_some(super::LSI_FREQ);
+ let hse_freq = (sw == Sw::HSE).then_some(sys_clk);
set_freqs(Clocks {
sys: sys_clk,
@@ -307,6 +309,9 @@ pub(crate) unsafe fn init(config: Config) {
pclk1: apb_freq,
pclk1_tim: apb_tim_freq,
hsi: hsi_freq,
+ hsi48: None,
+ hsi_div_8: hsi_div_8_freq,
+ hse: hse_freq,
lse: lse_freq,
lsi: lsi_freq,
pll1_q: pll1_q_freq,
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index c4bee4c95..240ffc6d2 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -162,8 +162,10 @@ pub struct Clocks {
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
pub hsi: Option<Hertz>,
- #[cfg(stm32h5)]
+ #[cfg(any(stm32h5, stm32g0))]
pub hsi48: Option<Hertz>,
+ #[cfg(stm32g0)]
+ pub hsi_div_8: Option<Hertz>,
#[cfg(any(stm32g0, stm32h5))]
pub lsi: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
@@ -171,7 +173,7 @@ pub struct Clocks {
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
pub lse: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7, stm32g4))]
+ #[cfg(any(stm32h5, stm32h7, stm32g0, stm32g4))]
pub hse: Option<Hertz>,
#[cfg(stm32h5)]