disable -> enable. also extracted to function for easy refactoring later
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1 changed files with 64 additions and 36 deletions
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@ -190,17 +190,17 @@ pub struct Config {
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#[cfg(gpdma)]
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pub gpdma_interrupt_priority: Priority,
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/// Disables UCPD1 dead battery functionality.
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/// Enables UCPD1 dead battery functionality.
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///
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/// Defaults to true (disabled).
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#[cfg(ucpd)]
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pub disable_ucpd1_dead_battery: bool,
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/// Defaults to false (disabled).
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#[cfg(peri_ucpd1)]
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pub enable_ucpd1_dead_battery: bool,
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/// Disables UCPD2 dead battery functionality.
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/// Enables UCPD2 dead battery functionality.
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///
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/// Defaults to true (disabled).
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#[cfg(all(ucpd, stm32g0x1))]
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pub disable_ucpd2_dead_battery: bool,
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/// Defaults to false (disabled).
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#[cfg(peri_ucpd2)]
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pub enable_ucpd2_dead_battery: bool,
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}
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impl Default for Config {
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@ -215,10 +215,10 @@ impl Default for Config {
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dma_interrupt_priority: Priority::P0,
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#[cfg(gpdma)]
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gpdma_interrupt_priority: Priority::P0,
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#[cfg(ucpd)]
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disable_ucpd1_dead_battery: true,
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#[cfg(all(ucpd, stm32g0x1))]
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uisable_ucpd2_dead_battery: true,
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#[cfg(peri_ucpd1)]
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enable_ucpd1_dead_battery: false,
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#[cfg(peri_ucpd2)]
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enable_ucpd2_dead_battery: false,
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}
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}
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}
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@ -270,37 +270,27 @@ pub fn init(config: Config) -> Peripherals {
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#[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7)))]
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peripherals::FLASH::enable_and_reset_with_cs(cs);
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// dead battery IOs are still present on g0x0 despite not having UCPD
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// dead battery functionality is still present on these
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// chips despite them not having UCPD- disable it
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#[cfg(any(stm32g070, stm32g0b0))]
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let (disable_ucpd1_dead_battery, disable_ucpd2_dead_battery) = (true, true);
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#[cfg(ucpd)]
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let disable_ucpd1_dead_battery = config.disable_ucpd1_dead_battery;
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#[cfg(all(ucpd, stm32g0x1))]
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let disable_ucpd2_dead_battery = config.disable_ucpd2_dead_battery;
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#[cfg(any(stm32g070, stm32g0b0, all(ucpd, stm32g0x1)))]
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{
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crate::pac::SYSCFG.cfgr1().modify(|w| {
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w.set_ucpd1_strobe(disable_ucpd1_dead_battery);
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w.set_ucpd2_strobe(disable_ucpd2_dead_battery);
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w.set_ucpd1_strobe(true);
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w.set_ucpd2_strobe(true);
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});
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}
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#[cfg(all(ucpd, any(stm32g4, stm32l5)))]
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{
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crate::pac::PWR
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.cr3()
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.modify(|w| w.set_ucpd1_dbdis(disable_ucpd1_dead_battery))
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}
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#[cfg(all(ucpd, any(stm32h5, stm32u5)))]
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{
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crate::pac::PWR
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.ucpdr()
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.modify(|w| w.set_ucpd1_dbdis(disable_ucpd1_dead_battery))
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}
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unsafe {
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// TODO: refactor into mod ucpd
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#[cfg(ucpd)]
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ucpd_init(
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cs,
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#[cfg(peri_ucpd1)]
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config.enable_ucpd1_dead_battery,
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#[cfg(peri_ucpd2)]
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config.enable_ucpd2_dead_battery,
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);
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#[cfg(feature = "_split-pins-enabled")]
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crate::pac::SYSCFG.pmcr().modify(|pmcr| {
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#[cfg(feature = "split-pa0")]
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@ -342,3 +332,41 @@ pub fn init(config: Config) -> Peripherals {
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p
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})
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}
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#[cfg(ucpd)]
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/// Safety: must only be called when all UCPDs are disabled (e.g. at startup)
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unsafe fn ucpd_init(
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_cs: critical_section::CriticalSection,
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#[cfg(peri_ucpd1)] ucpd1_db_enable: bool,
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#[cfg(peri_ucpd2)] ucpd2_db_enable: bool,
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) {
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#[cfg(stm32g0x1)]
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{
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// according to RM0444 (STM32G0x1) section 8.1.1:
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// when UCPD is disabled setting the strobe will disable dead battery
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// (which is enabled after reset) but if UCPD is enabled, setting the
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// strobe will apply the CC pin configuration from the control register
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// (which is why we need to be careful about when we call this)
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crate::pac::SYSCFG.cfgr1().modify(|w| {
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w.set_ucpd1_strobe(ucpd1_db_enable);
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w.set_ucpd2_strobe(ucpd2_db_enable);
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});
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}
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#[cfg(any(stm32g4, stm32l5))]
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{
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crate::pac::PWR.cr3().modify(|w| {
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#[cfg(stm32g4)]
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w.set_ucpd1_dbdis(!ucpd1_db_enable);
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#[cfg(stm32l5)]
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w.set_ucpd_dbdis(!ucpd1_db_enable);
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})
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}
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#[cfg(any(stm32h5, stm32u5))]
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{
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crate::pac::PWR.ucpdr().modify(|w| {
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w.set_ucpd_dbdis(!ucpd1_db_enable);
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})
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}
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}
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