From d5ff1a0ae30db8963eec1b7f23b90991e4f47c3d Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sun, 21 Mar 2021 21:57:04 +0100
Subject: [PATCH] nrf: rename inner peripheral to `peri` for consistence

---
 embassy-nrf/src/qspi.rs | 18 +++++++++---------
 embassy-nrf/src/spim.rs |  8 ++++----
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/embassy-nrf/src/qspi.rs b/embassy-nrf/src/qspi.rs
index 39428c62c..39cefa0a3 100644
--- a/embassy-nrf/src/qspi.rs
+++ b/embassy-nrf/src/qspi.rs
@@ -44,7 +44,7 @@ pub struct Config {
 }
 
 pub struct Qspi<'d, T: Instance> {
-    qspi: T,
+    peri: T,
     irq: T::Interrupt,
     phantom: PhantomData<&'d mut T>,
 }
@@ -131,14 +131,14 @@ impl<'d, T: Instance> Qspi<'d, T> {
         r.events_ready.reset();
 
         Self {
-            qspi,
+            peri: qspi,
             irq,
             phantom: PhantomData,
         }
     }
 
     pub fn sleep(mut self: Pin<&mut Self>) {
-        let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs();
+        let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
 
         info!("flash: sleeping");
         info!("flash: state = {:?}", r.status.read().bits());
@@ -177,7 +177,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
 
         let len = core::cmp::max(req.len(), resp.len()) as u8;
 
-        let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs();
+        let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
         r.cinstrdat0.write(|w| unsafe { w.bits(dat0) });
         r.cinstrdat1.write(|w| unsafe { w.bits(dat1) });
 
@@ -198,7 +198,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
 
         self.as_mut().wait_ready().await;
 
-        let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs();
+        let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
 
         let dat0 = r.cinstrdat0.read().bits();
         let dat1 = r.cinstrdat1.read().bits();
@@ -222,7 +222,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
         let this = unsafe { self.get_unchecked_mut() };
 
         poll_fn(move |cx| {
-            let r = this.qspi.regs();
+            let r = this.peri.regs();
 
             if r.events_ready.read().bits() != 0 {
                 r.events_ready.reset();
@@ -257,7 +257,7 @@ impl<'d, T: Instance> Flash for Qspi<'d, T> {
             assert_eq!(data.len() as u32 % 4, 0);
             assert_eq!(address as u32 % 4, 0);
 
-            let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs();
+            let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
 
             r.read
                 .src
@@ -293,7 +293,7 @@ impl<'d, T: Instance> Flash for Qspi<'d, T> {
             assert_eq!(data.len() as u32 % 4, 0);
             assert_eq!(address as u32 % 4, 0);
 
-            let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs();
+            let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
             r.write
                 .src
                 .write(|w| unsafe { w.src().bits(data.as_ptr() as u32) });
@@ -322,7 +322,7 @@ impl<'d, T: Instance> Flash for Qspi<'d, T> {
 
             assert_eq!(address as u32 % 4096, 0);
 
-            let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs();
+            let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
             r.erase
                 .ptr
                 .write(|w| unsafe { w.ptr().bits(address as u32) });
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index f0c6ebe19..214868b6f 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -26,7 +26,7 @@ pub enum Error {
 }
 
 pub struct Spim<'d, T: Instance> {
-    spim: T,
+    peri: T,
     irq: T::Interrupt,
     phantom: PhantomData<&'d mut T>,
 }
@@ -116,7 +116,7 @@ impl<'d, T: Instance> Spim<'d, T> {
         r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
 
         Self {
-            spim,
+            peri: spim,
             irq,
             phantom: PhantomData,
         }
@@ -155,7 +155,7 @@ impl<'d, T: Instance> FullDuplex<u8> for Spim<'d, T> {
             // before any DMA action has started.
             compiler_fence(Ordering::SeqCst);
 
-            let r = this.spim.regs();
+            let r = this.peri.regs();
 
             // Set up the DMA write.
             r.txd
@@ -187,7 +187,7 @@ impl<'d, T: Instance> FullDuplex<u8> for Spim<'d, T> {
 
             // Wait for 'end' event.
             poll_fn(|cx| {
-                let r = this.spim.regs();
+                let r = this.peri.regs();
 
                 if r.events_end.read().bits() != 0 {
                     r.events_end.reset();