diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs index 365738a31..3e2980bf4 100644 --- a/embassy-stm32/src/adc/mod.rs +++ b/embassy-stm32/src/adc/mod.rs @@ -74,9 +74,9 @@ pub(crate) mod sealed { } } -#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v4, adc_f3)))] +#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_g0)))] pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {} -#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v4, adc_f3))] +#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_g0))] pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {} pub trait AdcPin<T: Instance>: sealed::AdcPin<T> {} diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index 011ecc281..e50e6482c 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs @@ -9,19 +9,6 @@ pub const VREF_DEFAULT_MV: u32 = 3300; /// VREF voltage used for factory calibration of VREFINTCAL register. pub const VREF_CALIB_MV: u32 = 3000; -/// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock -/// configuration. -fn enable() { - critical_section::with(|_| { - #[cfg(any(stm32h7, stm32wl))] - crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true)); - #[cfg(stm32g0)] - crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true)); - #[cfg(any(stm32l4, stm32l5, stm32wb))] - crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true)); - }); -} - pub struct VrefInt; impl<T: Instance> AdcPin<T> for VrefInt {} impl<T: Instance> super::sealed::AdcPin<T> for VrefInt { @@ -61,7 +48,7 @@ impl<T: Instance> super::sealed::AdcPin<T> for Vbat { impl<'d, T: Instance> Adc<'d, T> { pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self { into_ref!(adc); - enable(); + T::reset_and_enable(); T::regs().cr().modify(|reg| { #[cfg(not(adc_g0))] reg.set_deeppwd(false);