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Disable UARTE in embassy-nrf::init

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This commit is contained in:
Henrik Alsér 2022-11-13 01:49:55 +01:00
parent af34fc4ccc
commit dca11095e2
3 changed files with 23 additions and 30 deletions
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6
embassy-nrf/src/lib.rs
View file

@ -268,5 +268,11 @@ pub fn init(config: config::Config) -> Peripherals {
#[cfg(feature = "_time-driver")]
time_driver::init(config.time_interrupt_priority);
// Disable UARTE (enabled by default for some reason)
unsafe {
(*pac::UARTE0::ptr()).enable.write(|w| w.enable().disabled());
(*pac::UARTE1::ptr()).enable.write(|w| w.enable().disabled());
}
peripherals
}

39
embassy-nrf/src/spis.rs
View file

@ -1,5 +1,4 @@
#![macro_use]
use core::future::poll_fn;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
@ -10,7 +9,7 @@ pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MO
use crate::chip::FORCE_COPY_BUFFER_SIZE;
use crate::gpio::sealed::Pin as _;
use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
use crate::gpio::{self, AnyPin, Pin as GpioPin};
use crate::interrupt::{Interrupt, InterruptExt};
use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
use crate::{pac, Peripheral};
@ -122,41 +121,26 @@ impl<'d, T: Instance> Spis<'d, T> {
mosi: Option<PeripheralRef<'d, AnyPin>>,
config: Config,
) -> Self {
into_ref!(cs, spis, irq);
compiler_fence(Ordering::SeqCst);
into_ref!(spis, irq, cs, sck);
let r = T::regs();
// Configure pins.
sck.conf().write(|w| w.input().connect().drive().h0h1());
r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
cs.conf().write(|w| w.input().connect().drive().h0h1());
r.psel.csn.write(|w| unsafe { w.bits(cs.psel_bits()) });
if let Some(mosi) = &mosi {
mosi.conf().write(|w| w.input().connect().drive().h0h1());
r.psel.mosi.write(|w| unsafe { w.bits(mosi.psel_bits()) });
}
if let Some(miso) = &miso {
miso.conf().write(|w| w.dir().output().drive().h0h1());
r.psel.miso.write(|w| unsafe { w.bits(miso.psel_bits()) });
}
match config.mode.polarity {
Polarity::IdleHigh => {
sck.set_high();
if let Some(mosi) = &mosi {
mosi.set_high();
}
}
Polarity::IdleLow => {
sck.set_low();
if let Some(mosi) = &mosi {
mosi.set_low();
}
}
}
// Select pins.
r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
r.psel.csn.write(|w| unsafe { w.bits(cs.psel_bits()) });
r.psel.mosi.write(|w| unsafe { w.bits(mosi.psel_bits()) });
r.psel.miso.write(|w| unsafe { w.bits(miso.psel_bits()) });
// Enable SPIS instance.
r.enable.write(|w| w.enable().enabled());
@ -246,9 +230,8 @@ impl<'d, T: Instance> Spis<'d, T> {
r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
// Reset and enable the end event.
// Reset end event.
r.events_end.reset();
r.intenset.write(|w| w.end().set());
// Release the semaphore.
r.tasks_release.write(|w| unsafe { w.bits(1) });
@ -316,6 +299,7 @@ impl<'d, T: Instance> Spis<'d, T> {
if r.semstat.read().bits() == 1 {
return Poll::Ready(());
}
r.intenset.write(|w| w.acquired().set());
Poll::Pending
})
.await;
@ -324,12 +308,13 @@ impl<'d, T: Instance> Spis<'d, T> {
self.prepare(rx, tx)?;
// Wait for 'end' event.
r.intenset.write(|w| w.end().set());
poll_fn(|cx| {
s.end_waker.register(cx.waker());
if r.events_end.read().bits() != 0 {
return Poll::Ready(());
}
r.intenset.write(|w| w.end().set());
Poll::Pending
})
.await;

8
examples/nrf/src/bin/spis.rs
View file

@ -17,9 +17,11 @@ async fn main(_spawner: Spawner) {
let mut spis = Spis::new(p.SPI2, irq, p.P0_31, p.P0_29, p.P0_28, p.P0_30, Config::default());
loop {
let mut buf = [0_u8; 64];
if let Ok(n) = spis.read(&mut buf).await {
info!("RX: {:?}", buf[..n]);
let mut rx_buf = [0_u8; 64];
let tx_buf = [1_u8, 2, 3, 4, 5, 6, 7, 8];
if let Ok((n_rx, n_tx)) = spis.transfer(&mut rx_buf, &tx_buf).await {
info!("RX: {:?}", rx_buf[..n_rx]);
info!("TX: {:?}", tx_buf[..n_tx]);
}
}
}