stm32-metapac: assume RCC is always present
This commit is contained in:
Dario Nieuwenhuis
parent
f3de443ee7
commit
dd62790f36
2 changed files with 95 additions and 85 deletions
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@ -1,4 +1,5 @@
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use chiptool::generate::CommonModule;
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use chiptool::ir::IR;
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use regex::Regex;
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use serde::Deserialize;
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use std::collections::{BTreeMap, HashMap, HashSet};
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@ -273,19 +274,18 @@ pub fn gen(options: Options) {
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});
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// Load RCC register for chip
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let rcc = core.peripherals.iter().find_map(|(name, p)| {
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if name == "RCC" {
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p.block.as_ref().map(|block| {
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let bi = BlockInfo::parse(block);
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let rcc_reg_path = data_dir
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.join("registers")
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.join(&format!("{}_{}.yaml", bi.module, bi.version));
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serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap()
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})
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} else {
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None
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}
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});
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let (_, rcc) = core
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.peripherals
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.iter()
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.find(|(name, _)| name == &"RCC")
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.expect("RCC peripheral missing");
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let rcc_block = rcc.block.as_ref().expect("RCC peripheral has no block");
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let bi = BlockInfo::parse(&rcc_block);
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let rcc_reg_path = data_dir
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.join("registers")
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.join(&format!("{}_{}.yaml", bi.module, bi.version));
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let rcc: IR = serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap();
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let mut peripheral_versions: BTreeMap<String, String> = BTreeMap::new();
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let mut pin_table: Vec<Vec<String>> = Vec::new();
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@ -424,73 +424,71 @@ pub fn gen(options: Options) {
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_ => {}
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}
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if let Some(rcc) = &rcc {
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// Workaround for clock registers being split on some chip families. Assume fields are
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// named after peripheral and look for first field matching and use that register.
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let mut en = find_reg_for_field(&rcc, "^.+ENR\\d*$", &format!("{}EN", name));
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let mut rst = find_reg_for_field(&rcc, "^.+RSTR\\d*$", &format!("{}RST", name));
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// Workaround for clock registers being split on some chip families. Assume fields are
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// named after peripheral and look for first field matching and use that register.
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let mut en = find_reg_for_field(&rcc, "^.+ENR\\d*$", &format!("{}EN", name));
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let mut rst = find_reg_for_field(&rcc, "^.+RSTR\\d*$", &format!("{}RST", name));
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if en.is_none() && name.ends_with("1") {
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en = find_reg_for_field(
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&rcc,
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"^.+ENR\\d*$",
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&format!("{}EN", &name[..name.len() - 1]),
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);
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rst = find_reg_for_field(
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&rcc,
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"^.+RSTR\\d*$",
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&format!("{}RST", &name[..name.len() - 1]),
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);
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if en.is_none() && name.ends_with("1") {
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en = find_reg_for_field(
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&rcc,
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"^.+ENR\\d*$",
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&format!("{}EN", &name[..name.len() - 1]),
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);
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rst = find_reg_for_field(
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&rcc,
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"^.+RSTR\\d*$",
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&format!("{}RST", &name[..name.len() - 1]),
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);
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}
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match (en, rst) {
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(Some((enable_reg, enable_field)), reset_reg_field) => {
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let clock = match &p.clock {
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Some(clock) => clock.as_str(),
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None => {
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// No clock was specified, derive the clock name from the enable register name.
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Regex::new("([A-Z]+\\d*).*")
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.unwrap()
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.captures(enable_reg)
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.unwrap()
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.get(1)
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.unwrap()
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.as_str()
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}
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};
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let clock = if name.starts_with("TIM") {
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format!("{}_tim", clock.to_ascii_lowercase())
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} else {
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clock.to_ascii_lowercase()
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};
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let mut row = Vec::with_capacity(6);
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row.push(name.clone());
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row.push(clock);
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row.push(enable_reg.to_ascii_lowercase());
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if let Some((reset_reg, reset_field)) = reset_reg_field {
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row.push(reset_reg.to_ascii_lowercase());
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row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
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row.push(format!("set_{}", reset_field.to_ascii_lowercase()));
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} else {
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row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
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}
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if !name.starts_with("GPIO") {
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peripheral_rcc_table.push(row);
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} else {
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gpio_rcc_table.push(row);
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gpio_regs.insert(enable_reg.to_ascii_lowercase());
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}
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}
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match (en, rst) {
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(Some((enable_reg, enable_field)), reset_reg_field) => {
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let clock = match &p.clock {
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Some(clock) => clock.as_str(),
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None => {
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// No clock was specified, derive the clock name from the enable register name.
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Regex::new("([A-Z]+\\d*).*")
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.unwrap()
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.captures(enable_reg)
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.unwrap()
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.get(1)
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.unwrap()
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.as_str()
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}
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};
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let clock = if name.starts_with("TIM") {
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format!("{}_tim", clock.to_ascii_lowercase())
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} else {
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clock.to_ascii_lowercase()
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};
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let mut row = Vec::with_capacity(6);
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row.push(name.clone());
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row.push(clock);
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row.push(enable_reg.to_ascii_lowercase());
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if let Some((reset_reg, reset_field)) = reset_reg_field {
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row.push(reset_reg.to_ascii_lowercase());
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row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
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row.push(format!("set_{}", reset_field.to_ascii_lowercase()));
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} else {
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row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
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}
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if !name.starts_with("GPIO") {
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peripheral_rcc_table.push(row);
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} else {
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gpio_rcc_table.push(row);
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gpio_regs.insert(enable_reg.to_ascii_lowercase());
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}
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}
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(None, Some(_)) => {
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println!("Unable to find enable register for {}", name)
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}
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(None, None) => {
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println!("Unable to find enable and reset register for {}", name)
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}
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(None, Some(_)) => {
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println!("Unable to find enable register for {}", name)
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}
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(None, None) => {
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println!("Unable to find enable and reset register for {}", name)
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}
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}
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}
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@ -1,3 +1,4 @@
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use std::env::args;
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use std::path::PathBuf;
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use stm32_metapac_gen::*;
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@ -5,13 +6,24 @@ fn main() {
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let out_dir = PathBuf::from("out");
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let data_dir = PathBuf::from("../stm32-data/data");
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let chips = std::fs::read_dir(data_dir.join("chips"))
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.unwrap()
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.filter_map(|res| res.unwrap().file_name().to_str().map(|s| s.to_string()))
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.filter(|s| s.ends_with(".yaml"))
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.filter(|s| !s.starts_with("STM32L1")) // cursed gpio stride
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.map(|s| s.strip_suffix(".yaml").unwrap().to_string())
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.collect();
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let args: Vec<String> = args().collect();
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let chips = match &args[..] {
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[_, chip] => {
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vec![chip.clone()]
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}
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[_] => {
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std::fs::read_dir(data_dir.join("chips"))
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.unwrap()
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.filter_map(|res| res.unwrap().file_name().to_str().map(|s| s.to_string()))
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.filter(|s| s.ends_with(".yaml"))
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.filter(|s| !s.starts_with("STM32L1")) // cursed gpio stride
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.filter(|s| !s.starts_with("STM32GBK")) // cursed weird STM32G4
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.map(|s| s.strip_suffix(".yaml").unwrap().to_string())
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.collect()
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}
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_ => panic!("usage: stm32-metapac-gen [chip?]"),
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};
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gen(Options {
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out_dir,
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