stm32: rename core features from _cmX to -cmX, cleanup gen.
This commit is contained in:
Dario Nieuwenhuis
parent
039621c56d
commit
dfb6d407a1
9 changed files with 611 additions and 630 deletions
2
ci.sh
2
ci.sh
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@ -28,7 +28,7 @@ cargo batch \
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--- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,defmt \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f411ce,defmt \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f429zi,log \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi_cm7,defmt \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi-cm7,defmt \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l476vg,defmt \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32l072cz,defmt \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32l151cb-a,defmt \
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@ -615,40 +615,40 @@ stm32h743xg = [ "stm32-metapac/stm32h743xg" ]
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stm32h743xi = [ "stm32-metapac/stm32h743xi" ]
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stm32h743zg = [ "stm32-metapac/stm32h743zg" ]
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stm32h743zi = [ "stm32-metapac/stm32h743zi" ]
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stm32h745bg_cm7 = [ "stm32-metapac/stm32h745bg_cm7" ]
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stm32h745bg_cm4 = [ "stm32-metapac/stm32h745bg_cm4" ]
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stm32h745bi_cm7 = [ "stm32-metapac/stm32h745bi_cm7" ]
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stm32h745bi_cm4 = [ "stm32-metapac/stm32h745bi_cm4" ]
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stm32h745ig_cm7 = [ "stm32-metapac/stm32h745ig_cm7" ]
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stm32h745ig_cm4 = [ "stm32-metapac/stm32h745ig_cm4" ]
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stm32h745ii_cm7 = [ "stm32-metapac/stm32h745ii_cm7" ]
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stm32h745ii_cm4 = [ "stm32-metapac/stm32h745ii_cm4" ]
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stm32h745xg_cm7 = [ "stm32-metapac/stm32h745xg_cm7" ]
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stm32h745xg_cm4 = [ "stm32-metapac/stm32h745xg_cm4" ]
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stm32h745xi_cm7 = [ "stm32-metapac/stm32h745xi_cm7" ]
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stm32h745xi_cm4 = [ "stm32-metapac/stm32h745xi_cm4" ]
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stm32h745zg_cm7 = [ "stm32-metapac/stm32h745zg_cm7" ]
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stm32h745zg_cm4 = [ "stm32-metapac/stm32h745zg_cm4" ]
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stm32h745zi_cm7 = [ "stm32-metapac/stm32h745zi_cm7" ]
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stm32h745zi_cm4 = [ "stm32-metapac/stm32h745zi_cm4" ]
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stm32h747ag_cm7 = [ "stm32-metapac/stm32h747ag_cm7" ]
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stm32h747ag_cm4 = [ "stm32-metapac/stm32h747ag_cm4" ]
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stm32h747ai_cm7 = [ "stm32-metapac/stm32h747ai_cm7" ]
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stm32h747ai_cm4 = [ "stm32-metapac/stm32h747ai_cm4" ]
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stm32h747bg_cm7 = [ "stm32-metapac/stm32h747bg_cm7" ]
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stm32h747bg_cm4 = [ "stm32-metapac/stm32h747bg_cm4" ]
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stm32h747bi_cm7 = [ "stm32-metapac/stm32h747bi_cm7" ]
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stm32h747bi_cm4 = [ "stm32-metapac/stm32h747bi_cm4" ]
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stm32h747ig_cm7 = [ "stm32-metapac/stm32h747ig_cm7" ]
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stm32h747ig_cm4 = [ "stm32-metapac/stm32h747ig_cm4" ]
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stm32h747ii_cm7 = [ "stm32-metapac/stm32h747ii_cm7" ]
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stm32h747ii_cm4 = [ "stm32-metapac/stm32h747ii_cm4" ]
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stm32h747xg_cm7 = [ "stm32-metapac/stm32h747xg_cm7" ]
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stm32h747xg_cm4 = [ "stm32-metapac/stm32h747xg_cm4" ]
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stm32h747xi_cm7 = [ "stm32-metapac/stm32h747xi_cm7" ]
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stm32h747xi_cm4 = [ "stm32-metapac/stm32h747xi_cm4" ]
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stm32h747zi_cm7 = [ "stm32-metapac/stm32h747zi_cm7" ]
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stm32h747zi_cm4 = [ "stm32-metapac/stm32h747zi_cm4" ]
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stm32h745bg-cm7 = [ "stm32-metapac/stm32h745bg-cm7" ]
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stm32h745bg-cm4 = [ "stm32-metapac/stm32h745bg-cm4" ]
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stm32h745bi-cm7 = [ "stm32-metapac/stm32h745bi-cm7" ]
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stm32h745bi-cm4 = [ "stm32-metapac/stm32h745bi-cm4" ]
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stm32h745ig-cm7 = [ "stm32-metapac/stm32h745ig-cm7" ]
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stm32h745ig-cm4 = [ "stm32-metapac/stm32h745ig-cm4" ]
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stm32h745ii-cm7 = [ "stm32-metapac/stm32h745ii-cm7" ]
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stm32h745ii-cm4 = [ "stm32-metapac/stm32h745ii-cm4" ]
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stm32h745xg-cm7 = [ "stm32-metapac/stm32h745xg-cm7" ]
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stm32h745xg-cm4 = [ "stm32-metapac/stm32h745xg-cm4" ]
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stm32h745xi-cm7 = [ "stm32-metapac/stm32h745xi-cm7" ]
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stm32h745xi-cm4 = [ "stm32-metapac/stm32h745xi-cm4" ]
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stm32h745zg-cm7 = [ "stm32-metapac/stm32h745zg-cm7" ]
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stm32h745zg-cm4 = [ "stm32-metapac/stm32h745zg-cm4" ]
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stm32h745zi-cm7 = [ "stm32-metapac/stm32h745zi-cm7" ]
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stm32h745zi-cm4 = [ "stm32-metapac/stm32h745zi-cm4" ]
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stm32h747ag-cm7 = [ "stm32-metapac/stm32h747ag-cm7" ]
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stm32h747ag-cm4 = [ "stm32-metapac/stm32h747ag-cm4" ]
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stm32h747ai-cm7 = [ "stm32-metapac/stm32h747ai-cm7" ]
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stm32h747ai-cm4 = [ "stm32-metapac/stm32h747ai-cm4" ]
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stm32h747bg-cm7 = [ "stm32-metapac/stm32h747bg-cm7" ]
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stm32h747bg-cm4 = [ "stm32-metapac/stm32h747bg-cm4" ]
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stm32h747bi-cm7 = [ "stm32-metapac/stm32h747bi-cm7" ]
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stm32h747bi-cm4 = [ "stm32-metapac/stm32h747bi-cm4" ]
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stm32h747ig-cm7 = [ "stm32-metapac/stm32h747ig-cm7" ]
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stm32h747ig-cm4 = [ "stm32-metapac/stm32h747ig-cm4" ]
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stm32h747ii-cm7 = [ "stm32-metapac/stm32h747ii-cm7" ]
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stm32h747ii-cm4 = [ "stm32-metapac/stm32h747ii-cm4" ]
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stm32h747xg-cm7 = [ "stm32-metapac/stm32h747xg-cm7" ]
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stm32h747xg-cm4 = [ "stm32-metapac/stm32h747xg-cm4" ]
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stm32h747xi-cm7 = [ "stm32-metapac/stm32h747xi-cm7" ]
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stm32h747xi-cm4 = [ "stm32-metapac/stm32h747xi-cm4" ]
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stm32h747zi-cm7 = [ "stm32-metapac/stm32h747zi-cm7" ]
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stm32h747zi-cm4 = [ "stm32-metapac/stm32h747zi-cm4" ]
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stm32h750ib = [ "stm32-metapac/stm32h750ib" ]
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stm32h750vb = [ "stm32-metapac/stm32h750vb" ]
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stm32h750xb = [ "stm32-metapac/stm32h750xb" ]
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@ -659,24 +659,24 @@ stm32h753ii = [ "stm32-metapac/stm32h753ii" ]
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stm32h753vi = [ "stm32-metapac/stm32h753vi" ]
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stm32h753xi = [ "stm32-metapac/stm32h753xi" ]
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stm32h753zi = [ "stm32-metapac/stm32h753zi" ]
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stm32h755bi_cm7 = [ "stm32-metapac/stm32h755bi_cm7" ]
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stm32h755bi_cm4 = [ "stm32-metapac/stm32h755bi_cm4" ]
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stm32h755ii_cm7 = [ "stm32-metapac/stm32h755ii_cm7" ]
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stm32h755ii_cm4 = [ "stm32-metapac/stm32h755ii_cm4" ]
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stm32h755xi_cm7 = [ "stm32-metapac/stm32h755xi_cm7" ]
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stm32h755xi_cm4 = [ "stm32-metapac/stm32h755xi_cm4" ]
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stm32h755zi_cm7 = [ "stm32-metapac/stm32h755zi_cm7" ]
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stm32h755zi_cm4 = [ "stm32-metapac/stm32h755zi_cm4" ]
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stm32h757ai_cm7 = [ "stm32-metapac/stm32h757ai_cm7" ]
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stm32h757ai_cm4 = [ "stm32-metapac/stm32h757ai_cm4" ]
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stm32h757bi_cm7 = [ "stm32-metapac/stm32h757bi_cm7" ]
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stm32h757bi_cm4 = [ "stm32-metapac/stm32h757bi_cm4" ]
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stm32h757ii_cm7 = [ "stm32-metapac/stm32h757ii_cm7" ]
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stm32h757ii_cm4 = [ "stm32-metapac/stm32h757ii_cm4" ]
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stm32h757xi_cm7 = [ "stm32-metapac/stm32h757xi_cm7" ]
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stm32h757xi_cm4 = [ "stm32-metapac/stm32h757xi_cm4" ]
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stm32h757zi_cm7 = [ "stm32-metapac/stm32h757zi_cm7" ]
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stm32h757zi_cm4 = [ "stm32-metapac/stm32h757zi_cm4" ]
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stm32h755bi-cm7 = [ "stm32-metapac/stm32h755bi-cm7" ]
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stm32h755bi-cm4 = [ "stm32-metapac/stm32h755bi-cm4" ]
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stm32h755ii-cm7 = [ "stm32-metapac/stm32h755ii-cm7" ]
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stm32h755ii-cm4 = [ "stm32-metapac/stm32h755ii-cm4" ]
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stm32h755xi-cm7 = [ "stm32-metapac/stm32h755xi-cm7" ]
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stm32h755xi-cm4 = [ "stm32-metapac/stm32h755xi-cm4" ]
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stm32h755zi-cm7 = [ "stm32-metapac/stm32h755zi-cm7" ]
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stm32h755zi-cm4 = [ "stm32-metapac/stm32h755zi-cm4" ]
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stm32h757ai-cm7 = [ "stm32-metapac/stm32h757ai-cm7" ]
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stm32h757ai-cm4 = [ "stm32-metapac/stm32h757ai-cm4" ]
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stm32h757bi-cm7 = [ "stm32-metapac/stm32h757bi-cm7" ]
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stm32h757bi-cm4 = [ "stm32-metapac/stm32h757bi-cm4" ]
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stm32h757ii-cm7 = [ "stm32-metapac/stm32h757ii-cm7" ]
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stm32h757ii-cm4 = [ "stm32-metapac/stm32h757ii-cm4" ]
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stm32h757xi-cm7 = [ "stm32-metapac/stm32h757xi-cm7" ]
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stm32h757xi-cm4 = [ "stm32-metapac/stm32h757xi-cm4" ]
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stm32h757zi-cm7 = [ "stm32-metapac/stm32h757zi-cm7" ]
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stm32h757zi-cm4 = [ "stm32-metapac/stm32h757zi-cm4" ]
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stm32h7a3ag = [ "stm32-metapac/stm32h7a3ag" ]
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stm32h7a3ai = [ "stm32-metapac/stm32h7a3ai" ]
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stm32h7a3ig = [ "stm32-metapac/stm32h7a3ig" ]
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@ -1066,10 +1066,10 @@ stm32wb55vc = [ "stm32-metapac/stm32wb55vc" ]
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stm32wb55ve = [ "stm32-metapac/stm32wb55ve" ]
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stm32wb55vg = [ "stm32-metapac/stm32wb55vg" ]
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stm32wb55vy = [ "stm32-metapac/stm32wb55vy" ]
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stm32wl55cc_cm4 = [ "stm32-metapac/stm32wl55cc_cm4" ]
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stm32wl55cc_cm0p = [ "stm32-metapac/stm32wl55cc_cm0p" ]
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stm32wl55jc_cm4 = [ "stm32-metapac/stm32wl55jc_cm4" ]
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stm32wl55jc_cm0p = [ "stm32-metapac/stm32wl55jc_cm0p" ]
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stm32wl55uc_cm4 = [ "stm32-metapac/stm32wl55uc_cm4" ]
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stm32wl55uc_cm0p = [ "stm32-metapac/stm32wl55uc_cm0p" ]
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stm32wl55cc-cm4 = [ "stm32-metapac/stm32wl55cc-cm4" ]
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stm32wl55cc-cm0p = [ "stm32-metapac/stm32wl55cc-cm0p" ]
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stm32wl55jc-cm4 = [ "stm32-metapac/stm32wl55jc-cm4" ]
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stm32wl55jc-cm0p = [ "stm32-metapac/stm32wl55jc-cm0p" ]
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stm32wl55uc-cm4 = [ "stm32-metapac/stm32wl55uc-cm4" ]
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stm32wl55uc-cm0p = [ "stm32-metapac/stm32wl55uc-cm0p" ]
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# END GENERATED FEATURES
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@ -8,7 +8,7 @@ resolver = "2"
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[dependencies]
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embassy = { version = "0.1.0", path = "../../embassy", features = ["defmt"] }
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embassy-traits = { version = "0.1.0", path = "../../embassy-traits", features = ["defmt"] }
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embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32wl55jc_cm4", "time-driver-tim2", "memory-x", "subghz", "unstable-pac"] }
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embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32wl55jc-cm4", "time-driver-tim2", "memory-x", "subghz", "unstable-pac"] }
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embassy-hal-common = {version = "0.1.0", path = "../../embassy-hal-common" }
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embassy-lora = { version = "0.1.0", path = "../../embassy-lora", features = ["stm32wl", "time"] }
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@ -123,7 +123,7 @@ pub fn stm32_metapac_needed_data(names_and_cores: &[(String, Vec<String>)]) -> S
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for (chip_name, cores) in names_and_cores {
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if cores.len() > 1 {
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for core_name in cores {
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result += &format!("{}_{} = []\n", chip_name, core_name);
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result += &format!("{}-{} = []\n", chip_name, core_name);
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}
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} else {
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result += &format!("{} = []\n", chip_name);
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@ -1,30 +1,30 @@
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use std::env;
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use std::path::PathBuf;
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fn main() {
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let chip_name = env::vars_os()
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let crate_dir = PathBuf::from(env::var_os("CARGO_MANIFEST_DIR").unwrap());
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let chip_core_name = env::vars_os()
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.map(|(a, _)| a.to_string_lossy().to_string())
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.find(|x| x.starts_with("CARGO_FEATURE_STM32"))
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.expect("No stm32xx Cargo feature enabled")
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.strip_prefix("CARGO_FEATURE_")
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.unwrap()
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.to_ascii_lowercase();
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.to_ascii_lowercase()
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.replace('_', "-");
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let mut s = chip_name.split('_');
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let mut chip_name: String = s.next().unwrap().to_string();
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if let Some(c) = s.next() {
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if !c.starts_with("CM") {
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chip_name.push('-');
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} else {
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chip_name.push('_');
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}
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chip_name.push_str(c);
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}
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println!(
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"cargo:rustc-link-search={}/src/chips/{}",
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crate_dir.display(),
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chip_core_name,
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);
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#[cfg(feature = "memory-x")]
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println!("cargo:rustc-link-search=src/chips/{}/memory_x/", _chip_name);
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#[cfg(feature = "rt")]
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println!("cargo:rustc-link-search=src/chips/{}", _chip_name);
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println!(
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"cargo:rustc-link-search={}/src/chips/{}/memory_x/",
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crate_dir.display(),
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chip_core_name,
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);
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println!("cargo:rerun-if-changed=build.rs");
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}
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@ -2,7 +2,6 @@ use chiptool::generate::CommonModule;
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use chiptool::ir::IR;
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use regex::Regex;
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use std::collections::{BTreeMap, HashMap, HashSet};
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use std::env;
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use std::fmt::Write as _;
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use std::fs;
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use std::fs::File;
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@ -98,474 +97,457 @@ pub struct Options {
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pub data_dir: PathBuf,
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}
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pub fn gen_chip(
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options: &Options,
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chip_core_name: &str,
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chip: &Chip,
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core: &Core,
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core_index: usize,
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all_peripheral_versions: &mut HashSet<(String, String)>,
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) {
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let mut ir = ir::IR::new();
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let mut dev = ir::Device {
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interrupts: Vec::new(),
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peripherals: Vec::new(),
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};
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// Load DBGMCU register for chip
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let mut dbgmcu: Option<ir::IR> = core.peripherals.iter().find_map(|(name, p)| {
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if name == "DBGMCU" {
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p.block.as_ref().map(|block| {
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let bi = BlockInfo::parse(block);
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let dbgmcu_reg_path = options
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.data_dir
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.join("registers")
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.join(&format!("{}_{}.yaml", bi.module, bi.version));
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serde_yaml::from_reader(File::open(dbgmcu_reg_path).unwrap()).unwrap()
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})
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} else {
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None
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}
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});
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|
||||
// Load RCC register for chip
|
||||
let (_, rcc) = core
|
||||
.peripherals
|
||||
.iter()
|
||||
.find(|(name, _)| name == &"RCC")
|
||||
.expect("RCC peripheral missing");
|
||||
|
||||
let rcc_block = rcc.block.as_ref().expect("RCC peripheral has no block");
|
||||
let bi = BlockInfo::parse(&rcc_block);
|
||||
let rcc_reg_path = options
|
||||
.data_dir
|
||||
.join("registers")
|
||||
.join(&format!("{}_{}.yaml", bi.module, bi.version));
|
||||
let rcc: IR = serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap();
|
||||
|
||||
let mut peripheral_versions: BTreeMap<String, String> = BTreeMap::new();
|
||||
let mut pin_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut interrupt_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut peripherals_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut peripheral_pins_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut peripheral_rcc_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut dma_channels_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut peripheral_dma_channels_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut peripheral_counts: BTreeMap<String, u8> = BTreeMap::new();
|
||||
let mut dma_channel_counts: BTreeMap<String, u8> = BTreeMap::new();
|
||||
let mut dbgmcu_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut gpio_rcc_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut gpio_regs: HashSet<String> = HashSet::new();
|
||||
|
||||
let gpio_base = core.peripherals.get(&"GPIOA".to_string()).unwrap().address as u32;
|
||||
let gpio_stride = 0x400;
|
||||
|
||||
let number_suffix_re = Regex::new("^(.*?)[0-9]*$").unwrap();
|
||||
|
||||
if let Some(ref mut reg) = dbgmcu {
|
||||
if let Some(ref cr) = reg.fieldsets.get("CR") {
|
||||
for field in cr.fields.iter().filter(|e| e.name.contains("DBG")) {
|
||||
let mut fn_name = String::new();
|
||||
fn_name.push_str("set_");
|
||||
fn_name.push_str(&field.name.to_sanitized_snake_case());
|
||||
dbgmcu_table.push(vec!["cr".into(), fn_name]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (name, p) in &core.peripherals {
|
||||
let captures = number_suffix_re.captures(&name).unwrap();
|
||||
let root_peri_name = captures.get(1).unwrap().as_str().to_string();
|
||||
peripheral_counts.insert(
|
||||
root_peri_name.clone(),
|
||||
peripheral_counts.get(&root_peri_name).map_or(1, |v| v + 1),
|
||||
);
|
||||
let mut ir_peri = ir::Peripheral {
|
||||
name: name.clone(),
|
||||
array: None,
|
||||
base_address: p.address,
|
||||
block: None,
|
||||
description: None,
|
||||
interrupts: HashMap::new(),
|
||||
};
|
||||
|
||||
if let Some(block) = &p.block {
|
||||
let bi = BlockInfo::parse(block);
|
||||
|
||||
peripheral_counts.insert(
|
||||
bi.module.clone(),
|
||||
peripheral_counts.get(&bi.module).map_or(1, |v| v + 1),
|
||||
);
|
||||
|
||||
for pin in &p.pins {
|
||||
let mut row = Vec::new();
|
||||
row.push(name.clone());
|
||||
row.push(bi.module.clone());
|
||||
row.push(bi.block.clone());
|
||||
row.push(pin.pin.clone());
|
||||
row.push(pin.signal.clone());
|
||||
if let Some(ref af) = pin.af {
|
||||
row.push(af.clone());
|
||||
}
|
||||
peripheral_pins_table.push(row);
|
||||
}
|
||||
|
||||
for (signal, irq_name) in &p.interrupts {
|
||||
let mut row = Vec::new();
|
||||
row.push(name.clone());
|
||||
row.push(bi.module.clone());
|
||||
row.push(bi.block.clone());
|
||||
row.push(signal.clone());
|
||||
row.push(irq_name.to_ascii_uppercase());
|
||||
interrupt_table.push(row)
|
||||
}
|
||||
|
||||
for (request, dma_channels) in &p.dma_channels {
|
||||
for channel in dma_channels.iter() {
|
||||
let mut row = Vec::new();
|
||||
row.push(name.clone());
|
||||
row.push(bi.module.clone());
|
||||
row.push(bi.block.clone());
|
||||
row.push(request.clone());
|
||||
row.push(if let Some(channel) = &channel.channel {
|
||||
format!("{{channel: {}}}", channel)
|
||||
} else if let Some(dmamux) = &channel.dmamux {
|
||||
format!("{{dmamux: {}}}", dmamux)
|
||||
} else {
|
||||
unreachable!();
|
||||
});
|
||||
|
||||
row.push(if let Some(request) = channel.request {
|
||||
request.to_string()
|
||||
} else {
|
||||
"()".to_string()
|
||||
});
|
||||
|
||||
if peripheral_dma_channels_table
|
||||
.iter()
|
||||
.find(|a| a[..a.len() - 1] == row[..row.len() - 1])
|
||||
.is_none()
|
||||
{
|
||||
peripheral_dma_channels_table.push(row);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
let mut peripheral_row = Vec::new();
|
||||
peripheral_row.push(bi.module.clone());
|
||||
peripheral_row.push(name.clone());
|
||||
peripherals_table.push(peripheral_row);
|
||||
|
||||
if let Some(old_version) =
|
||||
peripheral_versions.insert(bi.module.clone(), bi.version.clone())
|
||||
{
|
||||
if old_version != bi.version {
|
||||
panic!(
|
||||
"Peripheral {} has multiple versions: {} and {}",
|
||||
bi.module, old_version, bi.version
|
||||
);
|
||||
}
|
||||
}
|
||||
ir_peri.block = Some(format!("{}::{}", bi.module, bi.block));
|
||||
|
||||
match bi.module.as_str() {
|
||||
"gpio" => {
|
||||
let port_letter = name.chars().skip(4).next().unwrap();
|
||||
assert_eq!(0, (p.address as u32 - gpio_base) % gpio_stride);
|
||||
let port_num = (p.address as u32 - gpio_base) / gpio_stride;
|
||||
|
||||
for pin_num in 0..16 {
|
||||
let pin_name = format!("P{}{}", port_letter, pin_num);
|
||||
pin_table.push(vec![
|
||||
pin_name.clone(),
|
||||
name.clone(),
|
||||
port_num.to_string(),
|
||||
pin_num.to_string(),
|
||||
format!("EXTI{}", pin_num),
|
||||
]);
|
||||
}
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
|
||||
// Workaround for clock registers being split on some chip families. Assume fields are
|
||||
// named after peripheral and look for first field matching and use that register.
|
||||
let mut en = find_reg(&rcc, "^.+ENR\\d*$", &format!("{}EN", name));
|
||||
let mut rst = find_reg(&rcc, "^.+RSTR\\d*$", &format!("{}RST", name));
|
||||
|
||||
if en.is_none() && name.ends_with("1") {
|
||||
en = find_reg(
|
||||
&rcc,
|
||||
"^.+ENR\\d*$",
|
||||
&format!("{}EN", &name[..name.len() - 1]),
|
||||
);
|
||||
rst = find_reg(
|
||||
&rcc,
|
||||
"^.+RSTR\\d*$",
|
||||
&format!("{}RST", &name[..name.len() - 1]),
|
||||
);
|
||||
}
|
||||
|
||||
match (en, rst) {
|
||||
(Some((enable_reg, enable_field)), reset_reg_field) => {
|
||||
let clock = match &p.clock {
|
||||
Some(clock) => clock.as_str(),
|
||||
None => {
|
||||
// No clock was specified, derive the clock name from the enable register name.
|
||||
// N.B. STM32G0 has only one APB bus but split ENR registers
|
||||
// (e.g. APBENR1).
|
||||
Regex::new("([A-Z]+\\d*)ENR\\d*")
|
||||
.unwrap()
|
||||
.captures(enable_reg)
|
||||
.unwrap()
|
||||
.get(1)
|
||||
.unwrap()
|
||||
.as_str()
|
||||
}
|
||||
};
|
||||
|
||||
let clock = if name.starts_with("TIM") {
|
||||
format!("{}_tim", clock.to_ascii_lowercase())
|
||||
} else {
|
||||
clock.to_ascii_lowercase()
|
||||
};
|
||||
|
||||
let mut row = Vec::with_capacity(6);
|
||||
row.push(name.clone());
|
||||
row.push(clock);
|
||||
row.push(enable_reg.to_ascii_lowercase());
|
||||
|
||||
if let Some((reset_reg, reset_field)) = reset_reg_field {
|
||||
row.push(reset_reg.to_ascii_lowercase());
|
||||
row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
|
||||
row.push(format!("set_{}", reset_field.to_ascii_lowercase()));
|
||||
} else {
|
||||
row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
|
||||
}
|
||||
|
||||
if !name.starts_with("GPIO") {
|
||||
peripheral_rcc_table.push(row);
|
||||
} else {
|
||||
gpio_rcc_table.push(row);
|
||||
gpio_regs.insert(enable_reg.to_ascii_lowercase());
|
||||
}
|
||||
}
|
||||
(None, Some(_)) => {
|
||||
println!("Unable to find enable register for {}", name)
|
||||
}
|
||||
(None, None) => {
|
||||
println!("Unable to find enable and reset register for {}", name)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
dev.peripherals.push(ir_peri);
|
||||
}
|
||||
|
||||
for reg in gpio_regs {
|
||||
gpio_rcc_table.push(vec![reg]);
|
||||
}
|
||||
|
||||
// We should always find GPIO RCC regs. If not, it means something
|
||||
// is broken and GPIO won't work because it's not enabled.
|
||||
assert!(!gpio_rcc_table.is_empty());
|
||||
|
||||
for (id, channel_info) in &core.dma_channels {
|
||||
let mut row = Vec::new();
|
||||
let dma_peri = core.peripherals.get(&channel_info.dma).unwrap();
|
||||
let bi = BlockInfo::parse(dma_peri.block.as_ref().unwrap());
|
||||
|
||||
row.push(id.clone());
|
||||
row.push(channel_info.dma.clone());
|
||||
row.push(bi.module.clone());
|
||||
row.push(channel_info.channel.to_string());
|
||||
if let Some(dmamux) = &channel_info.dmamux {
|
||||
let dmamux_channel = channel_info.dmamux_channel.unwrap();
|
||||
row.push(format!(
|
||||
"{{dmamux: {}, dmamux_channel: {}}}",
|
||||
dmamux, dmamux_channel
|
||||
));
|
||||
} else {
|
||||
row.push("{}".to_string());
|
||||
}
|
||||
|
||||
dma_channels_table.push(row);
|
||||
|
||||
let dma_peri_name = channel_info.dma.clone();
|
||||
dma_channel_counts.insert(
|
||||
dma_peri_name.clone(),
|
||||
dma_channel_counts.get(&dma_peri_name).map_or(1, |v| v + 1),
|
||||
);
|
||||
}
|
||||
|
||||
for (name, &num) in &core.interrupts {
|
||||
dev.interrupts.push(ir::Interrupt {
|
||||
name: name.clone(),
|
||||
description: None,
|
||||
value: num,
|
||||
});
|
||||
|
||||
let name = name.to_ascii_uppercase();
|
||||
|
||||
interrupt_table.push(vec![name.clone()]);
|
||||
|
||||
if name.contains("EXTI") {
|
||||
interrupt_table.push(vec!["EXTI".to_string(), name.clone()]);
|
||||
}
|
||||
}
|
||||
|
||||
ir.devices.insert("".to_string(), dev);
|
||||
|
||||
let mut extra = format!(
|
||||
"pub fn GPIO(n: usize) -> gpio::Gpio {{
|
||||
gpio::Gpio(({} + {}*n) as _)
|
||||
}}",
|
||||
gpio_base, gpio_stride,
|
||||
);
|
||||
|
||||
let peripheral_version_table = peripheral_versions
|
||||
.iter()
|
||||
.map(|(kind, version)| vec![kind.clone(), version.clone()])
|
||||
.collect();
|
||||
|
||||
make_table(&mut extra, "pins", &pin_table);
|
||||
make_table(&mut extra, "interrupts", &interrupt_table);
|
||||
make_table(&mut extra, "peripherals", &peripherals_table);
|
||||
make_table(&mut extra, "peripheral_versions", &peripheral_version_table);
|
||||
make_table(&mut extra, "peripheral_pins", &peripheral_pins_table);
|
||||
make_table(
|
||||
&mut extra,
|
||||
"peripheral_dma_channels",
|
||||
&peripheral_dma_channels_table,
|
||||
);
|
||||
make_table(&mut extra, "peripheral_rcc", &peripheral_rcc_table);
|
||||
make_table(&mut extra, "gpio_rcc", &gpio_rcc_table);
|
||||
make_table(&mut extra, "dma_channels", &dma_channels_table);
|
||||
make_table(&mut extra, "dbgmcu", &dbgmcu_table);
|
||||
make_peripheral_counts(&mut extra, &peripheral_counts);
|
||||
make_dma_channel_counts(&mut extra, &dma_channel_counts);
|
||||
|
||||
for (module, version) in peripheral_versions {
|
||||
all_peripheral_versions.insert((module.clone(), version.clone()));
|
||||
write!(
|
||||
&mut extra,
|
||||
"#[path=\"../../peripherals/{}_{}.rs\"] pub mod {};\n",
|
||||
module, version, module
|
||||
)
|
||||
.unwrap();
|
||||
}
|
||||
write!(
|
||||
&mut extra,
|
||||
"pub const CORE_INDEX: usize = {};\n",
|
||||
core_index
|
||||
)
|
||||
.unwrap();
|
||||
|
||||
// Cleanups!
|
||||
transform::sort::Sort {}.run(&mut ir).unwrap();
|
||||
transform::Sanitize {}.run(&mut ir).unwrap();
|
||||
|
||||
let chip_dir = options
|
||||
.out_dir
|
||||
.join("src/chips")
|
||||
.join(chip_core_name.to_ascii_lowercase());
|
||||
fs::create_dir_all(&chip_dir).unwrap();
|
||||
|
||||
let generate_opts = generate::Options {
|
||||
common_module: CommonModule::Builtin,
|
||||
};
|
||||
let items = generate::render(&ir, &generate_opts).unwrap();
|
||||
let mut file = File::create(chip_dir.join("pac.rs")).unwrap();
|
||||
let data = items.to_string().replace("] ", "]\n");
|
||||
|
||||
// Remove inner attributes like #![no_std]
|
||||
let re = Regex::new("# *! *\\[.*\\]").unwrap();
|
||||
let data = re.replace_all(&data, "");
|
||||
file.write_all(data.as_bytes()).unwrap();
|
||||
file.write_all(extra.as_bytes()).unwrap();
|
||||
|
||||
let mut device_x = String::new();
|
||||
|
||||
for (name, _) in &core.interrupts {
|
||||
write!(
|
||||
&mut device_x,
|
||||
"PROVIDE({} = DefaultHandler);\n",
|
||||
name.to_ascii_uppercase()
|
||||
)
|
||||
.unwrap();
|
||||
}
|
||||
|
||||
File::create(chip_dir.join("device.x"))
|
||||
.unwrap()
|
||||
.write_all(device_x.as_bytes())
|
||||
.unwrap();
|
||||
|
||||
// generate default memory.x
|
||||
gen_memory_x(&chip_dir, &chip);
|
||||
}
|
||||
|
||||
fn load_chip(options: &Options, name: &str) -> Chip {
|
||||
let chip_path = options
|
||||
.data_dir
|
||||
.join("chips")
|
||||
.join(&format!("{}.yaml", name));
|
||||
let chip = fs::read(chip_path).expect(&format!("Could not load chip {}", name));
|
||||
serde_yaml::from_slice(&chip).unwrap()
|
||||
}
|
||||
|
||||
pub fn gen(options: Options) {
|
||||
let generate_opts = generate::Options {
|
||||
common_module: CommonModule::Builtin,
|
||||
};
|
||||
|
||||
let out_dir = options.out_dir;
|
||||
let data_dir = options.data_dir;
|
||||
|
||||
fs::create_dir_all(out_dir.join("src/peripherals")).unwrap();
|
||||
fs::create_dir_all(out_dir.join("src/chips")).unwrap();
|
||||
|
||||
println!("cwd: {:?}", env::current_dir());
|
||||
fs::create_dir_all(options.out_dir.join("src/peripherals")).unwrap();
|
||||
fs::create_dir_all(options.out_dir.join("src/chips")).unwrap();
|
||||
|
||||
let mut all_peripheral_versions: HashSet<(String, String)> = HashSet::new();
|
||||
let mut chip_cores: BTreeMap<String, Option<String>> = BTreeMap::new();
|
||||
let mut chip_core_names: Vec<String> = Vec::new();
|
||||
|
||||
for chip_name in &options.chips {
|
||||
let mut s = chip_name.split('_');
|
||||
let mut chip_name: String = s.next().unwrap().to_string();
|
||||
let core_name: Option<&str> = if let Some(c) = s.next() {
|
||||
if !c.starts_with("CM") {
|
||||
println!("Core not detected, adding as variant");
|
||||
chip_name.push('-');
|
||||
chip_name.push_str(c);
|
||||
None
|
||||
} else {
|
||||
println!("Detected core {}", c);
|
||||
Some(c)
|
||||
}
|
||||
} else {
|
||||
None
|
||||
};
|
||||
|
||||
chip_cores.insert(
|
||||
chip_name.to_string(),
|
||||
core_name.map(|s| s.to_ascii_lowercase().to_string()),
|
||||
);
|
||||
|
||||
let chip_path = data_dir.join("chips").join(&format!("{}.yaml", chip_name));
|
||||
println!("chip_path: {:?}", chip_path);
|
||||
let chip = fs::read(chip_path).unwrap();
|
||||
let chip: Chip = serde_yaml::from_slice(&chip).unwrap();
|
||||
|
||||
println!("looking for core {:?}", core_name);
|
||||
let core: Option<(&Core, usize)> = if let Some(core_name) = core_name {
|
||||
let core_name = core_name.to_ascii_lowercase();
|
||||
let mut c = None;
|
||||
let mut idx = 0;
|
||||
for (i, core) in chip.cores.iter().enumerate() {
|
||||
if core.name == core_name {
|
||||
c = Some(core);
|
||||
idx = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
c.map(|c| (c, idx))
|
||||
} else {
|
||||
Some((&chip.cores[0], 0))
|
||||
};
|
||||
|
||||
let (core, core_index) = core.unwrap();
|
||||
let core_name = &core.name;
|
||||
|
||||
let mut ir = ir::IR::new();
|
||||
|
||||
let mut dev = ir::Device {
|
||||
interrupts: Vec::new(),
|
||||
peripherals: Vec::new(),
|
||||
};
|
||||
|
||||
// Load DBGMCU register for chip
|
||||
let mut dbgmcu: Option<ir::IR> = core.peripherals.iter().find_map(|(name, p)| {
|
||||
if name == "DBGMCU" {
|
||||
p.block.as_ref().map(|block| {
|
||||
let bi = BlockInfo::parse(block);
|
||||
let dbgmcu_reg_path = data_dir
|
||||
.join("registers")
|
||||
.join(&format!("{}_{}.yaml", bi.module, bi.version));
|
||||
serde_yaml::from_reader(File::open(dbgmcu_reg_path).unwrap()).unwrap()
|
||||
})
|
||||
} else {
|
||||
None
|
||||
}
|
||||
});
|
||||
|
||||
// Load RCC register for chip
|
||||
let (_, rcc) = core
|
||||
.peripherals
|
||||
.iter()
|
||||
.find(|(name, _)| name == &"RCC")
|
||||
.expect("RCC peripheral missing");
|
||||
|
||||
let rcc_block = rcc.block.as_ref().expect("RCC peripheral has no block");
|
||||
let bi = BlockInfo::parse(&rcc_block);
|
||||
let rcc_reg_path = data_dir
|
||||
.join("registers")
|
||||
.join(&format!("{}_{}.yaml", bi.module, bi.version));
|
||||
let rcc: IR = serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap();
|
||||
|
||||
let mut peripheral_versions: BTreeMap<String, String> = BTreeMap::new();
|
||||
let mut pin_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut interrupt_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut peripherals_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut peripheral_pins_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut peripheral_rcc_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut dma_channels_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut peripheral_dma_channels_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut peripheral_counts: BTreeMap<String, u8> = BTreeMap::new();
|
||||
let mut dma_channel_counts: BTreeMap<String, u8> = BTreeMap::new();
|
||||
let mut dbgmcu_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut gpio_rcc_table: Vec<Vec<String>> = Vec::new();
|
||||
let mut gpio_regs: HashSet<String> = HashSet::new();
|
||||
|
||||
let gpio_base = core.peripherals.get(&"GPIOA".to_string()).unwrap().address as u32;
|
||||
let gpio_stride = 0x400;
|
||||
|
||||
let number_suffix_re = Regex::new("^(.*?)[0-9]*$").unwrap();
|
||||
|
||||
if let Some(ref mut reg) = dbgmcu {
|
||||
if let Some(ref cr) = reg.fieldsets.get("CR") {
|
||||
for field in cr.fields.iter().filter(|e| e.name.contains("DBG")) {
|
||||
let mut fn_name = String::new();
|
||||
fn_name.push_str("set_");
|
||||
fn_name.push_str(&field.name.to_sanitized_snake_case());
|
||||
dbgmcu_table.push(vec!["cr".into(), fn_name]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (name, p) in &core.peripherals {
|
||||
let captures = number_suffix_re.captures(&name).unwrap();
|
||||
let root_peri_name = captures.get(1).unwrap().as_str().to_string();
|
||||
peripheral_counts.insert(
|
||||
root_peri_name.clone(),
|
||||
peripheral_counts.get(&root_peri_name).map_or(1, |v| v + 1),
|
||||
);
|
||||
let mut ir_peri = ir::Peripheral {
|
||||
name: name.clone(),
|
||||
array: None,
|
||||
base_address: p.address,
|
||||
block: None,
|
||||
description: None,
|
||||
interrupts: HashMap::new(),
|
||||
let chip = load_chip(&options, chip_name);
|
||||
for (core_index, core) in chip.cores.iter().enumerate() {
|
||||
let chip_core_name = match chip.cores.len() {
|
||||
1 => chip_name.clone(),
|
||||
_ => format!("{}-{}", chip_name, core.name),
|
||||
};
|
||||
|
||||
if let Some(block) = &p.block {
|
||||
let bi = BlockInfo::parse(block);
|
||||
|
||||
peripheral_counts.insert(
|
||||
bi.module.clone(),
|
||||
peripheral_counts.get(&bi.module).map_or(1, |v| v + 1),
|
||||
);
|
||||
|
||||
for pin in &p.pins {
|
||||
let mut row = Vec::new();
|
||||
row.push(name.clone());
|
||||
row.push(bi.module.clone());
|
||||
row.push(bi.block.clone());
|
||||
row.push(pin.pin.clone());
|
||||
row.push(pin.signal.clone());
|
||||
if let Some(ref af) = pin.af {
|
||||
row.push(af.clone());
|
||||
}
|
||||
peripheral_pins_table.push(row);
|
||||
}
|
||||
|
||||
for (signal, irq_name) in &p.interrupts {
|
||||
let mut row = Vec::new();
|
||||
row.push(name.clone());
|
||||
row.push(bi.module.clone());
|
||||
row.push(bi.block.clone());
|
||||
row.push(signal.clone());
|
||||
row.push(irq_name.to_ascii_uppercase());
|
||||
interrupt_table.push(row)
|
||||
}
|
||||
|
||||
for (request, dma_channels) in &p.dma_channels {
|
||||
for channel in dma_channels.iter() {
|
||||
let mut row = Vec::new();
|
||||
row.push(name.clone());
|
||||
row.push(bi.module.clone());
|
||||
row.push(bi.block.clone());
|
||||
row.push(request.clone());
|
||||
row.push(if let Some(channel) = &channel.channel {
|
||||
format!("{{channel: {}}}", channel)
|
||||
} else if let Some(dmamux) = &channel.dmamux {
|
||||
format!("{{dmamux: {}}}", dmamux)
|
||||
} else {
|
||||
unreachable!();
|
||||
});
|
||||
|
||||
row.push(if let Some(request) = channel.request {
|
||||
request.to_string()
|
||||
} else {
|
||||
"()".to_string()
|
||||
});
|
||||
|
||||
if peripheral_dma_channels_table
|
||||
.iter()
|
||||
.find(|a| a[..a.len() - 1] == row[..row.len() - 1])
|
||||
.is_none()
|
||||
{
|
||||
peripheral_dma_channels_table.push(row);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
let mut peripheral_row = Vec::new();
|
||||
peripheral_row.push(bi.module.clone());
|
||||
peripheral_row.push(name.clone());
|
||||
peripherals_table.push(peripheral_row);
|
||||
|
||||
if let Some(old_version) =
|
||||
peripheral_versions.insert(bi.module.clone(), bi.version.clone())
|
||||
{
|
||||
if old_version != bi.version {
|
||||
panic!(
|
||||
"Peripheral {} has multiple versions: {} and {}",
|
||||
bi.module, old_version, bi.version
|
||||
);
|
||||
}
|
||||
}
|
||||
ir_peri.block = Some(format!("{}::{}", bi.module, bi.block));
|
||||
|
||||
match bi.module.as_str() {
|
||||
"gpio" => {
|
||||
let port_letter = name.chars().skip(4).next().unwrap();
|
||||
assert_eq!(0, (p.address as u32 - gpio_base) % gpio_stride);
|
||||
let port_num = (p.address as u32 - gpio_base) / gpio_stride;
|
||||
|
||||
for pin_num in 0..16 {
|
||||
let pin_name = format!("P{}{}", port_letter, pin_num);
|
||||
pin_table.push(vec![
|
||||
pin_name.clone(),
|
||||
name.clone(),
|
||||
port_num.to_string(),
|
||||
pin_num.to_string(),
|
||||
format!("EXTI{}", pin_num),
|
||||
]);
|
||||
}
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
|
||||
// Workaround for clock registers being split on some chip families. Assume fields are
|
||||
// named after peripheral and look for first field matching and use that register.
|
||||
let mut en = find_reg(&rcc, "^.+ENR\\d*$", &format!("{}EN", name));
|
||||
let mut rst = find_reg(&rcc, "^.+RSTR\\d*$", &format!("{}RST", name));
|
||||
|
||||
if en.is_none() && name.ends_with("1") {
|
||||
en = find_reg(
|
||||
&rcc,
|
||||
"^.+ENR\\d*$",
|
||||
&format!("{}EN", &name[..name.len() - 1]),
|
||||
);
|
||||
rst = find_reg(
|
||||
&rcc,
|
||||
"^.+RSTR\\d*$",
|
||||
&format!("{}RST", &name[..name.len() - 1]),
|
||||
);
|
||||
}
|
||||
|
||||
match (en, rst) {
|
||||
(Some((enable_reg, enable_field)), reset_reg_field) => {
|
||||
let clock = match &p.clock {
|
||||
Some(clock) => clock.as_str(),
|
||||
None => {
|
||||
// No clock was specified, derive the clock name from the enable register name.
|
||||
// N.B. STM32G0 has only one APB bus but split ENR registers
|
||||
// (e.g. APBENR1).
|
||||
Regex::new("([A-Z]+\\d*)ENR\\d*")
|
||||
.unwrap()
|
||||
.captures(enable_reg)
|
||||
.unwrap()
|
||||
.get(1)
|
||||
.unwrap()
|
||||
.as_str()
|
||||
}
|
||||
};
|
||||
|
||||
let clock = if name.starts_with("TIM") {
|
||||
format!("{}_tim", clock.to_ascii_lowercase())
|
||||
} else {
|
||||
clock.to_ascii_lowercase()
|
||||
};
|
||||
|
||||
let mut row = Vec::with_capacity(6);
|
||||
row.push(name.clone());
|
||||
row.push(clock);
|
||||
row.push(enable_reg.to_ascii_lowercase());
|
||||
|
||||
if let Some((reset_reg, reset_field)) = reset_reg_field {
|
||||
row.push(reset_reg.to_ascii_lowercase());
|
||||
row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
|
||||
row.push(format!("set_{}", reset_field.to_ascii_lowercase()));
|
||||
} else {
|
||||
row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
|
||||
}
|
||||
|
||||
if !name.starts_with("GPIO") {
|
||||
peripheral_rcc_table.push(row);
|
||||
} else {
|
||||
gpio_rcc_table.push(row);
|
||||
gpio_regs.insert(enable_reg.to_ascii_lowercase());
|
||||
}
|
||||
}
|
||||
(None, Some(_)) => {
|
||||
println!("Unable to find enable register for {}", name)
|
||||
}
|
||||
(None, None) => {
|
||||
println!("Unable to find enable and reset register for {}", name)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
dev.peripherals.push(ir_peri);
|
||||
}
|
||||
|
||||
for reg in gpio_regs {
|
||||
gpio_rcc_table.push(vec![reg]);
|
||||
}
|
||||
|
||||
// We should always find GPIO RCC regs. If not, it means something
|
||||
// is broken and GPIO won't work because it's not enabled.
|
||||
assert!(!gpio_rcc_table.is_empty());
|
||||
|
||||
for (id, channel_info) in &core.dma_channels {
|
||||
let mut row = Vec::new();
|
||||
let dma_peri = core.peripherals.get(&channel_info.dma).unwrap();
|
||||
let bi = BlockInfo::parse(dma_peri.block.as_ref().unwrap());
|
||||
|
||||
row.push(id.clone());
|
||||
row.push(channel_info.dma.clone());
|
||||
row.push(bi.module.clone());
|
||||
row.push(channel_info.channel.to_string());
|
||||
if let Some(dmamux) = &channel_info.dmamux {
|
||||
let dmamux_channel = channel_info.dmamux_channel.unwrap();
|
||||
row.push(format!(
|
||||
"{{dmamux: {}, dmamux_channel: {}}}",
|
||||
dmamux, dmamux_channel
|
||||
));
|
||||
} else {
|
||||
row.push("{}".to_string());
|
||||
}
|
||||
|
||||
dma_channels_table.push(row);
|
||||
|
||||
let dma_peri_name = channel_info.dma.clone();
|
||||
dma_channel_counts.insert(
|
||||
dma_peri_name.clone(),
|
||||
dma_channel_counts.get(&dma_peri_name).map_or(1, |v| v + 1),
|
||||
);
|
||||
}
|
||||
|
||||
for (name, &num) in &core.interrupts {
|
||||
dev.interrupts.push(ir::Interrupt {
|
||||
name: name.clone(),
|
||||
description: None,
|
||||
value: num,
|
||||
});
|
||||
|
||||
let name = name.to_ascii_uppercase();
|
||||
|
||||
interrupt_table.push(vec![name.clone()]);
|
||||
|
||||
if name.contains("EXTI") {
|
||||
interrupt_table.push(vec!["EXTI".to_string(), name.clone()]);
|
||||
}
|
||||
}
|
||||
|
||||
ir.devices.insert("".to_string(), dev);
|
||||
|
||||
let mut extra = format!(
|
||||
"pub fn GPIO(n: usize) -> gpio::Gpio {{
|
||||
gpio::Gpio(({} + {}*n) as _)
|
||||
}}",
|
||||
gpio_base, gpio_stride,
|
||||
);
|
||||
|
||||
let peripheral_version_table = peripheral_versions
|
||||
.iter()
|
||||
.map(|(kind, version)| vec![kind.clone(), version.clone()])
|
||||
.collect();
|
||||
|
||||
make_table(&mut extra, "pins", &pin_table);
|
||||
make_table(&mut extra, "interrupts", &interrupt_table);
|
||||
make_table(&mut extra, "peripherals", &peripherals_table);
|
||||
make_table(&mut extra, "peripheral_versions", &peripheral_version_table);
|
||||
make_table(&mut extra, "peripheral_pins", &peripheral_pins_table);
|
||||
make_table(
|
||||
&mut extra,
|
||||
"peripheral_dma_channels",
|
||||
&peripheral_dma_channels_table,
|
||||
);
|
||||
make_table(&mut extra, "peripheral_rcc", &peripheral_rcc_table);
|
||||
make_table(&mut extra, "gpio_rcc", &gpio_rcc_table);
|
||||
make_table(&mut extra, "dma_channels", &dma_channels_table);
|
||||
make_table(&mut extra, "dbgmcu", &dbgmcu_table);
|
||||
make_peripheral_counts(&mut extra, &peripheral_counts);
|
||||
make_dma_channel_counts(&mut extra, &dma_channel_counts);
|
||||
|
||||
for (module, version) in peripheral_versions {
|
||||
all_peripheral_versions.insert((module.clone(), version.clone()));
|
||||
write!(
|
||||
&mut extra,
|
||||
"#[path=\"../../peripherals/{}_{}.rs\"] pub mod {};\n",
|
||||
module, version, module
|
||||
chip_core_names.push(chip_core_name.clone());
|
||||
gen_chip(
|
||||
&options,
|
||||
&chip_core_name,
|
||||
&chip,
|
||||
core,
|
||||
core_index,
|
||||
&mut all_peripheral_versions,
|
||||
)
|
||||
.unwrap();
|
||||
}
|
||||
write!(
|
||||
&mut extra,
|
||||
"pub const CORE_INDEX: usize = {};\n",
|
||||
core_index
|
||||
)
|
||||
.unwrap();
|
||||
|
||||
// Cleanups!
|
||||
transform::sort::Sort {}.run(&mut ir).unwrap();
|
||||
transform::Sanitize {}.run(&mut ir).unwrap();
|
||||
|
||||
let chip_dir = if chip.cores.len() > 1 {
|
||||
out_dir.join("src/chips").join(format!(
|
||||
"{}_{}",
|
||||
chip_name.to_ascii_lowercase(),
|
||||
core_name.to_ascii_lowercase()
|
||||
))
|
||||
} else {
|
||||
out_dir
|
||||
.join("src/chips")
|
||||
.join(chip_name.to_ascii_lowercase())
|
||||
};
|
||||
fs::create_dir_all(&chip_dir).unwrap();
|
||||
|
||||
let items = generate::render(&ir, &generate_opts).unwrap();
|
||||
let mut file = File::create(chip_dir.join("pac.rs")).unwrap();
|
||||
let data = items.to_string().replace("] ", "]\n");
|
||||
|
||||
// Remove inner attributes like #![no_std]
|
||||
let re = Regex::new("# *! *\\[.*\\]").unwrap();
|
||||
let data = re.replace_all(&data, "");
|
||||
file.write_all(data.as_bytes()).unwrap();
|
||||
file.write_all(extra.as_bytes()).unwrap();
|
||||
|
||||
let mut device_x = String::new();
|
||||
|
||||
for (name, _) in &core.interrupts {
|
||||
write!(
|
||||
&mut device_x,
|
||||
"PROVIDE({} = DefaultHandler);\n",
|
||||
name.to_ascii_uppercase()
|
||||
)
|
||||
.unwrap();
|
||||
}
|
||||
|
||||
File::create(chip_dir.join("device.x"))
|
||||
.unwrap()
|
||||
.write_all(device_x.as_bytes())
|
||||
.unwrap();
|
||||
|
||||
// generate default memory.x
|
||||
gen_memory_x(&chip_dir, &chip);
|
||||
}
|
||||
|
||||
for (module, version) in all_peripheral_versions {
|
||||
println!("loading {} {}", module, version);
|
||||
|
||||
let regs_path = Path::new(&data_dir)
|
||||
let regs_path = Path::new(&options.data_dir)
|
||||
.join("registers")
|
||||
.join(&format!("{}_{}.yaml", module, version));
|
||||
|
||||
|
|
@ -587,7 +569,8 @@ pub fn gen(options: Options) {
|
|||
|
||||
let items = generate::render(&ir, &generate_opts).unwrap();
|
||||
let mut file = File::create(
|
||||
out_dir
|
||||
options
|
||||
.out_dir
|
||||
.join("src/peripherals")
|
||||
.join(format!("{}_{}.rs", module, version)),
|
||||
)
|
||||
|
|
@ -606,29 +589,20 @@ pub fn gen(options: Options) {
|
|||
let i = bytes_find(librs, PATHS_MARKER).unwrap();
|
||||
let mut paths = String::new();
|
||||
|
||||
for (chip, cores) in chip_cores.iter() {
|
||||
let x = chip.to_ascii_lowercase();
|
||||
if let Some(c) = cores {
|
||||
write!(
|
||||
&mut paths,
|
||||
"#[cfg_attr(feature=\"{}_{}\", path = \"chips/{}_{}/pac.rs\")]",
|
||||
x, c, x, c
|
||||
)
|
||||
.unwrap();
|
||||
} else {
|
||||
write!(
|
||||
&mut paths,
|
||||
"#[cfg_attr(feature=\"{}\", path = \"chips/{}/pac.rs\")]",
|
||||
x, x
|
||||
)
|
||||
.unwrap();
|
||||
}
|
||||
for name in chip_core_names {
|
||||
let x = name.to_ascii_lowercase();
|
||||
write!(
|
||||
&mut paths,
|
||||
"#[cfg_attr(feature=\"{}\", path = \"chips/{}/pac.rs\")]",
|
||||
x, x
|
||||
)
|
||||
.unwrap();
|
||||
}
|
||||
let mut contents: Vec<u8> = Vec::new();
|
||||
contents.extend(&librs[..i]);
|
||||
contents.extend(paths.as_bytes());
|
||||
contents.extend(&librs[i + PATHS_MARKER.len()..]);
|
||||
fs::write(out_dir.join("src").join("lib_inner.rs"), &contents).unwrap();
|
||||
fs::write(options.out_dir.join("src").join("lib_inner.rs"), &contents).unwrap();
|
||||
|
||||
// Generate src/lib.rs
|
||||
const CUT_MARKER: &[u8] = b"// GEN CUT HERE";
|
||||
|
|
@ -637,11 +611,11 @@ pub fn gen(options: Options) {
|
|||
let mut contents: Vec<u8> = Vec::new();
|
||||
contents.extend(&librs[..i]);
|
||||
contents.extend(b"include!(\"lib_inner.rs\");\n");
|
||||
fs::write(out_dir.join("src").join("lib.rs"), contents).unwrap();
|
||||
fs::write(options.out_dir.join("src").join("lib.rs"), contents).unwrap();
|
||||
|
||||
// Generate src/common.rs
|
||||
fs::write(
|
||||
out_dir.join("src").join("common.rs"),
|
||||
options.out_dir.join("src").join("common.rs"),
|
||||
generate::COMMON_MODULE,
|
||||
)
|
||||
.unwrap();
|
||||
|
|
@ -654,10 +628,14 @@ pub fn gen(options: Options) {
|
|||
let begin = bytes_find(&contents, BUILDDEP_BEGIN).unwrap();
|
||||
let end = bytes_find(&contents, BUILDDEP_END).unwrap() + BUILDDEP_END.len();
|
||||
contents.drain(begin..end);
|
||||
fs::write(out_dir.join("Cargo.toml"), contents).unwrap();
|
||||
fs::write(options.out_dir.join("Cargo.toml"), contents).unwrap();
|
||||
|
||||
// Generate build.rs
|
||||
fs::write(out_dir.join("build.rs"), include_bytes!("assets/build.rs")).unwrap();
|
||||
fs::write(
|
||||
options.out_dir.join("build.rs"),
|
||||
include_bytes!("assets/build.rs"),
|
||||
)
|
||||
.unwrap();
|
||||
}
|
||||
|
||||
fn bytes_find(haystack: &[u8], needle: &[u8]) -> Option<usize> {
|
||||
|
|
|
|||
|
|
@ -17,7 +17,6 @@ fn main() {
|
|||
.unwrap()
|
||||
.filter_map(|res| res.unwrap().file_name().to_str().map(|s| s.to_string()))
|
||||
.filter(|s| s.ends_with(".yaml"))
|
||||
.filter(|s| !s.starts_with("STM32L1")) // cursed gpio stride
|
||||
.filter(|s| !s.starts_with("STM32GBK")) // cursed weird STM32G4
|
||||
.map(|s| s.strip_suffix(".yaml").unwrap().to_string())
|
||||
.collect()
|
||||
|
|
|
|||
|
|
@ -780,40 +780,40 @@ stm32h743xg = []
|
|||
stm32h743xi = []
|
||||
stm32h743zg = []
|
||||
stm32h743zi = []
|
||||
stm32h745bg_cm7 = []
|
||||
stm32h745bg_cm4 = []
|
||||
stm32h745bi_cm7 = []
|
||||
stm32h745bi_cm4 = []
|
||||
stm32h745ig_cm7 = []
|
||||
stm32h745ig_cm4 = []
|
||||
stm32h745ii_cm7 = []
|
||||
stm32h745ii_cm4 = []
|
||||
stm32h745xg_cm7 = []
|
||||
stm32h745xg_cm4 = []
|
||||
stm32h745xi_cm7 = []
|
||||
stm32h745xi_cm4 = []
|
||||
stm32h745zg_cm7 = []
|
||||
stm32h745zg_cm4 = []
|
||||
stm32h745zi_cm7 = []
|
||||
stm32h745zi_cm4 = []
|
||||
stm32h747ag_cm7 = []
|
||||
stm32h747ag_cm4 = []
|
||||
stm32h747ai_cm7 = []
|
||||
stm32h747ai_cm4 = []
|
||||
stm32h747bg_cm7 = []
|
||||
stm32h747bg_cm4 = []
|
||||
stm32h747bi_cm7 = []
|
||||
stm32h747bi_cm4 = []
|
||||
stm32h747ig_cm7 = []
|
||||
stm32h747ig_cm4 = []
|
||||
stm32h747ii_cm7 = []
|
||||
stm32h747ii_cm4 = []
|
||||
stm32h747xg_cm7 = []
|
||||
stm32h747xg_cm4 = []
|
||||
stm32h747xi_cm7 = []
|
||||
stm32h747xi_cm4 = []
|
||||
stm32h747zi_cm7 = []
|
||||
stm32h747zi_cm4 = []
|
||||
stm32h745bg-cm7 = []
|
||||
stm32h745bg-cm4 = []
|
||||
stm32h745bi-cm7 = []
|
||||
stm32h745bi-cm4 = []
|
||||
stm32h745ig-cm7 = []
|
||||
stm32h745ig-cm4 = []
|
||||
stm32h745ii-cm7 = []
|
||||
stm32h745ii-cm4 = []
|
||||
stm32h745xg-cm7 = []
|
||||
stm32h745xg-cm4 = []
|
||||
stm32h745xi-cm7 = []
|
||||
stm32h745xi-cm4 = []
|
||||
stm32h745zg-cm7 = []
|
||||
stm32h745zg-cm4 = []
|
||||
stm32h745zi-cm7 = []
|
||||
stm32h745zi-cm4 = []
|
||||
stm32h747ag-cm7 = []
|
||||
stm32h747ag-cm4 = []
|
||||
stm32h747ai-cm7 = []
|
||||
stm32h747ai-cm4 = []
|
||||
stm32h747bg-cm7 = []
|
||||
stm32h747bg-cm4 = []
|
||||
stm32h747bi-cm7 = []
|
||||
stm32h747bi-cm4 = []
|
||||
stm32h747ig-cm7 = []
|
||||
stm32h747ig-cm4 = []
|
||||
stm32h747ii-cm7 = []
|
||||
stm32h747ii-cm4 = []
|
||||
stm32h747xg-cm7 = []
|
||||
stm32h747xg-cm4 = []
|
||||
stm32h747xi-cm7 = []
|
||||
stm32h747xi-cm4 = []
|
||||
stm32h747zi-cm7 = []
|
||||
stm32h747zi-cm4 = []
|
||||
stm32h750ib = []
|
||||
stm32h750vb = []
|
||||
stm32h750xb = []
|
||||
|
|
@ -824,24 +824,24 @@ stm32h753ii = []
|
|||
stm32h753vi = []
|
||||
stm32h753xi = []
|
||||
stm32h753zi = []
|
||||
stm32h755bi_cm7 = []
|
||||
stm32h755bi_cm4 = []
|
||||
stm32h755ii_cm7 = []
|
||||
stm32h755ii_cm4 = []
|
||||
stm32h755xi_cm7 = []
|
||||
stm32h755xi_cm4 = []
|
||||
stm32h755zi_cm7 = []
|
||||
stm32h755zi_cm4 = []
|
||||
stm32h757ai_cm7 = []
|
||||
stm32h757ai_cm4 = []
|
||||
stm32h757bi_cm7 = []
|
||||
stm32h757bi_cm4 = []
|
||||
stm32h757ii_cm7 = []
|
||||
stm32h757ii_cm4 = []
|
||||
stm32h757xi_cm7 = []
|
||||
stm32h757xi_cm4 = []
|
||||
stm32h757zi_cm7 = []
|
||||
stm32h757zi_cm4 = []
|
||||
stm32h755bi-cm7 = []
|
||||
stm32h755bi-cm4 = []
|
||||
stm32h755ii-cm7 = []
|
||||
stm32h755ii-cm4 = []
|
||||
stm32h755xi-cm7 = []
|
||||
stm32h755xi-cm4 = []
|
||||
stm32h755zi-cm7 = []
|
||||
stm32h755zi-cm4 = []
|
||||
stm32h757ai-cm7 = []
|
||||
stm32h757ai-cm4 = []
|
||||
stm32h757bi-cm7 = []
|
||||
stm32h757bi-cm4 = []
|
||||
stm32h757ii-cm7 = []
|
||||
stm32h757ii-cm4 = []
|
||||
stm32h757xi-cm7 = []
|
||||
stm32h757xi-cm4 = []
|
||||
stm32h757zi-cm7 = []
|
||||
stm32h757zi-cm4 = []
|
||||
stm32h7a3ag = []
|
||||
stm32h7a3ai = []
|
||||
stm32h7a3ig = []
|
||||
|
|
@ -1255,16 +1255,16 @@ stm32wb55ve = []
|
|||
stm32wb55vg = []
|
||||
stm32wb55vy = []
|
||||
stm32wb5mmg = []
|
||||
stm32wl54cc_cm4 = []
|
||||
stm32wl54cc_cm0p = []
|
||||
stm32wl54jc_cm4 = []
|
||||
stm32wl54jc_cm0p = []
|
||||
stm32wl55cc_cm4 = []
|
||||
stm32wl55cc_cm0p = []
|
||||
stm32wl55jc_cm4 = []
|
||||
stm32wl55jc_cm0p = []
|
||||
stm32wl55uc_cm4 = []
|
||||
stm32wl55uc_cm0p = []
|
||||
stm32wl54cc-cm4 = []
|
||||
stm32wl54cc-cm0p = []
|
||||
stm32wl54jc-cm4 = []
|
||||
stm32wl54jc-cm0p = []
|
||||
stm32wl55cc-cm4 = []
|
||||
stm32wl55cc-cm0p = []
|
||||
stm32wl55jc-cm4 = []
|
||||
stm32wl55jc-cm0p = []
|
||||
stm32wl55uc-cm4 = []
|
||||
stm32wl55uc-cm0p = []
|
||||
stm32wle4c8 = []
|
||||
stm32wle4cb = []
|
||||
stm32wle4cc = []
|
||||
|
|
|
|||
|
|
@ -2,48 +2,52 @@ use std::env;
|
|||
use std::path::PathBuf;
|
||||
use stm32_metapac_gen::*;
|
||||
|
||||
fn parse_chip_core(chip_and_core: &str) -> (String, Option<String>) {
|
||||
let mut s = chip_and_core.split('-');
|
||||
let chip_name: String = s.next().unwrap().to_string();
|
||||
if let Some(c) = s.next() {
|
||||
if c.starts_with("CM") {
|
||||
return (chip_name, Some(c.to_ascii_lowercase()));
|
||||
}
|
||||
}
|
||||
|
||||
(chip_and_core.to_string(), None)
|
||||
}
|
||||
|
||||
fn main() {
|
||||
let out_dir = PathBuf::from(env::var_os("OUT_DIR").unwrap());
|
||||
let data_dir = PathBuf::from("../stm32-data/data");
|
||||
|
||||
println!("cwd: {:?}", env::current_dir());
|
||||
|
||||
let chip_name = env::vars_os()
|
||||
let chip_core_name = env::vars_os()
|
||||
.map(|(a, _)| a.to_string_lossy().to_string())
|
||||
.find(|x| x.starts_with("CARGO_FEATURE_STM32"))
|
||||
.expect("No stm32xx Cargo feature enabled")
|
||||
.strip_prefix("CARGO_FEATURE_")
|
||||
.unwrap()
|
||||
.to_ascii_uppercase();
|
||||
.to_ascii_uppercase()
|
||||
.replace('_', "-");
|
||||
|
||||
let (chip_name, _) = parse_chip_core(&chip_core_name);
|
||||
|
||||
gen(Options {
|
||||
out_dir: out_dir.clone(),
|
||||
data_dir: data_dir.clone(),
|
||||
chips: vec![chip_name.clone()],
|
||||
chips: vec![chip_name],
|
||||
});
|
||||
|
||||
let mut s = chip_name.split('_');
|
||||
let mut chip_name: String = s.next().unwrap().to_string();
|
||||
if let Some(c) = s.next() {
|
||||
if !c.starts_with("CM") {
|
||||
chip_name.push('-');
|
||||
} else {
|
||||
chip_name.push('_');
|
||||
}
|
||||
chip_name.push_str(c);
|
||||
}
|
||||
|
||||
println!(
|
||||
"cargo:rustc-link-search={}/src/chips/{}",
|
||||
out_dir.display(),
|
||||
chip_name.to_ascii_lowercase()
|
||||
chip_core_name.to_ascii_lowercase()
|
||||
);
|
||||
|
||||
#[cfg(feature = "memory-x")]
|
||||
println!(
|
||||
"cargo:rustc-link-search={}/src/chips/{}/memory_x/",
|
||||
out_dir.display(),
|
||||
chip_name.to_ascii_lowercase()
|
||||
chip_core_name.to_ascii_lowercase()
|
||||
);
|
||||
|
||||
println!("cargo:rerun-if-changed=build.rs");
|
||||
|
|
|
|||
Loading…
Reference in a new issue