diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py
index cf04cc158..714ead373 100644
--- a/embassy-stm32/gen.py
+++ b/embassy-stm32/gen.py
@@ -67,6 +67,8 @@ for chip in chips.values():
     # We don't want to hardcode the EXTI peripheral addr
     peripherals.extend((f'EXTI{x}' for x in range(16)))
 
+    exti_base = chip['peripherals']['EXTI']['address']
+    syscfg_base = chip['peripherals']['SYSCFG']['address']
     gpio_base = chip['peripherals']['GPIOA']['address']
     gpio_stride = 0x400
 
@@ -129,6 +131,8 @@ for chip in chips.values():
         f.write(f"""
             use embassy_extras::peripherals;
             peripherals!({','.join(peripherals)});
+            pub const SYSCFG_BASE: usize = 0x{syscfg_base:x};
+            pub const EXTI_BASE: usize = 0x{exti_base:x};
             pub const GPIO_BASE: usize = 0x{gpio_base:x};
             pub const GPIO_STRIDE: usize = 0x{gpio_stride:x};
 
diff --git a/embassy-stm32/src/chip/stm32f401cb.rs b/embassy-stm32/src/chip/stm32f401cb.rs
index 654c39bdd..027fef5a2 100644
--- a/embassy-stm32/src/chip/stm32f401cb.rs
+++ b/embassy-stm32/src/chip/stm32f401cb.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3, TIM4,
-    TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3,
+    TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f401cc.rs b/embassy-stm32/src/chip/stm32f401cc.rs
index 654c39bdd..027fef5a2 100644
--- a/embassy-stm32/src/chip/stm32f401cc.rs
+++ b/embassy-stm32/src/chip/stm32f401cc.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3, TIM4,
-    TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3,
+    TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f401cd.rs b/embassy-stm32/src/chip/stm32f401cd.rs
index 654c39bdd..027fef5a2 100644
--- a/embassy-stm32/src/chip/stm32f401cd.rs
+++ b/embassy-stm32/src/chip/stm32f401cd.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3, TIM4,
-    TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3,
+    TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f401ce.rs b/embassy-stm32/src/chip/stm32f401ce.rs
index 654c39bdd..027fef5a2 100644
--- a/embassy-stm32/src/chip/stm32f401ce.rs
+++ b/embassy-stm32/src/chip/stm32f401ce.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3, TIM4,
-    TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3,
+    TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f401rb.rs b/embassy-stm32/src/chip/stm32f401rb.rs
index 5c413734a..163900e93 100644
--- a/embassy-stm32/src/chip/stm32f401rb.rs
+++ b/embassy-stm32/src/chip/stm32f401rb.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3,
-    TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2,
+    TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f401rc.rs b/embassy-stm32/src/chip/stm32f401rc.rs
index 5c413734a..163900e93 100644
--- a/embassy-stm32/src/chip/stm32f401rc.rs
+++ b/embassy-stm32/src/chip/stm32f401rc.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3,
-    TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2,
+    TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f401rd.rs b/embassy-stm32/src/chip/stm32f401rd.rs
index 5c413734a..163900e93 100644
--- a/embassy-stm32/src/chip/stm32f401rd.rs
+++ b/embassy-stm32/src/chip/stm32f401rd.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3,
-    TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2,
+    TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f401re.rs b/embassy-stm32/src/chip/stm32f401re.rs
index 5c413734a..163900e93 100644
--- a/embassy-stm32/src/chip/stm32f401re.rs
+++ b/embassy-stm32/src/chip/stm32f401re.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3,
-    TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2,
+    TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f401vb.rs b/embassy-stm32/src/chip/stm32f401vb.rs
index f9911116c..8976fb754 100644
--- a/embassy-stm32/src/chip/stm32f401vb.rs
+++ b/embassy-stm32/src/chip/stm32f401vb.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM2,
-    TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11,
+    TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f401vc.rs b/embassy-stm32/src/chip/stm32f401vc.rs
index f9911116c..8976fb754 100644
--- a/embassy-stm32/src/chip/stm32f401vc.rs
+++ b/embassy-stm32/src/chip/stm32f401vc.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM2,
-    TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11,
+    TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f401vd.rs b/embassy-stm32/src/chip/stm32f401vd.rs
index f9911116c..8976fb754 100644
--- a/embassy-stm32/src/chip/stm32f401vd.rs
+++ b/embassy-stm32/src/chip/stm32f401vd.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM2,
-    TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11,
+    TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f401ve.rs b/embassy-stm32/src/chip/stm32f401ve.rs
index f9911116c..8976fb754 100644
--- a/embassy-stm32/src/chip/stm32f401ve.rs
+++ b/embassy-stm32/src/chip/stm32f401ve.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM2,
-    TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11,
+    TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f405oe.rs b/embassy-stm32/src/chip/stm32f405oe.rs
index dcc229ce4..8cffccd9b 100644
--- a/embassy-stm32/src/chip/stm32f405oe.rs
+++ b/embassy-stm32/src/chip/stm32f405oe.rs
@@ -1,9 +1,9 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
     PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
     PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
     PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1,
     USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f405og.rs b/embassy-stm32/src/chip/stm32f405og.rs
index dcc229ce4..8cffccd9b 100644
--- a/embassy-stm32/src/chip/stm32f405og.rs
+++ b/embassy-stm32/src/chip/stm32f405og.rs
@@ -1,9 +1,9 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
     PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
     PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
     PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1,
     USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f405rg.rs b/embassy-stm32/src/chip/stm32f405rg.rs
index dcc229ce4..8cffccd9b 100644
--- a/embassy-stm32/src/chip/stm32f405rg.rs
+++ b/embassy-stm32/src/chip/stm32f405rg.rs
@@ -1,9 +1,9 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
     PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
     PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
     PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1,
     USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f405vg.rs b/embassy-stm32/src/chip/stm32f405vg.rs
index dcc229ce4..8cffccd9b 100644
--- a/embassy-stm32/src/chip/stm32f405vg.rs
+++ b/embassy-stm32/src/chip/stm32f405vg.rs
@@ -1,9 +1,9 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
     PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
     PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
     PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1,
     USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f405zg.rs b/embassy-stm32/src/chip/stm32f405zg.rs
index dcc229ce4..8cffccd9b 100644
--- a/embassy-stm32/src/chip/stm32f405zg.rs
+++ b/embassy-stm32/src/chip/stm32f405zg.rs
@@ -1,9 +1,9 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
     PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
     PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
     PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1,
     USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f407ie.rs b/embassy-stm32/src/chip/stm32f407ie.rs
index ac19c9844..f86038e1e 100644
--- a/embassy-stm32/src/chip/stm32f407ie.rs
+++ b/embassy-stm32/src/chip/stm32f407ie.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f407ig.rs b/embassy-stm32/src/chip/stm32f407ig.rs
index ac19c9844..f86038e1e 100644
--- a/embassy-stm32/src/chip/stm32f407ig.rs
+++ b/embassy-stm32/src/chip/stm32f407ig.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f407ve.rs b/embassy-stm32/src/chip/stm32f407ve.rs
index ac19c9844..f86038e1e 100644
--- a/embassy-stm32/src/chip/stm32f407ve.rs
+++ b/embassy-stm32/src/chip/stm32f407ve.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f407vg.rs b/embassy-stm32/src/chip/stm32f407vg.rs
index ac19c9844..f86038e1e 100644
--- a/embassy-stm32/src/chip/stm32f407vg.rs
+++ b/embassy-stm32/src/chip/stm32f407vg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f407ze.rs b/embassy-stm32/src/chip/stm32f407ze.rs
index ac19c9844..f86038e1e 100644
--- a/embassy-stm32/src/chip/stm32f407ze.rs
+++ b/embassy-stm32/src/chip/stm32f407ze.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f407zg.rs b/embassy-stm32/src/chip/stm32f407zg.rs
index ac19c9844..f86038e1e 100644
--- a/embassy-stm32/src/chip/stm32f407zg.rs
+++ b/embassy-stm32/src/chip/stm32f407zg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f410c8.rs b/embassy-stm32/src/chip/stm32f410c8.rs
index 8015e97a7..3b7a40d35 100644
--- a/embassy-stm32/src/chip/stm32f410c8.rs
+++ b/embassy-stm32/src/chip/stm32f410c8.rs
@@ -1,13 +1,15 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG, TIM1,
-    TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG,
+    TIM1, TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f410cb.rs b/embassy-stm32/src/chip/stm32f410cb.rs
index 8015e97a7..3b7a40d35 100644
--- a/embassy-stm32/src/chip/stm32f410cb.rs
+++ b/embassy-stm32/src/chip/stm32f410cb.rs
@@ -1,13 +1,15 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG, TIM1,
-    TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG,
+    TIM1, TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f410r8.rs b/embassy-stm32/src/chip/stm32f410r8.rs
index 8015e97a7..3b7a40d35 100644
--- a/embassy-stm32/src/chip/stm32f410r8.rs
+++ b/embassy-stm32/src/chip/stm32f410r8.rs
@@ -1,13 +1,15 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG, TIM1,
-    TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG,
+    TIM1, TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f410rb.rs b/embassy-stm32/src/chip/stm32f410rb.rs
index 8015e97a7..3b7a40d35 100644
--- a/embassy-stm32/src/chip/stm32f410rb.rs
+++ b/embassy-stm32/src/chip/stm32f410rb.rs
@@ -1,13 +1,15 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG, TIM1,
-    TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG,
+    TIM1, TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f410t8.rs b/embassy-stm32/src/chip/stm32f410t8.rs
index e34973843..e9035f1a3 100644
--- a/embassy-stm32/src/chip/stm32f410t8.rs
+++ b/embassy-stm32/src/chip/stm32f410t8.rs
@@ -1,13 +1,15 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SYSCFG, TIM1, TIM11, TIM5,
-    TIM6, TIM9, USART1, USART2, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SYSCFG, TIM1, TIM11,
+    TIM5, TIM6, TIM9, USART1, USART2, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f410tb.rs b/embassy-stm32/src/chip/stm32f410tb.rs
index e34973843..e9035f1a3 100644
--- a/embassy-stm32/src/chip/stm32f410tb.rs
+++ b/embassy-stm32/src/chip/stm32f410tb.rs
@@ -1,13 +1,15 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SYSCFG, TIM1, TIM11, TIM5,
-    TIM6, TIM9, USART1, USART2, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SYSCFG, TIM1, TIM11,
+    TIM5, TIM6, TIM9, USART1, USART2, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f411cc.rs b/embassy-stm32/src/chip/stm32f411cc.rs
index 5f0dbec63..1cad69bae 100644
--- a/embassy-stm32/src/chip/stm32f411cc.rs
+++ b/embassy-stm32/src/chip/stm32f411cc.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11,
-    TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10,
+    TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f411ce.rs b/embassy-stm32/src/chip/stm32f411ce.rs
index 5f0dbec63..1cad69bae 100644
--- a/embassy-stm32/src/chip/stm32f411ce.rs
+++ b/embassy-stm32/src/chip/stm32f411ce.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11,
-    TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10,
+    TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f411rc.rs b/embassy-stm32/src/chip/stm32f411rc.rs
index 5f0dbec63..1cad69bae 100644
--- a/embassy-stm32/src/chip/stm32f411rc.rs
+++ b/embassy-stm32/src/chip/stm32f411rc.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11,
-    TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10,
+    TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f411re.rs b/embassy-stm32/src/chip/stm32f411re.rs
index 5f0dbec63..1cad69bae 100644
--- a/embassy-stm32/src/chip/stm32f411re.rs
+++ b/embassy-stm32/src/chip/stm32f411re.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11,
-    TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10,
+    TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f411vc.rs b/embassy-stm32/src/chip/stm32f411vc.rs
index 5f0dbec63..1cad69bae 100644
--- a/embassy-stm32/src/chip/stm32f411vc.rs
+++ b/embassy-stm32/src/chip/stm32f411vc.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11,
-    TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10,
+    TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f411ve.rs b/embassy-stm32/src/chip/stm32f411ve.rs
index 5f0dbec63..1cad69bae 100644
--- a/embassy-stm32/src/chip/stm32f411ve.rs
+++ b/embassy-stm32/src/chip/stm32f411ve.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11,
-    PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12,
-    PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13,
-    PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14,
-    PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15,
-    PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, I2C1,
-    I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11,
-    TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,
+    PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11,
+    PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12,
+    PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13,
+    PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
+    PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
+    I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10,
+    TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f412ce.rs b/embassy-stm32/src/chip/stm32f412ce.rs
index f6749d135..5943ee391 100644
--- a/embassy-stm32/src/chip/stm32f412ce.rs
+++ b/embassy-stm32/src/chip/stm32f412ce.rs
@@ -1,14 +1,16 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
-    PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4,
-    SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
+    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
+    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10,
+    PH11, PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3,
+    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f412cg.rs b/embassy-stm32/src/chip/stm32f412cg.rs
index f6749d135..5943ee391 100644
--- a/embassy-stm32/src/chip/stm32f412cg.rs
+++ b/embassy-stm32/src/chip/stm32f412cg.rs
@@ -1,14 +1,16 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
-    PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4,
-    SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
+    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
+    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10,
+    PH11, PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3,
+    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f412re.rs b/embassy-stm32/src/chip/stm32f412re.rs
index 4fda48d4a..b668b84e8 100644
--- a/embassy-stm32/src/chip/stm32f412re.rs
+++ b/embassy-stm32/src/chip/stm32f412re.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4,
-    SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
+    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
+    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3,
+    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f412rg.rs b/embassy-stm32/src/chip/stm32f412rg.rs
index 4fda48d4a..b668b84e8 100644
--- a/embassy-stm32/src/chip/stm32f412rg.rs
+++ b/embassy-stm32/src/chip/stm32f412rg.rs
@@ -1,15 +1,17 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4,
-    SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
+    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
+    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3,
+    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f412ve.rs b/embassy-stm32/src/chip/stm32f412ve.rs
index 798ca7f41..2c3dda1c8 100644
--- a/embassy-stm32/src/chip/stm32f412ve.rs
+++ b/embassy-stm32/src/chip/stm32f412ve.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13,
-    PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14,
-    PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
-    I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9,
-    USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
+    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
+    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
+    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
+    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
+    PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f412vg.rs b/embassy-stm32/src/chip/stm32f412vg.rs
index 798ca7f41..2c3dda1c8 100644
--- a/embassy-stm32/src/chip/stm32f412vg.rs
+++ b/embassy-stm32/src/chip/stm32f412vg.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13,
-    PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14,
-    PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
-    I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9,
-    USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
+    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
+    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
+    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
+    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
+    PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f412ze.rs b/embassy-stm32/src/chip/stm32f412ze.rs
index 798ca7f41..2c3dda1c8 100644
--- a/embassy-stm32/src/chip/stm32f412ze.rs
+++ b/embassy-stm32/src/chip/stm32f412ze.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13,
-    PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14,
-    PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
-    I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9,
-    USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
+    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
+    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
+    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
+    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
+    PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f412zg.rs b/embassy-stm32/src/chip/stm32f412zg.rs
index 798ca7f41..2c3dda1c8 100644
--- a/embassy-stm32/src/chip/stm32f412zg.rs
+++ b/embassy-stm32/src/chip/stm32f412zg.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13,
-    PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14,
-    PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15,
-    I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9,
-    USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
+    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
+    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
+    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
+    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
+    PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f413cg.rs b/embassy-stm32/src/chip/stm32f413cg.rs
index 485fce7b9..f15f2ed3c 100644
--- a/embassy-stm32/src/chip/stm32f413cg.rs
+++ b/embassy-stm32/src/chip/stm32f413cg.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
-    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
-    TIM9, UART4, UART5, UART7, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
+    TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f413ch.rs b/embassy-stm32/src/chip/stm32f413ch.rs
index 485fce7b9..f15f2ed3c 100644
--- a/embassy-stm32/src/chip/stm32f413ch.rs
+++ b/embassy-stm32/src/chip/stm32f413ch.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
-    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
-    TIM9, UART4, UART5, UART7, USART1, USART2, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
+    TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f413mg.rs b/embassy-stm32/src/chip/stm32f413mg.rs
index d0a83492e..7ea6dd58f 100644
--- a/embassy-stm32/src/chip/stm32f413mg.rs
+++ b/embassy-stm32/src/chip/stm32f413mg.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
-    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2,
+    SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f413mh.rs b/embassy-stm32/src/chip/stm32f413mh.rs
index d0a83492e..7ea6dd58f 100644
--- a/embassy-stm32/src/chip/stm32f413mh.rs
+++ b/embassy-stm32/src/chip/stm32f413mh.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
-    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2,
+    SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f413rg.rs b/embassy-stm32/src/chip/stm32f413rg.rs
index d0a83492e..7ea6dd58f 100644
--- a/embassy-stm32/src/chip/stm32f413rg.rs
+++ b/embassy-stm32/src/chip/stm32f413rg.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
-    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2,
+    SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f413rh.rs b/embassy-stm32/src/chip/stm32f413rh.rs
index d0a83492e..7ea6dd58f 100644
--- a/embassy-stm32/src/chip/stm32f413rh.rs
+++ b/embassy-stm32/src/chip/stm32f413rh.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
-    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2,
+    SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f413vg.rs b/embassy-stm32/src/chip/stm32f413vg.rs
index e2d6a981b..1894feacb 100644
--- a/embassy-stm32/src/chip/stm32f413vg.rs
+++ b/embassy-stm32/src/chip/stm32f413vg.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
-    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3, USART6,
-    USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2,
+    SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3,
+    USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f413vh.rs b/embassy-stm32/src/chip/stm32f413vh.rs
index e2d6a981b..1894feacb 100644
--- a/embassy-stm32/src/chip/stm32f413vh.rs
+++ b/embassy-stm32/src/chip/stm32f413vh.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
-    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3, USART6,
-    USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2,
+    SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3,
+    USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f413zg.rs b/embassy-stm32/src/chip/stm32f413zg.rs
index e2d6a981b..1894feacb 100644
--- a/embassy-stm32/src/chip/stm32f413zg.rs
+++ b/embassy-stm32/src/chip/stm32f413zg.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
-    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3, USART6,
-    USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2,
+    SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3,
+    USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f413zh.rs b/embassy-stm32/src/chip/stm32f413zh.rs
index e2d6a981b..1894feacb 100644
--- a/embassy-stm32/src/chip/stm32f413zh.rs
+++ b/embassy-stm32/src/chip/stm32f413zh.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
-    SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3, USART6,
-    USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2,
+    SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3,
+    USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f415og.rs b/embassy-stm32/src/chip/stm32f415og.rs
index cd801d6cd..1c3243ed1 100644
--- a/embassy-stm32/src/chip/stm32f415og.rs
+++ b/embassy-stm32/src/chip/stm32f415og.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15,
-    HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, EXTI, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
+    PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f415rg.rs b/embassy-stm32/src/chip/stm32f415rg.rs
index cd801d6cd..1c3243ed1 100644
--- a/embassy-stm32/src/chip/stm32f415rg.rs
+++ b/embassy-stm32/src/chip/stm32f415rg.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15,
-    HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, EXTI, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
+    PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f415vg.rs b/embassy-stm32/src/chip/stm32f415vg.rs
index cd801d6cd..1c3243ed1 100644
--- a/embassy-stm32/src/chip/stm32f415vg.rs
+++ b/embassy-stm32/src/chip/stm32f415vg.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15,
-    HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, EXTI, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
+    PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f415zg.rs b/embassy-stm32/src/chip/stm32f415zg.rs
index cd801d6cd..1c3243ed1 100644
--- a/embassy-stm32/src/chip/stm32f415zg.rs
+++ b/embassy-stm32/src/chip/stm32f415zg.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, PA0, PA1, PA2, PA3, PA4, PA5,
-    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
-    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12,
-    PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13,
-    PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14,
-    PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15,
-    HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, EXTI, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
+    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
+    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
+    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
+    PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f417ie.rs b/embassy-stm32/src/chip/stm32f417ie.rs
index 034543078..f99ca7b1b 100644
--- a/embassy-stm32/src/chip/stm32f417ie.rs
+++ b/embassy-stm32/src/chip/stm32f417ie.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
-    TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
-    USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1,
+    TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
+    UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f417ig.rs b/embassy-stm32/src/chip/stm32f417ig.rs
index 034543078..f99ca7b1b 100644
--- a/embassy-stm32/src/chip/stm32f417ig.rs
+++ b/embassy-stm32/src/chip/stm32f417ig.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
-    TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
-    USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1,
+    TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
+    UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f417ve.rs b/embassy-stm32/src/chip/stm32f417ve.rs
index 034543078..f99ca7b1b 100644
--- a/embassy-stm32/src/chip/stm32f417ve.rs
+++ b/embassy-stm32/src/chip/stm32f417ve.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
-    TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
-    USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1,
+    TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
+    UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f417vg.rs b/embassy-stm32/src/chip/stm32f417vg.rs
index 034543078..f99ca7b1b 100644
--- a/embassy-stm32/src/chip/stm32f417vg.rs
+++ b/embassy-stm32/src/chip/stm32f417vg.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
-    TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
-    USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1,
+    TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
+    UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f417ze.rs b/embassy-stm32/src/chip/stm32f417ze.rs
index 034543078..f99ca7b1b 100644
--- a/embassy-stm32/src/chip/stm32f417ze.rs
+++ b/embassy-stm32/src/chip/stm32f417ze.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
-    TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
-    USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1,
+    TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
+    UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f417zg.rs b/embassy-stm32/src/chip/stm32f417zg.rs
index 034543078..f99ca7b1b 100644
--- a/embassy-stm32/src/chip/stm32f417zg.rs
+++ b/embassy-stm32/src/chip/stm32f417zg.rs
@@ -1,19 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10,
-    TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
-    USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1,
+    TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
+    UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f423ch.rs b/embassy-stm32/src/chip/stm32f423ch.rs
index ddb9ee0f5..54d5dbae6 100644
--- a/embassy-stm32/src/chip/stm32f423ch.rs
+++ b/embassy-stm32/src/chip/stm32f423ch.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -13,6 +13,8 @@ peripherals!(
     SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
     TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f423mh.rs b/embassy-stm32/src/chip/stm32f423mh.rs
index adedcbc23..a033c03ba 100644
--- a/embassy-stm32/src/chip/stm32f423mh.rs
+++ b/embassy-stm32/src/chip/stm32f423mh.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -13,6 +13,8 @@ peripherals!(
     SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
     TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f423rh.rs b/embassy-stm32/src/chip/stm32f423rh.rs
index adedcbc23..a033c03ba 100644
--- a/embassy-stm32/src/chip/stm32f423rh.rs
+++ b/embassy-stm32/src/chip/stm32f423rh.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -13,6 +13,8 @@ peripherals!(
     SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
     TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f423vh.rs b/embassy-stm32/src/chip/stm32f423vh.rs
index 6c531d7f2..6f0c5bd6e 100644
--- a/embassy-stm32/src/chip/stm32f423vh.rs
+++ b/embassy-stm32/src/chip/stm32f423vh.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3,
     USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f423zh.rs b/embassy-stm32/src/chip/stm32f423zh.rs
index 6c531d7f2..6f0c5bd6e 100644
--- a/embassy-stm32/src/chip/stm32f423zh.rs
+++ b/embassy-stm32/src/chip/stm32f423zh.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, FMPI2C1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,6 +14,8 @@ peripherals!(
     TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3,
     USART6, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f427ag.rs b/embassy-stm32/src/chip/stm32f427ag.rs
index 0251a0bca..9d2e19b80 100644
--- a/embassy-stm32/src/chip/stm32f427ag.rs
+++ b/embassy-stm32/src/chip/stm32f427ag.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f427ai.rs b/embassy-stm32/src/chip/stm32f427ai.rs
index 0251a0bca..9d2e19b80 100644
--- a/embassy-stm32/src/chip/stm32f427ai.rs
+++ b/embassy-stm32/src/chip/stm32f427ai.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f427ig.rs b/embassy-stm32/src/chip/stm32f427ig.rs
index 9111a78cc..2e18827e7 100644
--- a/embassy-stm32/src/chip/stm32f427ig.rs
+++ b/embassy-stm32/src/chip/stm32f427ig.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f427ii.rs b/embassy-stm32/src/chip/stm32f427ii.rs
index 9111a78cc..2e18827e7 100644
--- a/embassy-stm32/src/chip/stm32f427ii.rs
+++ b/embassy-stm32/src/chip/stm32f427ii.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f427vg.rs b/embassy-stm32/src/chip/stm32f427vg.rs
index fdebb3b98..67ee554a0 100644
--- a/embassy-stm32/src/chip/stm32f427vg.rs
+++ b/embassy-stm32/src/chip/stm32f427vg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f427vi.rs b/embassy-stm32/src/chip/stm32f427vi.rs
index fdebb3b98..67ee554a0 100644
--- a/embassy-stm32/src/chip/stm32f427vi.rs
+++ b/embassy-stm32/src/chip/stm32f427vi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5,
     UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f427zg.rs b/embassy-stm32/src/chip/stm32f427zg.rs
index 9111a78cc..2e18827e7 100644
--- a/embassy-stm32/src/chip/stm32f427zg.rs
+++ b/embassy-stm32/src/chip/stm32f427zg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f427zi.rs b/embassy-stm32/src/chip/stm32f427zi.rs
index 9111a78cc..2e18827e7 100644
--- a/embassy-stm32/src/chip/stm32f427zi.rs
+++ b/embassy-stm32/src/chip/stm32f427zi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429ag.rs b/embassy-stm32/src/chip/stm32f429ag.rs
index 408655851..8ae247ad1 100644
--- a/embassy-stm32/src/chip/stm32f429ag.rs
+++ b/embassy-stm32/src/chip/stm32f429ag.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429ai.rs b/embassy-stm32/src/chip/stm32f429ai.rs
index 408655851..8ae247ad1 100644
--- a/embassy-stm32/src/chip/stm32f429ai.rs
+++ b/embassy-stm32/src/chip/stm32f429ai.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429be.rs b/embassy-stm32/src/chip/stm32f429be.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429be.rs
+++ b/embassy-stm32/src/chip/stm32f429be.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429bg.rs b/embassy-stm32/src/chip/stm32f429bg.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429bg.rs
+++ b/embassy-stm32/src/chip/stm32f429bg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429bi.rs b/embassy-stm32/src/chip/stm32f429bi.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429bi.rs
+++ b/embassy-stm32/src/chip/stm32f429bi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429ie.rs b/embassy-stm32/src/chip/stm32f429ie.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429ie.rs
+++ b/embassy-stm32/src/chip/stm32f429ie.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429ig.rs b/embassy-stm32/src/chip/stm32f429ig.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429ig.rs
+++ b/embassy-stm32/src/chip/stm32f429ig.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429ii.rs b/embassy-stm32/src/chip/stm32f429ii.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429ii.rs
+++ b/embassy-stm32/src/chip/stm32f429ii.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429ne.rs b/embassy-stm32/src/chip/stm32f429ne.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429ne.rs
+++ b/embassy-stm32/src/chip/stm32f429ne.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429ng.rs b/embassy-stm32/src/chip/stm32f429ng.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429ng.rs
+++ b/embassy-stm32/src/chip/stm32f429ng.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429ni.rs b/embassy-stm32/src/chip/stm32f429ni.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429ni.rs
+++ b/embassy-stm32/src/chip/stm32f429ni.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429ve.rs b/embassy-stm32/src/chip/stm32f429ve.rs
index f9532b2d1..4b609740f 100644
--- a/embassy-stm32/src/chip/stm32f429ve.rs
+++ b/embassy-stm32/src/chip/stm32f429ve.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429vg.rs b/embassy-stm32/src/chip/stm32f429vg.rs
index f9532b2d1..4b609740f 100644
--- a/embassy-stm32/src/chip/stm32f429vg.rs
+++ b/embassy-stm32/src/chip/stm32f429vg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429vi.rs b/embassy-stm32/src/chip/stm32f429vi.rs
index f9532b2d1..4b609740f 100644
--- a/embassy-stm32/src/chip/stm32f429vi.rs
+++ b/embassy-stm32/src/chip/stm32f429vi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429ze.rs b/embassy-stm32/src/chip/stm32f429ze.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429ze.rs
+++ b/embassy-stm32/src/chip/stm32f429ze.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429zg.rs b/embassy-stm32/src/chip/stm32f429zg.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429zg.rs
+++ b/embassy-stm32/src/chip/stm32f429zg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f429zi.rs b/embassy-stm32/src/chip/stm32f429zi.rs
index 1a285e03a..a1c7ae71b 100644
--- a/embassy-stm32/src/chip/stm32f429zi.rs
+++ b/embassy-stm32/src/chip/stm32f429zi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f437ai.rs b/embassy-stm32/src/chip/stm32f437ai.rs
index 14d3863ed..8b1eb9e33 100644
--- a/embassy-stm32/src/chip/stm32f437ai.rs
+++ b/embassy-stm32/src/chip/stm32f437ai.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
-    UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f437ig.rs b/embassy-stm32/src/chip/stm32f437ig.rs
index e7eec4f5b..198585d78 100644
--- a/embassy-stm32/src/chip/stm32f437ig.rs
+++ b/embassy-stm32/src/chip/stm32f437ig.rs
@@ -1,21 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6,
-    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
-    TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
+    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
+    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f437ii.rs b/embassy-stm32/src/chip/stm32f437ii.rs
index e7eec4f5b..198585d78 100644
--- a/embassy-stm32/src/chip/stm32f437ii.rs
+++ b/embassy-stm32/src/chip/stm32f437ii.rs
@@ -1,21 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6,
-    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
-    TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
+    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
+    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f437vg.rs b/embassy-stm32/src/chip/stm32f437vg.rs
index a570e9608..b1d2e290f 100644
--- a/embassy-stm32/src/chip/stm32f437vg.rs
+++ b/embassy-stm32/src/chip/stm32f437vg.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1,
-    TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG,
+    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f437vi.rs b/embassy-stm32/src/chip/stm32f437vi.rs
index a570e9608..b1d2e290f 100644
--- a/embassy-stm32/src/chip/stm32f437vi.rs
+++ b/embassy-stm32/src/chip/stm32f437vi.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1,
-    TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG,
+    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
     UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f437zg.rs b/embassy-stm32/src/chip/stm32f437zg.rs
index e7eec4f5b..198585d78 100644
--- a/embassy-stm32/src/chip/stm32f437zg.rs
+++ b/embassy-stm32/src/chip/stm32f437zg.rs
@@ -1,21 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6,
-    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
-    TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
+    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
+    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f437zi.rs b/embassy-stm32/src/chip/stm32f437zi.rs
index e7eec4f5b..198585d78 100644
--- a/embassy-stm32/src/chip/stm32f437zi.rs
+++ b/embassy-stm32/src/chip/stm32f437zi.rs
@@ -1,21 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6,
-    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
-    TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
+    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
+    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f439ai.rs b/embassy-stm32/src/chip/stm32f439ai.rs
index 6475617fe..b0ff8fa35 100644
--- a/embassy-stm32/src/chip/stm32f439ai.rs
+++ b/embassy-stm32/src/chip/stm32f439ai.rs
@@ -1,21 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
-    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
-    TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
+    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f439bg.rs b/embassy-stm32/src/chip/stm32f439bg.rs
index 11fbc8adc..eec3a3f65 100644
--- a/embassy-stm32/src/chip/stm32f439bg.rs
+++ b/embassy-stm32/src/chip/stm32f439bg.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
-    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
-    WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f439bi.rs b/embassy-stm32/src/chip/stm32f439bi.rs
index 11fbc8adc..eec3a3f65 100644
--- a/embassy-stm32/src/chip/stm32f439bi.rs
+++ b/embassy-stm32/src/chip/stm32f439bi.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
-    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
-    WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f439ig.rs b/embassy-stm32/src/chip/stm32f439ig.rs
index 11fbc8adc..eec3a3f65 100644
--- a/embassy-stm32/src/chip/stm32f439ig.rs
+++ b/embassy-stm32/src/chip/stm32f439ig.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
-    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
-    WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f439ii.rs b/embassy-stm32/src/chip/stm32f439ii.rs
index 11fbc8adc..eec3a3f65 100644
--- a/embassy-stm32/src/chip/stm32f439ii.rs
+++ b/embassy-stm32/src/chip/stm32f439ii.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
-    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
-    WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f439ng.rs b/embassy-stm32/src/chip/stm32f439ng.rs
index 11fbc8adc..eec3a3f65 100644
--- a/embassy-stm32/src/chip/stm32f439ng.rs
+++ b/embassy-stm32/src/chip/stm32f439ng.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
-    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
-    WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f439ni.rs b/embassy-stm32/src/chip/stm32f439ni.rs
index 11fbc8adc..eec3a3f65 100644
--- a/embassy-stm32/src/chip/stm32f439ni.rs
+++ b/embassy-stm32/src/chip/stm32f439ni.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
-    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
-    WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f439vg.rs b/embassy-stm32/src/chip/stm32f439vg.rs
index b195f3ac6..8dfb7bdbc 100644
--- a/embassy-stm32/src/chip/stm32f439vg.rs
+++ b/embassy-stm32/src/chip/stm32f439vg.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
-    UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f439vi.rs b/embassy-stm32/src/chip/stm32f439vi.rs
index b195f3ac6..8dfb7bdbc 100644
--- a/embassy-stm32/src/chip/stm32f439vi.rs
+++ b/embassy-stm32/src/chip/stm32f439vi.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
-    UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f439zg.rs b/embassy-stm32/src/chip/stm32f439zg.rs
index 11fbc8adc..eec3a3f65 100644
--- a/embassy-stm32/src/chip/stm32f439zg.rs
+++ b/embassy-stm32/src/chip/stm32f439zg.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
-    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
-    WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f439zi.rs b/embassy-stm32/src/chip/stm32f439zi.rs
index 11fbc8adc..eec3a3f65 100644
--- a/embassy-stm32/src/chip/stm32f439zi.rs
+++ b/embassy-stm32/src/chip/stm32f439zi.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5,
-    SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
-    TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
-    WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
+    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f446mc.rs b/embassy-stm32/src/chip/stm32f446mc.rs
index acf4a3968..b4f048cab 100644
--- a/embassy-stm32/src/chip/stm32f446mc.rs
+++ b/embassy-stm32/src/chip/stm32f446mc.rs
@@ -1,18 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, FMPI2C1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, SPI2,
-    SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1,
+    SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f446me.rs b/embassy-stm32/src/chip/stm32f446me.rs
index acf4a3968..b4f048cab 100644
--- a/embassy-stm32/src/chip/stm32f446me.rs
+++ b/embassy-stm32/src/chip/stm32f446me.rs
@@ -1,18 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, FMPI2C1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, SPI2,
-    SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1,
+    SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f446rc.rs b/embassy-stm32/src/chip/stm32f446rc.rs
index 6392b7681..222dcfb80 100644
--- a/embassy-stm32/src/chip/stm32f446rc.rs
+++ b/embassy-stm32/src/chip/stm32f446rc.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, FMPI2C1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SDIO, SPDIFRX, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
-    TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SDIO, SPDIFRX, SPI1, SPI2,
+    SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
+    TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f446re.rs b/embassy-stm32/src/chip/stm32f446re.rs
index 6392b7681..222dcfb80 100644
--- a/embassy-stm32/src/chip/stm32f446re.rs
+++ b/embassy-stm32/src/chip/stm32f446re.rs
@@ -1,18 +1,20 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, FMPI2C1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SDIO, SPDIFRX, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
-    TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SDIO, SPDIFRX, SPI1, SPI2,
+    SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7,
+    TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f446vc.rs b/embassy-stm32/src/chip/stm32f446vc.rs
index acf4a3968..b4f048cab 100644
--- a/embassy-stm32/src/chip/stm32f446vc.rs
+++ b/embassy-stm32/src/chip/stm32f446vc.rs
@@ -1,18 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, FMPI2C1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, SPI2,
-    SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1,
+    SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f446ve.rs b/embassy-stm32/src/chip/stm32f446ve.rs
index acf4a3968..b4f048cab 100644
--- a/embassy-stm32/src/chip/stm32f446ve.rs
+++ b/embassy-stm32/src/chip/stm32f446ve.rs
@@ -1,18 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, FMPI2C1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, SPI2,
-    SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1,
+    SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f446zc.rs b/embassy-stm32/src/chip/stm32f446zc.rs
index acf4a3968..b4f048cab 100644
--- a/embassy-stm32/src/chip/stm32f446zc.rs
+++ b/embassy-stm32/src/chip/stm32f446zc.rs
@@ -1,18 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, FMPI2C1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, SPI2,
-    SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1,
+    SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f446ze.rs b/embassy-stm32/src/chip/stm32f446ze.rs
index acf4a3968..b4f048cab 100644
--- a/embassy-stm32/src/chip/stm32f446ze.rs
+++ b/embassy-stm32/src/chip/stm32f446ze.rs
@@ -1,18 +1,21 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, FMPI2C1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, SPI2,
-    SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1,
+    SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469ae.rs b/embassy-stm32/src/chip/stm32f469ae.rs
index a9503f67d..94e2689fc 100644
--- a/embassy-stm32/src/chip/stm32f469ae.rs
+++ b/embassy-stm32/src/chip/stm32f469ae.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15,
-    PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1,
-    I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI6,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
+    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
+    I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI6,
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469ag.rs b/embassy-stm32/src/chip/stm32f469ag.rs
index a9503f67d..94e2689fc 100644
--- a/embassy-stm32/src/chip/stm32f469ag.rs
+++ b/embassy-stm32/src/chip/stm32f469ag.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15,
-    PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1,
-    I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI6,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
+    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
+    I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI6,
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469ai.rs b/embassy-stm32/src/chip/stm32f469ai.rs
index a9503f67d..94e2689fc 100644
--- a/embassy-stm32/src/chip/stm32f469ai.rs
+++ b/embassy-stm32/src/chip/stm32f469ai.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15,
-    PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1,
-    I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI6,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
+    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
+    I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI6,
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469be.rs b/embassy-stm32/src/chip/stm32f469be.rs
index 53bd9fd98..ccfe25ded 100644
--- a/embassy-stm32/src/chip/stm32f469be.rs
+++ b/embassy-stm32/src/chip/stm32f469be.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -17,6 +17,8 @@ peripherals!(
     TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469bg.rs b/embassy-stm32/src/chip/stm32f469bg.rs
index 53bd9fd98..ccfe25ded 100644
--- a/embassy-stm32/src/chip/stm32f469bg.rs
+++ b/embassy-stm32/src/chip/stm32f469bg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -17,6 +17,8 @@ peripherals!(
     TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469bi.rs b/embassy-stm32/src/chip/stm32f469bi.rs
index 53bd9fd98..ccfe25ded 100644
--- a/embassy-stm32/src/chip/stm32f469bi.rs
+++ b/embassy-stm32/src/chip/stm32f469bi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -17,6 +17,8 @@ peripherals!(
     TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469ie.rs b/embassy-stm32/src/chip/stm32f469ie.rs
index 53bd9fd98..ccfe25ded 100644
--- a/embassy-stm32/src/chip/stm32f469ie.rs
+++ b/embassy-stm32/src/chip/stm32f469ie.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -17,6 +17,8 @@ peripherals!(
     TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469ig.rs b/embassy-stm32/src/chip/stm32f469ig.rs
index 53bd9fd98..ccfe25ded 100644
--- a/embassy-stm32/src/chip/stm32f469ig.rs
+++ b/embassy-stm32/src/chip/stm32f469ig.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -17,6 +17,8 @@ peripherals!(
     TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469ii.rs b/embassy-stm32/src/chip/stm32f469ii.rs
index 53bd9fd98..ccfe25ded 100644
--- a/embassy-stm32/src/chip/stm32f469ii.rs
+++ b/embassy-stm32/src/chip/stm32f469ii.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -17,6 +17,8 @@ peripherals!(
     TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469ne.rs b/embassy-stm32/src/chip/stm32f469ne.rs
index 53bd9fd98..ccfe25ded 100644
--- a/embassy-stm32/src/chip/stm32f469ne.rs
+++ b/embassy-stm32/src/chip/stm32f469ne.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -17,6 +17,8 @@ peripherals!(
     TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469ng.rs b/embassy-stm32/src/chip/stm32f469ng.rs
index 53bd9fd98..ccfe25ded 100644
--- a/embassy-stm32/src/chip/stm32f469ng.rs
+++ b/embassy-stm32/src/chip/stm32f469ng.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -17,6 +17,8 @@ peripherals!(
     TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469ni.rs b/embassy-stm32/src/chip/stm32f469ni.rs
index 53bd9fd98..ccfe25ded 100644
--- a/embassy-stm32/src/chip/stm32f469ni.rs
+++ b/embassy-stm32/src/chip/stm32f469ni.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -17,6 +17,8 @@ peripherals!(
     TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469ve.rs b/embassy-stm32/src/chip/stm32f469ve.rs
index 0d2dc9c93..ef61f2bde 100644
--- a/embassy-stm32/src/chip/stm32f469ve.rs
+++ b/embassy-stm32/src/chip/stm32f469ve.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15,
-    PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1,
-    I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
-    UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
+    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
+    I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469vg.rs b/embassy-stm32/src/chip/stm32f469vg.rs
index 0d2dc9c93..ef61f2bde 100644
--- a/embassy-stm32/src/chip/stm32f469vg.rs
+++ b/embassy-stm32/src/chip/stm32f469vg.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15,
-    PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1,
-    I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
-    UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
+    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
+    I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469vi.rs b/embassy-stm32/src/chip/stm32f469vi.rs
index 0d2dc9c93..ef61f2bde 100644
--- a/embassy-stm32/src/chip/stm32f469vi.rs
+++ b/embassy-stm32/src/chip/stm32f469vi.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15,
-    PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1,
-    I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
-    UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
+    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
+    I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469ze.rs b/embassy-stm32/src/chip/stm32f469ze.rs
index aaeefbeb9..569912a38 100644
--- a/embassy-stm32/src/chip/stm32f469ze.rs
+++ b/embassy-stm32/src/chip/stm32f469ze.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15,
-    PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1,
-    I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
-    UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
+    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
+    I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469zg.rs b/embassy-stm32/src/chip/stm32f469zg.rs
index aaeefbeb9..569912a38 100644
--- a/embassy-stm32/src/chip/stm32f469zg.rs
+++ b/embassy-stm32/src/chip/stm32f469zg.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15,
-    PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1,
-    I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
-    UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
+    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
+    I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f469zi.rs b/embassy-stm32/src/chip/stm32f469zi.rs
index aaeefbeb9..569912a38 100644
--- a/embassy-stm32/src/chip/stm32f469zi.rs
+++ b/embassy-stm32/src/chip/stm32f469zi.rs
@@ -1,21 +1,23 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15,
-    PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1,
-    I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG,
-    TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4,
-    UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
+    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
+    I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
+    SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
+    TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479ag.rs b/embassy-stm32/src/chip/stm32f479ag.rs
index 110026c82..6cea1e1df 100644
--- a/embassy-stm32/src/chip/stm32f479ag.rs
+++ b/embassy-stm32/src/chip/stm32f479ag.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -17,6 +17,8 @@ peripherals!(
     TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479ai.rs b/embassy-stm32/src/chip/stm32f479ai.rs
index 110026c82..6cea1e1df 100644
--- a/embassy-stm32/src/chip/stm32f479ai.rs
+++ b/embassy-stm32/src/chip/stm32f479ai.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -17,6 +17,8 @@ peripherals!(
     TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479bg.rs b/embassy-stm32/src/chip/stm32f479bg.rs
index d5133d313..40a58618b 100644
--- a/embassy-stm32/src/chip/stm32f479bg.rs
+++ b/embassy-stm32/src/chip/stm32f479bg.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
-    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
+    SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
     USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479bi.rs b/embassy-stm32/src/chip/stm32f479bi.rs
index d5133d313..40a58618b 100644
--- a/embassy-stm32/src/chip/stm32f479bi.rs
+++ b/embassy-stm32/src/chip/stm32f479bi.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
-    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
+    SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
     USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479ig.rs b/embassy-stm32/src/chip/stm32f479ig.rs
index d5133d313..40a58618b 100644
--- a/embassy-stm32/src/chip/stm32f479ig.rs
+++ b/embassy-stm32/src/chip/stm32f479ig.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
-    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
+    SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
     USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479ii.rs b/embassy-stm32/src/chip/stm32f479ii.rs
index d5133d313..40a58618b 100644
--- a/embassy-stm32/src/chip/stm32f479ii.rs
+++ b/embassy-stm32/src/chip/stm32f479ii.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
-    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
+    SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
     USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479ng.rs b/embassy-stm32/src/chip/stm32f479ng.rs
index d5133d313..40a58618b 100644
--- a/embassy-stm32/src/chip/stm32f479ng.rs
+++ b/embassy-stm32/src/chip/stm32f479ng.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
-    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
+    SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
     USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479ni.rs b/embassy-stm32/src/chip/stm32f479ni.rs
index d5133d313..40a58618b 100644
--- a/embassy-stm32/src/chip/stm32f479ni.rs
+++ b/embassy-stm32/src/chip/stm32f479ni.rs
@@ -1,22 +1,24 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14,
-    PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15,
-    HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4,
-    SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6,
-    TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3,
+    SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS,
     USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479vg.rs b/embassy-stm32/src/chip/stm32f479vg.rs
index d5f37360a..25c960a4a 100644
--- a/embassy-stm32/src/chip/stm32f479vg.rs
+++ b/embassy-stm32/src/chip/stm32f479vg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479vi.rs b/embassy-stm32/src/chip/stm32f479vi.rs
index d5f37360a..25c960a4a 100644
--- a/embassy-stm32/src/chip/stm32f479vi.rs
+++ b/embassy-stm32/src/chip/stm32f479vi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479zg.rs b/embassy-stm32/src/chip/stm32f479zg.rs
index 76134afa5..7e5ee3245 100644
--- a/embassy-stm32/src/chip/stm32f479zg.rs
+++ b/embassy-stm32/src/chip/stm32f479zg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32f479zi.rs b/embassy-stm32/src/chip/stm32f479zi.rs
index 76134afa5..7e5ee3245 100644
--- a/embassy-stm32/src/chip/stm32f479zi.rs
+++ b/embassy-stm32/src/chip/stm32f479zi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -16,6 +16,8 @@ peripherals!(
     SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8,
     TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40013800;
+pub const EXTI_BASE: usize = 0x40013c00;
 pub const GPIO_BASE: usize = 0x40020000;
 pub const GPIO_STRIDE: usize = 0x400;
 
diff --git a/embassy-stm32/src/chip/stm32l412c8.rs b/embassy-stm32/src/chip/stm32l412c8.rs
index c20a8a60a..e319e06a7 100644
--- a/embassy-stm32/src/chip/stm32l412c8.rs
+++ b/embassy-stm32/src/chip/stm32l412c8.rs
@@ -1,16 +1,340 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12,
-    PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
-    SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
+    PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
+    RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l412cb.rs b/embassy-stm32/src/chip/stm32l412cb.rs
index c20a8a60a..e319e06a7 100644
--- a/embassy-stm32/src/chip/stm32l412cb.rs
+++ b/embassy-stm32/src/chip/stm32l412cb.rs
@@ -1,16 +1,340 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12,
-    PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
-    SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
+    PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
+    RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l412k8.rs b/embassy-stm32/src/chip/stm32l412k8.rs
index c12d91a6a..88cc20b04 100644
--- a/embassy-stm32/src/chip/stm32l412k8.rs
+++ b/embassy-stm32/src/chip/stm32l412k8.rs
@@ -1,16 +1,339 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12,
-    PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SPI1,
-    SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
+    PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
+    SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l412kb.rs b/embassy-stm32/src/chip/stm32l412kb.rs
index c12d91a6a..88cc20b04 100644
--- a/embassy-stm32/src/chip/stm32l412kb.rs
+++ b/embassy-stm32/src/chip/stm32l412kb.rs
@@ -1,16 +1,339 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12,
-    PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SPI1,
-    SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
+    PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
+    SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l412r8.rs b/embassy-stm32/src/chip/stm32l412r8.rs
index c20a8a60a..e319e06a7 100644
--- a/embassy-stm32/src/chip/stm32l412r8.rs
+++ b/embassy-stm32/src/chip/stm32l412r8.rs
@@ -1,16 +1,340 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12,
-    PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
-    SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
+    PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
+    RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l412rb.rs b/embassy-stm32/src/chip/stm32l412rb.rs
index c20a8a60a..e319e06a7 100644
--- a/embassy-stm32/src/chip/stm32l412rb.rs
+++ b/embassy-stm32/src/chip/stm32l412rb.rs
@@ -1,16 +1,340 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12,
-    PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
-    SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
+    PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
+    RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l412t8.rs b/embassy-stm32/src/chip/stm32l412t8.rs
index c12d91a6a..88cc20b04 100644
--- a/embassy-stm32/src/chip/stm32l412t8.rs
+++ b/embassy-stm32/src/chip/stm32l412t8.rs
@@ -1,16 +1,339 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12,
-    PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SPI1,
-    SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
+    PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
+    SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l412tb.rs b/embassy-stm32/src/chip/stm32l412tb.rs
index c12d91a6a..88cc20b04 100644
--- a/embassy-stm32/src/chip/stm32l412tb.rs
+++ b/embassy-stm32/src/chip/stm32l412tb.rs
@@ -1,16 +1,339 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9,
-    PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10,
-    PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11,
-    PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12,
-    PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SPI1,
-    SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
+    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
+    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
+    PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
+    SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l422cb.rs b/embassy-stm32/src/chip/stm32l422cb.rs
index f3734f940..015b11be3 100644
--- a/embassy-stm32/src/chip/stm32l422cb.rs
+++ b/embassy-stm32/src/chip/stm32l422cb.rs
@@ -1,8 +1,8 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
+    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
     PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
     PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
     PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -10,8 +10,334 @@ peripherals!(
     RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        AES = 79,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(AES);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn AES();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l422kb.rs b/embassy-stm32/src/chip/stm32l422kb.rs
index 634db7aaf..26decd09b 100644
--- a/embassy-stm32/src/chip/stm32l422kb.rs
+++ b/embassy-stm32/src/chip/stm32l422kb.rs
@@ -1,16 +1,342 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
+    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
     PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
     PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
     PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
     PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
     SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        AES = 79,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(AES);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn AES();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l422rb.rs b/embassy-stm32/src/chip/stm32l422rb.rs
index f3734f940..015b11be3 100644
--- a/embassy-stm32/src/chip/stm32l422rb.rs
+++ b/embassy-stm32/src/chip/stm32l422rb.rs
@@ -1,8 +1,8 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
+    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
     PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
     PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
     PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -10,8 +10,334 @@ peripherals!(
     RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        AES = 79,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(AES);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn AES();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l422tb.rs b/embassy-stm32/src/chip/stm32l422tb.rs
index 634db7aaf..26decd09b 100644
--- a/embassy-stm32/src/chip/stm32l422tb.rs
+++ b/embassy-stm32/src/chip/stm32l422tb.rs
@@ -1,16 +1,342 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8,
-    PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
+    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
     PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
     PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
     PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
     PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
     SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        AES = 79,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6 = 54,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(AES);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn AES();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l431cb.rs b/embassy-stm32/src/chip/stm32l431cb.rs
index fb418c2ab..c4f33502f 100644
--- a/embassy-stm32/src/chip/stm32l431cb.rs
+++ b/embassy-stm32/src/chip/stm32l431cb.rs
@@ -1,18 +1,365 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
-    SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
+    RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1,
     USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l431cc.rs b/embassy-stm32/src/chip/stm32l431cc.rs
index fb418c2ab..c4f33502f 100644
--- a/embassy-stm32/src/chip/stm32l431cc.rs
+++ b/embassy-stm32/src/chip/stm32l431cc.rs
@@ -1,18 +1,365 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
-    SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
+    RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1,
     USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l431kb.rs b/embassy-stm32/src/chip/stm32l431kb.rs
index 3959d4989..a55b3860f 100644
--- a/embassy-stm32/src/chip/stm32l431kb.rs
+++ b/embassy-stm32/src/chip/stm32l431kb.rs
@@ -1,17 +1,365 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SAI1,
-    SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, USART2, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
+    SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, USART2,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l431kc.rs b/embassy-stm32/src/chip/stm32l431kc.rs
index 3959d4989..a55b3860f 100644
--- a/embassy-stm32/src/chip/stm32l431kc.rs
+++ b/embassy-stm32/src/chip/stm32l431kc.rs
@@ -1,17 +1,365 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SAI1,
-    SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, USART2, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
+    SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, USART2,
+    WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l431rb.rs b/embassy-stm32/src/chip/stm32l431rb.rs
index 9c26d500d..902c4eb19 100644
--- a/embassy-stm32/src/chip/stm32l431rb.rs
+++ b/embassy-stm32/src/chip/stm32l431rb.rs
@@ -1,18 +1,365 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
-    SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
+    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
     USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l431rc.rs b/embassy-stm32/src/chip/stm32l431rc.rs
index 9c26d500d..902c4eb19 100644
--- a/embassy-stm32/src/chip/stm32l431rc.rs
+++ b/embassy-stm32/src/chip/stm32l431rc.rs
@@ -1,18 +1,365 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
-    SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
+    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
     USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l431vc.rs b/embassy-stm32/src/chip/stm32l431vc.rs
index 9c26d500d..902c4eb19 100644
--- a/embassy-stm32/src/chip/stm32l431vc.rs
+++ b/embassy-stm32/src/chip/stm32l431vc.rs
@@ -1,18 +1,365 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC,
-    SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
+    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
     USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l432kb.rs b/embassy-stm32/src/chip/stm32l432kb.rs
index 36b8571c1..915bbbd6a 100644
--- a/embassy-stm32/src/chip/stm32l432kb.rs
+++ b/embassy-stm32/src/chip/stm32l432kb.rs
@@ -1,16 +1,351 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
-    PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10,
+    PH11, PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1,
     USART2, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SPI1 = 35,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SPI1);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SPI1();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l432kc.rs b/embassy-stm32/src/chip/stm32l432kc.rs
index 36b8571c1..915bbbd6a 100644
--- a/embassy-stm32/src/chip/stm32l432kc.rs
+++ b/embassy-stm32/src/chip/stm32l432kc.rs
@@ -1,16 +1,351 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
-    PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10,
+    PH11, PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1,
     USART2, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SPI1 = 35,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SPI1);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SPI1();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l433cb.rs b/embassy-stm32/src/chip/stm32l433cb.rs
index 80e01da59..95313ffb0 100644
--- a/embassy-stm32/src/chip/stm32l433cb.rs
+++ b/embassy-stm32/src/chip/stm32l433cb.rs
@@ -1,18 +1,371 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1,
-    USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
+    USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l433cc.rs b/embassy-stm32/src/chip/stm32l433cc.rs
index 80e01da59..95313ffb0 100644
--- a/embassy-stm32/src/chip/stm32l433cc.rs
+++ b/embassy-stm32/src/chip/stm32l433cc.rs
@@ -1,18 +1,371 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1,
-    USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
+    USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l433rb.rs b/embassy-stm32/src/chip/stm32l433rb.rs
index a61a3c53e..38d4b8310 100644
--- a/embassy-stm32/src/chip/stm32l433rb.rs
+++ b/embassy-stm32/src/chip/stm32l433rb.rs
@@ -1,18 +1,371 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
-    USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7,
+    TSC, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l433rc.rs b/embassy-stm32/src/chip/stm32l433rc.rs
index a61a3c53e..38d4b8310 100644
--- a/embassy-stm32/src/chip/stm32l433rc.rs
+++ b/embassy-stm32/src/chip/stm32l433rc.rs
@@ -1,18 +1,371 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
-    USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7,
+    TSC, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l433vc.rs b/embassy-stm32/src/chip/stm32l433vc.rs
index a61a3c53e..38d4b8310 100644
--- a/embassy-stm32/src/chip/stm32l433vc.rs
+++ b/embassy-stm32/src/chip/stm32l433vc.rs
@@ -1,18 +1,371 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
-    USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7,
+    TSC, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l442kc.rs b/embassy-stm32/src/chip/stm32l442kc.rs
index 331d152f3..4837adef1 100644
--- a/embassy-stm32/src/chip/stm32l442kc.rs
+++ b/embassy-stm32/src/chip/stm32l442kc.rs
@@ -1,16 +1,354 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10,
-    PH11, PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
-    RNG, RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1,
-    USART2, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI,
+    RCC, RNG, RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
+    USART1, USART2, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SPI1 = 35,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SPI1);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SPI1();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l443cc.rs b/embassy-stm32/src/chip/stm32l443cc.rs
index 10d538aef..aa21e3322 100644
--- a/embassy-stm32/src/chip/stm32l443cc.rs
+++ b/embassy-stm32/src/chip/stm32l443cc.rs
@@ -1,18 +1,374 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
-    RNG, RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC,
-    USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI,
+    RCC, RNG, RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7,
+    TSC, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l443rc.rs b/embassy-stm32/src/chip/stm32l443rc.rs
index 4842bf0f6..f3139bc11 100644
--- a/embassy-stm32/src/chip/stm32l443rc.rs
+++ b/embassy-stm32/src/chip/stm32l443rc.rs
@@ -1,18 +1,374 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
-    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7,
-    TSC, USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI,
+    RCC, RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6,
+    TIM7, TSC, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l443vc.rs b/embassy-stm32/src/chip/stm32l443vc.rs
index 4842bf0f6..f3139bc11 100644
--- a/embassy-stm32/src/chip/stm32l443vc.rs
+++ b/embassy-stm32/src/chip/stm32l443vc.rs
@@ -1,18 +1,374 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
-    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7,
-    TSC, USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI,
+    RCC, RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6,
+    TIM7, TSC, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TSC = 77,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TSC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TSC();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 83] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l451cc.rs b/embassy-stm32/src/chip/stm32l451cc.rs
index 59132f492..6d8463347 100644
--- a/embassy-stm32/src/chip/stm32l451cc.rs
+++ b/embassy-stm32/src/chip/stm32l451cc.rs
@@ -1,18 +1,383 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, USART1,
-    USART2, USART3, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
+    USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l451ce.rs b/embassy-stm32/src/chip/stm32l451ce.rs
index 59132f492..6d8463347 100644
--- a/embassy-stm32/src/chip/stm32l451ce.rs
+++ b/embassy-stm32/src/chip/stm32l451ce.rs
@@ -1,18 +1,383 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, USART1,
-    USART2, USART3, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
+    USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l451rc.rs b/embassy-stm32/src/chip/stm32l451rc.rs
index af1f601c7..464fdc4ac 100644
--- a/embassy-stm32/src/chip/stm32l451rc.rs
+++ b/embassy-stm32/src/chip/stm32l451rc.rs
@@ -1,18 +1,383 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
-    USART1, USART2, USART3, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC,
+    UART4, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l451re.rs b/embassy-stm32/src/chip/stm32l451re.rs
index af1f601c7..464fdc4ac 100644
--- a/embassy-stm32/src/chip/stm32l451re.rs
+++ b/embassy-stm32/src/chip/stm32l451re.rs
@@ -1,18 +1,383 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
-    USART1, USART2, USART3, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC,
+    UART4, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l451vc.rs b/embassy-stm32/src/chip/stm32l451vc.rs
index af1f601c7..464fdc4ac 100644
--- a/embassy-stm32/src/chip/stm32l451vc.rs
+++ b/embassy-stm32/src/chip/stm32l451vc.rs
@@ -1,18 +1,383 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
-    USART1, USART2, USART3, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC,
+    UART4, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l451ve.rs b/embassy-stm32/src/chip/stm32l451ve.rs
index af1f601c7..464fdc4ac 100644
--- a/embassy-stm32/src/chip/stm32l451ve.rs
+++ b/embassy-stm32/src/chip/stm32l451ve.rs
@@ -1,18 +1,383 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
-    USART1, USART2, USART3, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC,
+    UART4, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l452cc.rs b/embassy-stm32/src/chip/stm32l452cc.rs
index 9c348ae47..ef4a256e5 100644
--- a/embassy-stm32/src/chip/stm32l452cc.rs
+++ b/embassy-stm32/src/chip/stm32l452cc.rs
@@ -1,18 +1,386 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, USART1,
-    USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
+    USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l452ce.rs b/embassy-stm32/src/chip/stm32l452ce.rs
index 9c348ae47..ef4a256e5 100644
--- a/embassy-stm32/src/chip/stm32l452ce.rs
+++ b/embassy-stm32/src/chip/stm32l452ce.rs
@@ -1,18 +1,386 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, USART1,
-    USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
+    USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l452rc.rs b/embassy-stm32/src/chip/stm32l452rc.rs
index 5b23cead2..05eaeda97 100644
--- a/embassy-stm32/src/chip/stm32l452rc.rs
+++ b/embassy-stm32/src/chip/stm32l452rc.rs
@@ -1,18 +1,386 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
-    USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC,
+    UART4, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l452re.rs b/embassy-stm32/src/chip/stm32l452re.rs
index 5b23cead2..05eaeda97 100644
--- a/embassy-stm32/src/chip/stm32l452re.rs
+++ b/embassy-stm32/src/chip/stm32l452re.rs
@@ -1,18 +1,386 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
-    USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC,
+    UART4, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l452vc.rs b/embassy-stm32/src/chip/stm32l452vc.rs
index 5b23cead2..05eaeda97 100644
--- a/embassy-stm32/src/chip/stm32l452vc.rs
+++ b/embassy-stm32/src/chip/stm32l452vc.rs
@@ -1,18 +1,386 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
-    USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC,
+    UART4, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l452ve.rs b/embassy-stm32/src/chip/stm32l452ve.rs
index 5b23cead2..05eaeda97 100644
--- a/embassy-stm32/src/chip/stm32l452ve.rs
+++ b/embassy-stm32/src/chip/stm32l452ve.rs
@@ -1,18 +1,386 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
-    PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9,
-    PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10,
-    PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11,
-    PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12,
-    PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG,
-    RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
-    USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5,
+    PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
+    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
+    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
+    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
+    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC,
+    UART4, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l462ce.rs b/embassy-stm32/src/chip/stm32l462ce.rs
index 2b8be5423..65b8842cd 100644
--- a/embassy-stm32/src/chip/stm32l462ce.rs
+++ b/embassy-stm32/src/chip/stm32l462ce.rs
@@ -1,18 +1,389 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
-    RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4,
-    USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI,
+    RCC, RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC,
+    UART4, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l462re.rs b/embassy-stm32/src/chip/stm32l462re.rs
index 40dbb9a04..4a4055b50 100644
--- a/embassy-stm32/src/chip/stm32l462re.rs
+++ b/embassy-stm32/src/chip/stm32l462re.rs
@@ -1,18 +1,389 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
-    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC,
-    UART4, USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI,
+    RCC, RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6,
+    TSC, UART4, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l462ve.rs b/embassy-stm32/src/chip/stm32l462ve.rs
index 40dbb9a04..4a4055b50 100644
--- a/embassy-stm32/src/chip/stm32l462ve.rs
+++ b/embassy-stm32/src/chip/stm32l462ve.rs
@@ -1,18 +1,389 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6,
-    PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8,
-    PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9,
-    PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10,
-    PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,
-    PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC,
-    RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC,
-    UART4, USART1, USART2, USART3, USB, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4,
+    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
+    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
+    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
+    PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI,
+    RCC, RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6,
+    TSC, UART4, USART1, USART2, USART3, USB, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM6_DAC = 54,
+        TSC = 77,
+        UART4 = 52,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USB = 67,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM6_DAC);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USB);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM6_DAC();
+        fn TSC();
+        fn UART4();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USB();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDMMC1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: USB },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l471qe.rs b/embassy-stm32/src/chip/stm32l471qe.rs
index 937127de9..192060c1f 100644
--- a/embassy-stm32/src/chip/stm32l471qe.rs
+++ b/embassy-stm32/src/chip/stm32l471qe.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -13,8 +13,409 @@ peripherals!(
     RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2,
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l471qg.rs b/embassy-stm32/src/chip/stm32l471qg.rs
index 937127de9..192060c1f 100644
--- a/embassy-stm32/src/chip/stm32l471qg.rs
+++ b/embassy-stm32/src/chip/stm32l471qg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -13,8 +13,409 @@ peripherals!(
     RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2,
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l471re.rs b/embassy-stm32/src/chip/stm32l471re.rs
index 937127de9..192060c1f 100644
--- a/embassy-stm32/src/chip/stm32l471re.rs
+++ b/embassy-stm32/src/chip/stm32l471re.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -13,8 +13,409 @@ peripherals!(
     RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2,
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l471rg.rs b/embassy-stm32/src/chip/stm32l471rg.rs
index 937127de9..192060c1f 100644
--- a/embassy-stm32/src/chip/stm32l471rg.rs
+++ b/embassy-stm32/src/chip/stm32l471rg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -13,8 +13,409 @@ peripherals!(
     RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2,
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l471ve.rs b/embassy-stm32/src/chip/stm32l471ve.rs
index 937127de9..192060c1f 100644
--- a/embassy-stm32/src/chip/stm32l471ve.rs
+++ b/embassy-stm32/src/chip/stm32l471ve.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -13,8 +13,409 @@ peripherals!(
     RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2,
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l471vg.rs b/embassy-stm32/src/chip/stm32l471vg.rs
index 937127de9..192060c1f 100644
--- a/embassy-stm32/src/chip/stm32l471vg.rs
+++ b/embassy-stm32/src/chip/stm32l471vg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -13,8 +13,409 @@ peripherals!(
     RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2,
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l471ze.rs b/embassy-stm32/src/chip/stm32l471ze.rs
index 937127de9..192060c1f 100644
--- a/embassy-stm32/src/chip/stm32l471ze.rs
+++ b/embassy-stm32/src/chip/stm32l471ze.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -13,8 +13,409 @@ peripherals!(
     RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2,
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l471zg.rs b/embassy-stm32/src/chip/stm32l471zg.rs
index 937127de9..192060c1f 100644
--- a/embassy-stm32/src/chip/stm32l471zg.rs
+++ b/embassy-stm32/src/chip/stm32l471zg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -13,8 +13,409 @@ peripherals!(
     RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2,
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l475rc.rs b/embassy-stm32/src/chip/stm32l475rc.rs
index 774df143c..7a818be15 100644
--- a/embassy-stm32/src/chip/stm32l475rc.rs
+++ b/embassy-stm32/src/chip/stm32l475rc.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,412 @@ peripherals!(
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l475re.rs b/embassy-stm32/src/chip/stm32l475re.rs
index 774df143c..7a818be15 100644
--- a/embassy-stm32/src/chip/stm32l475re.rs
+++ b/embassy-stm32/src/chip/stm32l475re.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,412 @@ peripherals!(
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l475rg.rs b/embassy-stm32/src/chip/stm32l475rg.rs
index 774df143c..7a818be15 100644
--- a/embassy-stm32/src/chip/stm32l475rg.rs
+++ b/embassy-stm32/src/chip/stm32l475rg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,412 @@ peripherals!(
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l475vc.rs b/embassy-stm32/src/chip/stm32l475vc.rs
index 774df143c..7a818be15 100644
--- a/embassy-stm32/src/chip/stm32l475vc.rs
+++ b/embassy-stm32/src/chip/stm32l475vc.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,412 @@ peripherals!(
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l475ve.rs b/embassy-stm32/src/chip/stm32l475ve.rs
index 774df143c..7a818be15 100644
--- a/embassy-stm32/src/chip/stm32l475ve.rs
+++ b/embassy-stm32/src/chip/stm32l475ve.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,412 @@ peripherals!(
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l475vg.rs b/embassy-stm32/src/chip/stm32l475vg.rs
index 774df143c..7a818be15 100644
--- a/embassy-stm32/src/chip/stm32l475vg.rs
+++ b/embassy-stm32/src/chip/stm32l475vg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,412 @@ peripherals!(
     TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS,
     WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476je.rs b/embassy-stm32/src/chip/stm32l476je.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476je.rs
+++ b/embassy-stm32/src/chip/stm32l476je.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476jg.rs b/embassy-stm32/src/chip/stm32l476jg.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476jg.rs
+++ b/embassy-stm32/src/chip/stm32l476jg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476me.rs b/embassy-stm32/src/chip/stm32l476me.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476me.rs
+++ b/embassy-stm32/src/chip/stm32l476me.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476mg.rs b/embassy-stm32/src/chip/stm32l476mg.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476mg.rs
+++ b/embassy-stm32/src/chip/stm32l476mg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476qe.rs b/embassy-stm32/src/chip/stm32l476qe.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476qe.rs
+++ b/embassy-stm32/src/chip/stm32l476qe.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476qg.rs b/embassy-stm32/src/chip/stm32l476qg.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476qg.rs
+++ b/embassy-stm32/src/chip/stm32l476qg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476rc.rs b/embassy-stm32/src/chip/stm32l476rc.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476rc.rs
+++ b/embassy-stm32/src/chip/stm32l476rc.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476re.rs b/embassy-stm32/src/chip/stm32l476re.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476re.rs
+++ b/embassy-stm32/src/chip/stm32l476re.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476rg.rs b/embassy-stm32/src/chip/stm32l476rg.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476rg.rs
+++ b/embassy-stm32/src/chip/stm32l476rg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476vc.rs b/embassy-stm32/src/chip/stm32l476vc.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476vc.rs
+++ b/embassy-stm32/src/chip/stm32l476vc.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476ve.rs b/embassy-stm32/src/chip/stm32l476ve.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476ve.rs
+++ b/embassy-stm32/src/chip/stm32l476ve.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476vg.rs b/embassy-stm32/src/chip/stm32l476vg.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476vg.rs
+++ b/embassy-stm32/src/chip/stm32l476vg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476ze.rs b/embassy-stm32/src/chip/stm32l476ze.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476ze.rs
+++ b/embassy-stm32/src/chip/stm32l476ze.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l476zg.rs b/embassy-stm32/src/chip/stm32l476zg.rs
index ce07466a5..d5b271290 100644
--- a/embassy-stm32/src/chip/stm32l476zg.rs
+++ b/embassy-stm32/src/chip/stm32l476zg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -14,8 +14,415 @@ peripherals!(
     TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
     USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l485jc.rs b/embassy-stm32/src/chip/stm32l485jc.rs
index 77b2e512c..829a5b5a8 100644
--- a/embassy-stm32/src/chip/stm32l485jc.rs
+++ b/embassy-stm32/src/chip/stm32l485jc.rs
@@ -1,21 +1,428 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG,
-    RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2,
-    TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS,
-    WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI,
+    RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17,
+    TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
+    USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l485je.rs b/embassy-stm32/src/chip/stm32l485je.rs
index 77b2e512c..829a5b5a8 100644
--- a/embassy-stm32/src/chip/stm32l485je.rs
+++ b/embassy-stm32/src/chip/stm32l485je.rs
@@ -1,21 +1,428 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG,
-    RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2,
-    TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS,
-    WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI,
+    RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17,
+    TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
+    USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l486jg.rs b/embassy-stm32/src/chip/stm32l486jg.rs
index e6b55967e..27ce58704 100644
--- a/embassy-stm32/src/chip/stm32l486jg.rs
+++ b/embassy-stm32/src/chip/stm32l486jg.rs
@@ -1,21 +1,431 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC,
-    RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17,
-    TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
-    USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2,
+    QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15,
+    TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
+    USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l486qg.rs b/embassy-stm32/src/chip/stm32l486qg.rs
index e6b55967e..27ce58704 100644
--- a/embassy-stm32/src/chip/stm32l486qg.rs
+++ b/embassy-stm32/src/chip/stm32l486qg.rs
@@ -1,21 +1,431 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC,
-    RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17,
-    TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
-    USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2,
+    QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15,
+    TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
+    USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l486rg.rs b/embassy-stm32/src/chip/stm32l486rg.rs
index e6b55967e..27ce58704 100644
--- a/embassy-stm32/src/chip/stm32l486rg.rs
+++ b/embassy-stm32/src/chip/stm32l486rg.rs
@@ -1,21 +1,431 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC,
-    RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17,
-    TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
-    USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2,
+    QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15,
+    TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
+    USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l486vg.rs b/embassy-stm32/src/chip/stm32l486vg.rs
index e6b55967e..27ce58704 100644
--- a/embassy-stm32/src/chip/stm32l486vg.rs
+++ b/embassy-stm32/src/chip/stm32l486vg.rs
@@ -1,21 +1,431 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC,
-    RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17,
-    TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
-    USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2,
+    QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15,
+    TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
+    USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l486zg.rs b/embassy-stm32/src/chip/stm32l486zg.rs
index e6b55967e..27ce58704 100644
--- a/embassy-stm32/src/chip/stm32l486zg.rs
+++ b/embassy-stm32/src/chip/stm32l486zg.rs
@@ -1,21 +1,431 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC,
-    RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17,
-    TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3,
-    USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2,
+    QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15,
+    TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
+    USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l496ae.rs b/embassy-stm32/src/chip/stm32l496ae.rs
index 5200ecd80..e54e0774d 100644
--- a/embassy-stm32/src/chip/stm32l496ae.rs
+++ b/embassy-stm32/src/chip/stm32l496ae.rs
@@ -1,12 +1,12 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0,
-    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
-    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
-    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
-    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
-    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
     PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l496ag.rs b/embassy-stm32/src/chip/stm32l496ag.rs
index 5200ecd80..e54e0774d 100644
--- a/embassy-stm32/src/chip/stm32l496ag.rs
+++ b/embassy-stm32/src/chip/stm32l496ag.rs
@@ -1,12 +1,12 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0,
-    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
-    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
-    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
-    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
-    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
     PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l496qe.rs b/embassy-stm32/src/chip/stm32l496qe.rs
index 5200ecd80..e54e0774d 100644
--- a/embassy-stm32/src/chip/stm32l496qe.rs
+++ b/embassy-stm32/src/chip/stm32l496qe.rs
@@ -1,12 +1,12 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0,
-    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
-    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
-    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
-    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
-    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
     PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l496qg.rs b/embassy-stm32/src/chip/stm32l496qg.rs
index 5200ecd80..e54e0774d 100644
--- a/embassy-stm32/src/chip/stm32l496qg.rs
+++ b/embassy-stm32/src/chip/stm32l496qg.rs
@@ -1,12 +1,12 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0,
-    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
-    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
-    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
-    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
-    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
     PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l496re.rs b/embassy-stm32/src/chip/stm32l496re.rs
index 5200ecd80..e54e0774d 100644
--- a/embassy-stm32/src/chip/stm32l496re.rs
+++ b/embassy-stm32/src/chip/stm32l496re.rs
@@ -1,12 +1,12 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0,
-    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
-    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
-    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
-    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
-    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
     PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l496rg.rs b/embassy-stm32/src/chip/stm32l496rg.rs
index 5200ecd80..e54e0774d 100644
--- a/embassy-stm32/src/chip/stm32l496rg.rs
+++ b/embassy-stm32/src/chip/stm32l496rg.rs
@@ -1,12 +1,12 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0,
-    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
-    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
-    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
-    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
-    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
     PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l496ve.rs b/embassy-stm32/src/chip/stm32l496ve.rs
index 5200ecd80..e54e0774d 100644
--- a/embassy-stm32/src/chip/stm32l496ve.rs
+++ b/embassy-stm32/src/chip/stm32l496ve.rs
@@ -1,12 +1,12 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0,
-    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
-    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
-    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
-    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
-    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
     PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l496vg.rs b/embassy-stm32/src/chip/stm32l496vg.rs
index 5200ecd80..e54e0774d 100644
--- a/embassy-stm32/src/chip/stm32l496vg.rs
+++ b/embassy-stm32/src/chip/stm32l496vg.rs
@@ -1,12 +1,12 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0,
-    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
-    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
-    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
-    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
-    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
     PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l496wg.rs b/embassy-stm32/src/chip/stm32l496wg.rs
index 5200ecd80..e54e0774d 100644
--- a/embassy-stm32/src/chip/stm32l496wg.rs
+++ b/embassy-stm32/src/chip/stm32l496wg.rs
@@ -1,12 +1,12 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0,
-    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
-    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
-    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
-    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
-    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
     PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l496ze.rs b/embassy-stm32/src/chip/stm32l496ze.rs
index 5200ecd80..e54e0774d 100644
--- a/embassy-stm32/src/chip/stm32l496ze.rs
+++ b/embassy-stm32/src/chip/stm32l496ze.rs
@@ -1,12 +1,12 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0,
-    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
-    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
-    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
-    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
-    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
     PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l496zg.rs b/embassy-stm32/src/chip/stm32l496zg.rs
index 5200ecd80..e54e0774d 100644
--- a/embassy-stm32/src/chip/stm32l496zg.rs
+++ b/embassy-stm32/src/chip/stm32l496zg.rs
@@ -1,12 +1,12 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0,
-    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
-    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
-    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
-    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
-    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
     PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
     PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
     PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4a6ag.rs b/embassy-stm32/src/chip/stm32l4a6ag.rs
index d758caee1..a3e227f1f 100644
--- a/embassy-stm32/src/chip/stm32l4a6ag.rs
+++ b/embassy-stm32/src/chip/stm32l4a6ag.rs
@@ -2,21 +2,467 @@ use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
     EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D,
-    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
-    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
-    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
-    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
-    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
-    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
-    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
-    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
-    PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1,
-    OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1,
-    TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
+    EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15,
+    PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1,
+    PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3,
+    PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5,
+    PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
+    PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9,
+    PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10,
+    PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11,
+    PI12, PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1,
+    OPAMP1, OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG,
+    TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4a6qg.rs b/embassy-stm32/src/chip/stm32l4a6qg.rs
index d758caee1..a3e227f1f 100644
--- a/embassy-stm32/src/chip/stm32l4a6qg.rs
+++ b/embassy-stm32/src/chip/stm32l4a6qg.rs
@@ -2,21 +2,467 @@ use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
     EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D,
-    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
-    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
-    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
-    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
-    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
-    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
-    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
-    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
-    PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1,
-    OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1,
-    TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
+    EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15,
+    PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1,
+    PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3,
+    PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5,
+    PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
+    PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9,
+    PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10,
+    PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11,
+    PI12, PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1,
+    OPAMP1, OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG,
+    TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4a6rg.rs b/embassy-stm32/src/chip/stm32l4a6rg.rs
index d758caee1..a3e227f1f 100644
--- a/embassy-stm32/src/chip/stm32l4a6rg.rs
+++ b/embassy-stm32/src/chip/stm32l4a6rg.rs
@@ -2,21 +2,467 @@ use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
     EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D,
-    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
-    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
-    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
-    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
-    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
-    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
-    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
-    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
-    PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1,
-    OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1,
-    TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
+    EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15,
+    PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1,
+    PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3,
+    PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5,
+    PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
+    PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9,
+    PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10,
+    PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11,
+    PI12, PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1,
+    OPAMP1, OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG,
+    TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4a6vg.rs b/embassy-stm32/src/chip/stm32l4a6vg.rs
index d758caee1..a3e227f1f 100644
--- a/embassy-stm32/src/chip/stm32l4a6vg.rs
+++ b/embassy-stm32/src/chip/stm32l4a6vg.rs
@@ -2,21 +2,467 @@ use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
     EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D,
-    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
-    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
-    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
-    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
-    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
-    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
-    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
-    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
-    PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1,
-    OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1,
-    TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
+    EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15,
+    PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1,
+    PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3,
+    PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5,
+    PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
+    PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9,
+    PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10,
+    PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11,
+    PI12, PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1,
+    OPAMP1, OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG,
+    TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4a6zg.rs b/embassy-stm32/src/chip/stm32l4a6zg.rs
index d758caee1..a3e227f1f 100644
--- a/embassy-stm32/src/chip/stm32l4a6zg.rs
+++ b/embassy-stm32/src/chip/stm32l4a6zg.rs
@@ -2,21 +2,467 @@ use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
     EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D,
-    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
-    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
-    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
-    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
-    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
-    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
-    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
-    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
-    PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1,
-    OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1,
-    TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
+    EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15,
+    PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1,
+    PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3,
+    PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5,
+    PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
+    PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9,
+    PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10,
+    PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11,
+    PI12, PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1,
+    OPAMP1, OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG,
+    TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        ADC3 = 47,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 87,
+        CAN2_RX1 = 88,
+        CAN2_SCE = 89,
+        CAN2_TX = 86,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 84,
+        I2C4_EV = 83,
+        LCD = 78,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        QUADSPI = 71,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SWPMI1 = 76,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(ADC3);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LCD);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SWPMI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn ADC3();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LCD();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn QUADSPI();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SWPMI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: ADC3 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: QUADSPI },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: SWPMI1 },
+        Vector { _handler: TSC },
+        Vector { _handler: LCD },
+        Vector { _handler: AES },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: DCMI },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: DMA2D },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5ae.rs b/embassy-stm32/src/chip/stm32l4p5ae.rs
index 6d2a25917..66034e537 100644
--- a/embassy-stm32/src/chip/stm32l4p5ae.rs
+++ b/embassy-stm32/src/chip/stm32l4p5ae.rs
@@ -1,22 +1,457 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2,
-    OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
-    USART1, USART2, USART3, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1,
+    SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
+    UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5ag.rs b/embassy-stm32/src/chip/stm32l4p5ag.rs
index 6d2a25917..66034e537 100644
--- a/embassy-stm32/src/chip/stm32l4p5ag.rs
+++ b/embassy-stm32/src/chip/stm32l4p5ag.rs
@@ -1,22 +1,457 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2,
-    OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
-    USART1, USART2, USART3, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1,
+    SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
+    UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5ce.rs b/embassy-stm32/src/chip/stm32l4p5ce.rs
index f0ddb6b8d..e3622c0ec 100644
--- a/embassy-stm32/src/chip/stm32l4p5ce.rs
+++ b/embassy-stm32/src/chip/stm32l4p5ce.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DMA2D, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DMA2D, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -15,8 +15,443 @@ peripherals!(
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5cg.rs b/embassy-stm32/src/chip/stm32l4p5cg.rs
index f0ddb6b8d..e3622c0ec 100644
--- a/embassy-stm32/src/chip/stm32l4p5cg.rs
+++ b/embassy-stm32/src/chip/stm32l4p5cg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DMA2D, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DMA2D, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -15,8 +15,443 @@ peripherals!(
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5qe.rs b/embassy-stm32/src/chip/stm32l4p5qe.rs
index 6d2a25917..66034e537 100644
--- a/embassy-stm32/src/chip/stm32l4p5qe.rs
+++ b/embassy-stm32/src/chip/stm32l4p5qe.rs
@@ -1,22 +1,457 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2,
-    OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
-    USART1, USART2, USART3, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1,
+    SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
+    UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5qg.rs b/embassy-stm32/src/chip/stm32l4p5qg.rs
index 6d2a25917..66034e537 100644
--- a/embassy-stm32/src/chip/stm32l4p5qg.rs
+++ b/embassy-stm32/src/chip/stm32l4p5qg.rs
@@ -1,22 +1,457 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2,
-    OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
-    USART1, USART2, USART3, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1,
+    SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
+    UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5re.rs b/embassy-stm32/src/chip/stm32l4p5re.rs
index 2c9823ee8..c60e21456 100644
--- a/embassy-stm32/src/chip/stm32l4p5re.rs
+++ b/embassy-stm32/src/chip/stm32l4p5re.rs
@@ -1,22 +1,457 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2,
-    OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4,
-    USART1, USART2, USART3, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1,
+    SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
+    UART4, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5rg.rs b/embassy-stm32/src/chip/stm32l4p5rg.rs
index 2c9823ee8..c60e21456 100644
--- a/embassy-stm32/src/chip/stm32l4p5rg.rs
+++ b/embassy-stm32/src/chip/stm32l4p5rg.rs
@@ -1,22 +1,457 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2,
-    OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4,
-    USART1, USART2, USART3, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1,
+    SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
+    UART4, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5ve.rs b/embassy-stm32/src/chip/stm32l4p5ve.rs
index 6d2a25917..66034e537 100644
--- a/embassy-stm32/src/chip/stm32l4p5ve.rs
+++ b/embassy-stm32/src/chip/stm32l4p5ve.rs
@@ -1,22 +1,457 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2,
-    OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
-    USART1, USART2, USART3, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1,
+    SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
+    UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5vg.rs b/embassy-stm32/src/chip/stm32l4p5vg.rs
index 6d2a25917..66034e537 100644
--- a/embassy-stm32/src/chip/stm32l4p5vg.rs
+++ b/embassy-stm32/src/chip/stm32l4p5vg.rs
@@ -1,22 +1,457 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2,
-    OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
-    USART1, USART2, USART3, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1,
+    SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
+    UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5ze.rs b/embassy-stm32/src/chip/stm32l4p5ze.rs
index 6d2a25917..66034e537 100644
--- a/embassy-stm32/src/chip/stm32l4p5ze.rs
+++ b/embassy-stm32/src/chip/stm32l4p5ze.rs
@@ -1,22 +1,457 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2,
-    OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
-    USART1, USART2, USART3, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1,
+    SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
+    UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4p5zg.rs b/embassy-stm32/src/chip/stm32l4p5zg.rs
index 6d2a25917..66034e537 100644
--- a/embassy-stm32/src/chip/stm32l4p5zg.rs
+++ b/embassy-stm32/src/chip/stm32l4p5zg.rs
@@ -1,22 +1,457 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2,
-    OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3,
-    SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
-    USART1, USART2, USART3, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1,
+    SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
+    UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4q5ag.rs b/embassy-stm32/src/chip/stm32l4q5ag.rs
index 295c68f1c..64643dc4e 100644
--- a/embassy-stm32/src/chip/stm32l4q5ag.rs
+++ b/embassy-stm32/src/chip/stm32l4q5ag.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,449 @@ peripherals!(
     SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
     UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PKA = 86,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PKA);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PKA();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _handler: PKA },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4q5cg.rs b/embassy-stm32/src/chip/stm32l4q5cg.rs
index 1ae248437..75adefddd 100644
--- a/embassy-stm32/src/chip/stm32l4q5cg.rs
+++ b/embassy-stm32/src/chip/stm32l4q5cg.rs
@@ -1,22 +1,463 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2,
-    OCTOSPIM, OPAMP1, OPAMP2, PKA, RCC, RNG, RTC, SAI1, SAI2, SDMMC2, SPI1, SPI2, SPI3, SYSCFG,
-    TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, USART1,
-    USART2, USART3, USB_OTG_FS, WWDG
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, RCC, RNG, RTC, SAI1, SAI2, SDMMC2, SPI1, SPI2, SPI3,
+    SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4,
+    USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PKA = 86,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PKA);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PKA();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _handler: PKA },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4q5qg.rs b/embassy-stm32/src/chip/stm32l4q5qg.rs
index 295c68f1c..64643dc4e 100644
--- a/embassy-stm32/src/chip/stm32l4q5qg.rs
+++ b/embassy-stm32/src/chip/stm32l4q5qg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,449 @@ peripherals!(
     SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
     UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PKA = 86,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PKA);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PKA();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _handler: PKA },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4q5rg.rs b/embassy-stm32/src/chip/stm32l4q5rg.rs
index 716f8233b..bbf0c47db 100644
--- a/embassy-stm32/src/chip/stm32l4q5rg.rs
+++ b/embassy-stm32/src/chip/stm32l4q5rg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,449 @@ peripherals!(
     SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
     UART4, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PKA = 86,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PKA);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PKA();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _handler: PKA },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4q5vg.rs b/embassy-stm32/src/chip/stm32l4q5vg.rs
index 295c68f1c..64643dc4e 100644
--- a/embassy-stm32/src/chip/stm32l4q5vg.rs
+++ b/embassy-stm32/src/chip/stm32l4q5vg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,449 @@ peripherals!(
     SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
     UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PKA = 86,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PKA);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PKA();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _handler: PKA },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4q5zg.rs b/embassy-stm32/src/chip/stm32l4q5zg.rs
index 295c68f1c..64643dc4e 100644
--- a/embassy-stm32/src/chip/stm32l4q5zg.rs
+++ b/embassy-stm32/src/chip/stm32l4q5zg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,449 @@ peripherals!(
     SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC,
     UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1_2 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI_PSSI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PKA = 86,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SDMMC2 = 47,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1_2);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI_PSSI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PKA);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SDMMC2);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1_2();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI_PSSI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PKA();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SDMMC2();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1_2 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _handler: SDMMC2 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector {
+            _handler: DCMI_PSSI,
+        },
+        Vector { _handler: PKA },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r5ag.rs b/embassy-stm32/src/chip/stm32l4r5ag.rs
index d8b9445b9..9c98d1f88 100644
--- a/embassy-stm32/src/chip/stm32l4r5ag.rs
+++ b/embassy-stm32/src/chip/stm32l4r5ag.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -15,8 +15,442 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r5ai.rs b/embassy-stm32/src/chip/stm32l4r5ai.rs
index d8b9445b9..9c98d1f88 100644
--- a/embassy-stm32/src/chip/stm32l4r5ai.rs
+++ b/embassy-stm32/src/chip/stm32l4r5ai.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -15,8 +15,442 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r5qg.rs b/embassy-stm32/src/chip/stm32l4r5qg.rs
index d8b9445b9..9c98d1f88 100644
--- a/embassy-stm32/src/chip/stm32l4r5qg.rs
+++ b/embassy-stm32/src/chip/stm32l4r5qg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -15,8 +15,442 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r5qi.rs b/embassy-stm32/src/chip/stm32l4r5qi.rs
index d8b9445b9..9c98d1f88 100644
--- a/embassy-stm32/src/chip/stm32l4r5qi.rs
+++ b/embassy-stm32/src/chip/stm32l4r5qi.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -15,8 +15,442 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r5vg.rs b/embassy-stm32/src/chip/stm32l4r5vg.rs
index d8b9445b9..9c98d1f88 100644
--- a/embassy-stm32/src/chip/stm32l4r5vg.rs
+++ b/embassy-stm32/src/chip/stm32l4r5vg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -15,8 +15,442 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r5vi.rs b/embassy-stm32/src/chip/stm32l4r5vi.rs
index d8b9445b9..9c98d1f88 100644
--- a/embassy-stm32/src/chip/stm32l4r5vi.rs
+++ b/embassy-stm32/src/chip/stm32l4r5vi.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -15,8 +15,442 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r5zg.rs b/embassy-stm32/src/chip/stm32l4r5zg.rs
index d8b9445b9..9c98d1f88 100644
--- a/embassy-stm32/src/chip/stm32l4r5zg.rs
+++ b/embassy-stm32/src/chip/stm32l4r5zg.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -15,8 +15,442 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r5zi.rs b/embassy-stm32/src/chip/stm32l4r5zi.rs
index d8b9445b9..9c98d1f88 100644
--- a/embassy-stm32/src/chip/stm32l4r5zi.rs
+++ b/embassy-stm32/src/chip/stm32l4r5zi.rs
@@ -1,10 +1,10 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4,
-    PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6,
-    PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8,
-    PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3,
+    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
+    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
     PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
     PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
     PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
@@ -15,8 +15,442 @@ peripherals!(
     TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2,
     USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r7ai.rs b/embassy-stm32/src/chip/stm32l4r7ai.rs
index d0f3be660..d3d635c43 100644
--- a/embassy-stm32/src/chip/stm32l4r7ai.rs
+++ b/embassy-stm32/src/chip/stm32l4r7ai.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r7vi.rs b/embassy-stm32/src/chip/stm32l4r7vi.rs
index d0f3be660..d3d635c43 100644
--- a/embassy-stm32/src/chip/stm32l4r7vi.rs
+++ b/embassy-stm32/src/chip/stm32l4r7vi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r7zi.rs b/embassy-stm32/src/chip/stm32l4r7zi.rs
index d0f3be660..d3d635c43 100644
--- a/embassy-stm32/src/chip/stm32l4r7zi.rs
+++ b/embassy-stm32/src/chip/stm32l4r7zi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,451 @@ peripherals!(
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r9ag.rs b/embassy-stm32/src/chip/stm32l4r9ag.rs
index d0f3be660..9d994d7a1 100644
--- a/embassy-stm32/src/chip/stm32l4r9ag.rs
+++ b/embassy-stm32/src/chip/stm32l4r9ag.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,454 @@ peripherals!(
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        DSI = 78,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(DSI);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn DSI();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _handler: DSI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r9ai.rs b/embassy-stm32/src/chip/stm32l4r9ai.rs
index d0f3be660..9d994d7a1 100644
--- a/embassy-stm32/src/chip/stm32l4r9ai.rs
+++ b/embassy-stm32/src/chip/stm32l4r9ai.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,454 @@ peripherals!(
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        DSI = 78,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(DSI);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn DSI();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _handler: DSI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r9vg.rs b/embassy-stm32/src/chip/stm32l4r9vg.rs
index d0f3be660..9d994d7a1 100644
--- a/embassy-stm32/src/chip/stm32l4r9vg.rs
+++ b/embassy-stm32/src/chip/stm32l4r9vg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,454 @@ peripherals!(
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        DSI = 78,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(DSI);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn DSI();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _handler: DSI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r9vi.rs b/embassy-stm32/src/chip/stm32l4r9vi.rs
index d0f3be660..9d994d7a1 100644
--- a/embassy-stm32/src/chip/stm32l4r9vi.rs
+++ b/embassy-stm32/src/chip/stm32l4r9vi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,454 @@ peripherals!(
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        DSI = 78,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(DSI);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn DSI();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _handler: DSI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r9zg.rs b/embassy-stm32/src/chip/stm32l4r9zg.rs
index d0f3be660..9d994d7a1 100644
--- a/embassy-stm32/src/chip/stm32l4r9zg.rs
+++ b/embassy-stm32/src/chip/stm32l4r9zg.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,454 @@ peripherals!(
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        DSI = 78,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(DSI);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn DSI();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _handler: DSI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4r9zi.rs b/embassy-stm32/src/chip/stm32l4r9zi.rs
index d0f3be660..9d994d7a1 100644
--- a/embassy-stm32/src/chip/stm32l4r9zi.rs
+++ b/embassy-stm32/src/chip/stm32l4r9zi.rs
@@ -1,11 +1,11 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2,
-    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
-    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
-    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
-    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1,
+    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
+    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
+    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
     PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
     PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
     PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
@@ -15,8 +15,454 @@ peripherals!(
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        CRS = 82,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        DSI = 78,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(CRS);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(DSI);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn CRS();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn DSI();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _handler: DSI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4s5ai.rs b/embassy-stm32/src/chip/stm32l4s5ai.rs
index 88d4b7bc6..cac7ba52a 100644
--- a/embassy-stm32/src/chip/stm32l4s5ai.rs
+++ b/embassy-stm32/src/chip/stm32l4s5ai.rs
@@ -1,22 +1,459 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2,
     OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1,
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4s5qi.rs b/embassy-stm32/src/chip/stm32l4s5qi.rs
index 88d4b7bc6..cac7ba52a 100644
--- a/embassy-stm32/src/chip/stm32l4s5qi.rs
+++ b/embassy-stm32/src/chip/stm32l4s5qi.rs
@@ -1,22 +1,459 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2,
     OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1,
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4s5vi.rs b/embassy-stm32/src/chip/stm32l4s5vi.rs
index 88d4b7bc6..cac7ba52a 100644
--- a/embassy-stm32/src/chip/stm32l4s5vi.rs
+++ b/embassy-stm32/src/chip/stm32l4s5vi.rs
@@ -1,22 +1,459 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2,
     OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1,
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4s5zi.rs b/embassy-stm32/src/chip/stm32l4s5zi.rs
index 88d4b7bc6..cac7ba52a 100644
--- a/embassy-stm32/src/chip/stm32l4s5zi.rs
+++ b/embassy-stm32/src/chip/stm32l4s5zi.rs
@@ -1,22 +1,459 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3,
-    PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5,
-    PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
-    PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9,
-    PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10,
-    PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11,
-    PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12,
-    PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13,
-    PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14,
-    PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2,
+    PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4,
+    PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6,
+    PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8,
+    PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
+    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
+    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
+    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
+    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
+    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2,
     OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1,
     TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1,
     USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4s7ai.rs b/embassy-stm32/src/chip/stm32l4s7ai.rs
index bae375145..5cef4a852 100644
--- a/embassy-stm32/src/chip/stm32l4s7ai.rs
+++ b/embassy-stm32/src/chip/stm32l4s7ai.rs
@@ -1,22 +1,468 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
     OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3,
     SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
     USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4s7vi.rs b/embassy-stm32/src/chip/stm32l4s7vi.rs
index bae375145..5cef4a852 100644
--- a/embassy-stm32/src/chip/stm32l4s7vi.rs
+++ b/embassy-stm32/src/chip/stm32l4s7vi.rs
@@ -1,22 +1,468 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
     OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3,
     SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
     USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4s7zi.rs b/embassy-stm32/src/chip/stm32l4s7zi.rs
index bae375145..5cef4a852 100644
--- a/embassy-stm32/src/chip/stm32l4s7zi.rs
+++ b/embassy-stm32/src/chip/stm32l4s7zi.rs
@@ -1,22 +1,468 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
     OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3,
     SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
     USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4s9ai.rs b/embassy-stm32/src/chip/stm32l4s9ai.rs
index bae375145..a79938e3e 100644
--- a/embassy-stm32/src/chip/stm32l4s9ai.rs
+++ b/embassy-stm32/src/chip/stm32l4s9ai.rs
@@ -1,22 +1,471 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
     OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3,
     SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
     USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        DSI = 78,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(DSI);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn DSI();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _handler: DSI },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4s9vi.rs b/embassy-stm32/src/chip/stm32l4s9vi.rs
index bae375145..a79938e3e 100644
--- a/embassy-stm32/src/chip/stm32l4s9vi.rs
+++ b/embassy-stm32/src/chip/stm32l4s9vi.rs
@@ -1,22 +1,471 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
     OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3,
     SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
     USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        DSI = 78,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(DSI);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn DSI();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _handler: DSI },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);
diff --git a/embassy-stm32/src/chip/stm32l4s9zi.rs b/embassy-stm32/src/chip/stm32l4s9zi.rs
index bae375145..a79938e3e 100644
--- a/embassy-stm32/src/chip/stm32l4s9zi.rs
+++ b/embassy-stm32/src/chip/stm32l4s9zi.rs
@@ -1,22 +1,471 @@
 use embassy_extras::peripherals;
 peripherals!(
     EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
-    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1,
-    PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3,
-    PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5,
-    PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
-    PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9,
-    PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10,
-    PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11,
-    PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12,
-    PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13,
-    PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
+    EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0,
+    PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2,
+    PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4,
+    PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6,
+    PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,
+    PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1,
     OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3,
     SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5,
     USART1, USART2, USART3, USB_OTG_FS, WWDG
 );
+pub const SYSCFG_BASE: usize = 0x40010000;
+pub const EXTI_BASE: usize = 0x40010400;
 pub const GPIO_BASE: usize = 0x48000000;
 pub const GPIO_STRIDE: usize = 0x400;
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    enum InterruptEnum {
+        ADC1 = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        COMP = 64,
+        DCMI = 85,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM1_FLT2 = 63,
+        DFSDM1_FLT3 = 42,
+        DMA1_Channel1 = 11,
+        DMA1_Channel2 = 12,
+        DMA1_Channel3 = 13,
+        DMA1_Channel4 = 14,
+        DMA1_Channel5 = 15,
+        DMA1_Channel6 = 16,
+        DMA1_Channel7 = 17,
+        DMA2D = 90,
+        DMA2_Channel1 = 56,
+        DMA2_Channel2 = 57,
+        DMA2_Channel3 = 58,
+        DMA2_Channel4 = 59,
+        DMA2_Channel5 = 60,
+        DMA2_Channel6 = 68,
+        DMA2_Channel7 = 69,
+        DMAMUX1_OVR = 94,
+        DSI = 78,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        GFXMMU = 93,
+        HASH_CRS = 82,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        I2C4_ER = 83,
+        I2C4_EV = 84,
+        LPTIM1 = 65,
+        LPTIM2 = 66,
+        LPUART1 = 70,
+        LTDC = 91,
+        LTDC_ER = 92,
+        OCTOSPI1 = 71,
+        OCTOSPI2 = 76,
+        OTG_FS = 67,
+        PVD_PVM = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 74,
+        SAI2 = 75,
+        SDMMC1 = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM15 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM17 = 26,
+        TIM1_UP_TIM16 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM = 45,
+        TIM8_UP = 44,
+        TSC = 77,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC1);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(COMP);
+    declare!(DCMI);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM1_FLT2);
+    declare!(DFSDM1_FLT3);
+    declare!(DMA1_Channel1);
+    declare!(DMA1_Channel2);
+    declare!(DMA1_Channel3);
+    declare!(DMA1_Channel4);
+    declare!(DMA1_Channel5);
+    declare!(DMA1_Channel6);
+    declare!(DMA1_Channel7);
+    declare!(DMA2D);
+    declare!(DMA2_Channel1);
+    declare!(DMA2_Channel2);
+    declare!(DMA2_Channel3);
+    declare!(DMA2_Channel4);
+    declare!(DMA2_Channel5);
+    declare!(DMA2_Channel6);
+    declare!(DMA2_Channel7);
+    declare!(DMAMUX1_OVR);
+    declare!(DSI);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(GFXMMU);
+    declare!(HASH_CRS);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(I2C4_ER);
+    declare!(I2C4_EV);
+    declare!(LPTIM1);
+    declare!(LPTIM2);
+    declare!(LPUART1);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OCTOSPI1);
+    declare!(OCTOSPI2);
+    declare!(OTG_FS);
+    declare!(PVD_PVM);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SAI2);
+    declare!(SDMMC1);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM15);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM17);
+    declare!(TIM1_UP_TIM16);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM);
+    declare!(TIM8_UP);
+    declare!(TSC);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC1();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn COMP();
+        fn DCMI();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM1_FLT2();
+        fn DFSDM1_FLT3();
+        fn DMA1_Channel1();
+        fn DMA1_Channel2();
+        fn DMA1_Channel3();
+        fn DMA1_Channel4();
+        fn DMA1_Channel5();
+        fn DMA1_Channel6();
+        fn DMA1_Channel7();
+        fn DMA2D();
+        fn DMA2_Channel1();
+        fn DMA2_Channel2();
+        fn DMA2_Channel3();
+        fn DMA2_Channel4();
+        fn DMA2_Channel5();
+        fn DMA2_Channel6();
+        fn DMA2_Channel7();
+        fn DMAMUX1_OVR();
+        fn DSI();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn GFXMMU();
+        fn HASH_CRS();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn I2C4_ER();
+        fn I2C4_EV();
+        fn LPTIM1();
+        fn LPTIM2();
+        fn LPUART1();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OCTOSPI1();
+        fn OCTOSPI2();
+        fn OTG_FS();
+        fn PVD_PVM();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SAI2();
+        fn SDMMC1();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM15();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM17();
+        fn TIM1_UP_TIM16();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM();
+        fn TIM8_UP();
+        fn TSC();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 95] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD_PVM },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Channel1,
+        },
+        Vector {
+            _handler: DMA1_Channel2,
+        },
+        Vector {
+            _handler: DMA1_Channel3,
+        },
+        Vector {
+            _handler: DMA1_Channel4,
+        },
+        Vector {
+            _handler: DMA1_Channel5,
+        },
+        Vector {
+            _handler: DMA1_Channel6,
+        },
+        Vector {
+            _handler: DMA1_Channel7,
+        },
+        Vector { _handler: ADC1 },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM15,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM16,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM17,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: DFSDM1_FLT3,
+        },
+        Vector { _handler: TIM8_BRK },
+        Vector { _handler: TIM8_UP },
+        Vector {
+            _handler: TIM8_TRG_COM,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector { _reserved: 0 },
+        Vector { _handler: FMC },
+        Vector { _handler: SDMMC1 },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Channel1,
+        },
+        Vector {
+            _handler: DMA2_Channel2,
+        },
+        Vector {
+            _handler: DMA2_Channel3,
+        },
+        Vector {
+            _handler: DMA2_Channel4,
+        },
+        Vector {
+            _handler: DMA2_Channel5,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector {
+            _handler: DFSDM1_FLT2,
+        },
+        Vector { _handler: COMP },
+        Vector { _handler: LPTIM1 },
+        Vector { _handler: LPTIM2 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Channel6,
+        },
+        Vector {
+            _handler: DMA2_Channel7,
+        },
+        Vector { _handler: LPUART1 },
+        Vector { _handler: OCTOSPI1 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: SAI1 },
+        Vector { _handler: SAI2 },
+        Vector { _handler: OCTOSPI2 },
+        Vector { _handler: TSC },
+        Vector { _handler: DSI },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: HASH_CRS },
+        Vector { _handler: I2C4_ER },
+        Vector { _handler: I2C4_EV },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: GFXMMU },
+        Vector {
+            _handler: DMAMUX1_OVR,
+        },
+    ];
+}
 impl_gpio_pin!(PA0, 0, 0, EXTI0);
 impl_gpio_pin!(PA1, 0, 1, EXTI1);
 impl_gpio_pin!(PA2, 0, 2, EXTI2);