Add support for STM32G0
This commit is contained in:
Ben Gamari
Dario Nieuwenhuis
parent
174c51f097
commit
e2f71ffbbd
7 changed files with 354 additions and 12 deletions
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@ -281,6 +281,110 @@ stm32f479vg = [ "stm32-metapac/stm32f479vg",]
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stm32f479vi = [ "stm32-metapac/stm32f479vi",]
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stm32f479zg = [ "stm32-metapac/stm32f479zg",]
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stm32f479zi = [ "stm32-metapac/stm32f479zi",]
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stm32g030c6 = [ "stm32-metapac/stm32g030c6",]
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stm32g030c8 = [ "stm32-metapac/stm32g030c8",]
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stm32g030f6 = [ "stm32-metapac/stm32g030f6",]
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stm32g030j6 = [ "stm32-metapac/stm32g030j6",]
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stm32g030k6 = [ "stm32-metapac/stm32g030k6",]
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stm32g030k8 = [ "stm32-metapac/stm32g030k8",]
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stm32g031c4 = [ "stm32-metapac/stm32g031c4",]
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stm32g031c6 = [ "stm32-metapac/stm32g031c6",]
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stm32g031c8 = [ "stm32-metapac/stm32g031c8",]
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stm32g031f4 = [ "stm32-metapac/stm32g031f4",]
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stm32g031f6 = [ "stm32-metapac/stm32g031f6",]
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stm32g031f8 = [ "stm32-metapac/stm32g031f8",]
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stm32g031g4 = [ "stm32-metapac/stm32g031g4",]
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stm32g031g6 = [ "stm32-metapac/stm32g031g6",]
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stm32g031g8 = [ "stm32-metapac/stm32g031g8",]
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stm32g031j4 = [ "stm32-metapac/stm32g031j4",]
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stm32g031j6 = [ "stm32-metapac/stm32g031j6",]
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stm32g031k4 = [ "stm32-metapac/stm32g031k4",]
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stm32g031k6 = [ "stm32-metapac/stm32g031k6",]
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stm32g031k8 = [ "stm32-metapac/stm32g031k8",]
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stm32g031y8 = [ "stm32-metapac/stm32g031y8",]
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stm32g041c6 = [ "stm32-metapac/stm32g041c6",]
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stm32g041c8 = [ "stm32-metapac/stm32g041c8",]
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stm32g041f6 = [ "stm32-metapac/stm32g041f6",]
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stm32g041f8 = [ "stm32-metapac/stm32g041f8",]
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stm32g041g6 = [ "stm32-metapac/stm32g041g6",]
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stm32g041g8 = [ "stm32-metapac/stm32g041g8",]
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stm32g041j6 = [ "stm32-metapac/stm32g041j6",]
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stm32g041k6 = [ "stm32-metapac/stm32g041k6",]
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stm32g041k8 = [ "stm32-metapac/stm32g041k8",]
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stm32g041y8 = [ "stm32-metapac/stm32g041y8",]
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stm32g050c6 = [ "stm32-metapac/stm32g050c6",]
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stm32g050c8 = [ "stm32-metapac/stm32g050c8",]
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stm32g050f6 = [ "stm32-metapac/stm32g050f6",]
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stm32g050k6 = [ "stm32-metapac/stm32g050k6",]
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stm32g050k8 = [ "stm32-metapac/stm32g050k8",]
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stm32g051c6 = [ "stm32-metapac/stm32g051c6",]
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stm32g051c8 = [ "stm32-metapac/stm32g051c8",]
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stm32g051f6 = [ "stm32-metapac/stm32g051f6",]
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stm32g051f8 = [ "stm32-metapac/stm32g051f8",]
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stm32g051g6 = [ "stm32-metapac/stm32g051g6",]
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stm32g051g8 = [ "stm32-metapac/stm32g051g8",]
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stm32g051k6 = [ "stm32-metapac/stm32g051k6",]
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stm32g051k8 = [ "stm32-metapac/stm32g051k8",]
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stm32g061c6 = [ "stm32-metapac/stm32g061c6",]
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stm32g061c8 = [ "stm32-metapac/stm32g061c8",]
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stm32g061f6 = [ "stm32-metapac/stm32g061f6",]
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stm32g061f8 = [ "stm32-metapac/stm32g061f8",]
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stm32g061g6 = [ "stm32-metapac/stm32g061g6",]
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stm32g061g8 = [ "stm32-metapac/stm32g061g8",]
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stm32g061k6 = [ "stm32-metapac/stm32g061k6",]
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stm32g061k8 = [ "stm32-metapac/stm32g061k8",]
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stm32g070cb = [ "stm32-metapac/stm32g070cb",]
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stm32g070kb = [ "stm32-metapac/stm32g070kb",]
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stm32g070rb = [ "stm32-metapac/stm32g070rb",]
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stm32g071c6 = [ "stm32-metapac/stm32g071c6",]
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stm32g071c8 = [ "stm32-metapac/stm32g071c8",]
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stm32g071cb = [ "stm32-metapac/stm32g071cb",]
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stm32g071eb = [ "stm32-metapac/stm32g071eb",]
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stm32g071g6 = [ "stm32-metapac/stm32g071g6",]
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stm32g071g8 = [ "stm32-metapac/stm32g071g8",]
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stm32g071gb = [ "stm32-metapac/stm32g071gb",]
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stm32g071k6 = [ "stm32-metapac/stm32g071k6",]
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stm32g071k8 = [ "stm32-metapac/stm32g071k8",]
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stm32g071kb = [ "stm32-metapac/stm32g071kb",]
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stm32g071r6 = [ "stm32-metapac/stm32g071r6",]
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stm32g071r8 = [ "stm32-metapac/stm32g071r8",]
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stm32g071rb = [ "stm32-metapac/stm32g071rb",]
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stm32g081cb = [ "stm32-metapac/stm32g081cb",]
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stm32g081eb = [ "stm32-metapac/stm32g081eb",]
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stm32g081gb = [ "stm32-metapac/stm32g081gb",]
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stm32g081kb = [ "stm32-metapac/stm32g081kb",]
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stm32g081rb = [ "stm32-metapac/stm32g081rb",]
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stm32g0b0ce = [ "stm32-metapac/stm32g0b0ce",]
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stm32g0b0ke = [ "stm32-metapac/stm32g0b0ke",]
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stm32g0b0re = [ "stm32-metapac/stm32g0b0re",]
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stm32g0b0ve = [ "stm32-metapac/stm32g0b0ve",]
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stm32g0b1cb = [ "stm32-metapac/stm32g0b1cb",]
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stm32g0b1cc = [ "stm32-metapac/stm32g0b1cc",]
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stm32g0b1ce = [ "stm32-metapac/stm32g0b1ce",]
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stm32g0b1kb = [ "stm32-metapac/stm32g0b1kb",]
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stm32g0b1kc = [ "stm32-metapac/stm32g0b1kc",]
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stm32g0b1ke = [ "stm32-metapac/stm32g0b1ke",]
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stm32g0b1mb = [ "stm32-metapac/stm32g0b1mb",]
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stm32g0b1mc = [ "stm32-metapac/stm32g0b1mc",]
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stm32g0b1me = [ "stm32-metapac/stm32g0b1me",]
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stm32g0b1ne = [ "stm32-metapac/stm32g0b1ne",]
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stm32g0b1rb = [ "stm32-metapac/stm32g0b1rb",]
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stm32g0b1rc = [ "stm32-metapac/stm32g0b1rc",]
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stm32g0b1re = [ "stm32-metapac/stm32g0b1re",]
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stm32g0b1vb = [ "stm32-metapac/stm32g0b1vb",]
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stm32g0b1vc = [ "stm32-metapac/stm32g0b1vc",]
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stm32g0b1ve = [ "stm32-metapac/stm32g0b1ve",]
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stm32g0c1cc = [ "stm32-metapac/stm32g0c1cc",]
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stm32g0c1ce = [ "stm32-metapac/stm32g0c1ce",]
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stm32g0c1kc = [ "stm32-metapac/stm32g0c1kc",]
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stm32g0c1ke = [ "stm32-metapac/stm32g0c1ke",]
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stm32g0c1mc = [ "stm32-metapac/stm32g0c1mc",]
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stm32g0c1me = [ "stm32-metapac/stm32g0c1me",]
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stm32g0c1ne = [ "stm32-metapac/stm32g0c1ne",]
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stm32g0c1rc = [ "stm32-metapac/stm32g0c1rc",]
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stm32g0c1re = [ "stm32-metapac/stm32g0c1re",]
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stm32g0c1vc = [ "stm32-metapac/stm32g0c1vc",]
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stm32g0c1ve = [ "stm32-metapac/stm32g0c1ve",]
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stm32h723ve = [ "stm32-metapac/stm32h723ve",]
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stm32h723vg = [ "stm32-metapac/stm32h723vg",]
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stm32h723ze = [ "stm32-metapac/stm32h723ze",]
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@ -15,6 +15,7 @@ os.chdir(dname)
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supported_families = [
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"STM32F0",
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'STM32F4',
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'STM32G0',
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'STM32L0',
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'STM32L4',
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'STM32H7',
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@ -188,6 +188,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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/// Calculates the system VDDA by sampling the internal VREF channel and comparing
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/// the result with the value stored at the factory. If the chip's VDDA is not stable, run
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/// this before each ADC conversion.
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#[cfg(not(rcc_g0))] // TODO is this supposed to be public?
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#[allow(unused)] // TODO is this supposed to be public?
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fn calibrate(&mut self, vref: &mut Vref) {
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let vref_cal = unsafe { crate::pac::VREFINTCAL.data().read().value() };
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@ -11,7 +11,8 @@ use embedded_hal::digital::v2::InputPin;
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use crate::gpio::{AnyPin, Input, Pin as GpioPin};
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use crate::interrupt;
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use crate::pac;
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use crate::pac::{EXTI, SYSCFG};
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use crate::pac::exti::regs::Lines;
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use crate::pac::EXTI;
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use crate::peripherals;
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const EXTI_COUNT: usize = 16;
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@ -28,19 +29,37 @@ fn cpu_regs() -> pac::exti::Exti {
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EXTI
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}
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#[cfg(not(any(exti_g0, exti_l5)))]
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fn exticr_regs() -> pac::syscfg::Syscfg {
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pac::SYSCFG
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}
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#[cfg(any(exti_g0, exti_l5))]
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fn exticr_regs() -> pac::exti::Exti {
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EXTI
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}
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pub unsafe fn on_irq() {
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let bits = EXTI.pr(0).read();
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#[cfg(not(any(exti_g0, exti_l5)))]
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let bits = EXTI.pr(0).read().0;
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#[cfg(any(exti_g0, exti_l5))]
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let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0;
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// Mask all the channels that fired.
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cpu_regs().imr(0).modify(|w| w.0 &= !bits.0);
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cpu_regs().imr(0).modify(|w| w.0 &= !bits);
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// Wake the tasks
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for pin in BitIter(bits.0) {
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for pin in BitIter(bits) {
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EXTI_WAKERS[pin as usize].wake();
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}
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// Clear pending
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EXTI.pr(0).write_value(bits);
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#[cfg(not(any(exti_g0, exti_l5)))]
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EXTI.pr(0).write_value(Lines(bits));
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#[cfg(any(exti_g0, exti_l5))]
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{
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EXTI.rpr(0).write_value(Lines(bits));
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EXTI.fpr(0).write_value(Lines(bits));
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}
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}
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struct BitIter(u32);
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@ -117,10 +136,21 @@ impl<'a> ExtiInputFuture<'a> {
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fn new(pin: u8, port: u8, rising: bool, falling: bool) -> Self {
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cortex_m::interrupt::free(|_| unsafe {
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let pin = pin as usize;
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SYSCFG.exticr(pin / 4).modify(|w| w.set_exti(pin % 4, port));
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exticr_regs()
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.exticr(pin / 4)
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.modify(|w| w.set_exti(pin % 4, port));
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EXTI.rtsr(0).modify(|w| w.set_line(pin, rising));
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EXTI.ftsr(0).modify(|w| w.set_line(pin, falling));
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EXTI.pr(0).write(|w| w.set_line(pin, true)); // clear pending bit
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// clear pending bit
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#[cfg(not(any(exti_g0, exti_l5)))]
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EXTI.pr(0).write(|w| w.set_line(pin, true));
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#[cfg(any(exti_g0, exti_l5))]
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{
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EXTI.rpr(0).write(|w| w.set_line(pin, true));
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EXTI.fpr(0).write(|w| w.set_line(pin, true));
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}
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cpu_regs().imr(0).modify(|w| w.set_line(pin, true));
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});
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190
embassy-stm32/src/rcc/g0/mod.rs
Normal file
190
embassy-stm32/src/rcc/g0/mod.rs
Normal file
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@ -0,0 +1,190 @@
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pub use super::types::*;
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use crate::pac;
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use crate::peripherals::{self, RCC};
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use crate::rcc::{get_freqs, set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::time::U32Ext;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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/// HSI speed
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pub const HSI_FREQ: u32 = 16_000_000;
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/// LSI speed
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pub const LSI_FREQ: u32 = 32_000;
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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HSE(Hertz),
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HSI16,
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LSI,
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}
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impl Into<u8> for APBPrescaler {
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fn into(self) -> u8 {
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match self {
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APBPrescaler::NotDivided => 1,
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APBPrescaler::Div2 => 0x04,
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APBPrescaler::Div4 => 0x05,
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APBPrescaler::Div8 => 0x06,
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APBPrescaler::Div16 => 0x07,
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}
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}
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}
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impl Into<u8> for AHBPrescaler {
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fn into(self) -> u8 {
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match self {
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AHBPrescaler::NotDivided => 1,
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AHBPrescaler::Div2 => 0x08,
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AHBPrescaler::Div4 => 0x09,
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AHBPrescaler::Div8 => 0x0a,
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AHBPrescaler::Div16 => 0x0b,
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AHBPrescaler::Div64 => 0x0c,
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AHBPrescaler::Div128 => 0x0d,
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AHBPrescaler::Div256 => 0x0e,
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AHBPrescaler::Div512 => 0x0f,
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}
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}
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}
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/// Clocks configutation
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pub struct Config {
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mux: ClockSrc,
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ahb_pre: AHBPrescaler,
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apb_pre: APBPrescaler,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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mux: ClockSrc::HSI16,
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ahb_pre: AHBPrescaler::NotDivided,
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apb_pre: APBPrescaler::NotDivided,
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}
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}
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}
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impl Config {
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#[inline]
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pub fn clock_src(mut self, mux: ClockSrc) -> Self {
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self.mux = mux;
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self
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}
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#[inline]
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pub fn ahb_pre(mut self, pre: AHBPrescaler) -> Self {
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self.ahb_pre = pre;
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self
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}
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#[inline]
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pub fn apb_pre(mut self, pre: APBPrescaler) -> Self {
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self.apb_pre = pre;
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self
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}
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}
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/// RCC peripheral
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pub struct Rcc<'d> {
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_rb: peripherals::RCC,
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phantom: PhantomData<&'d mut peripherals::RCC>,
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}
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impl<'d> Rcc<'d> {
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pub fn new(rcc: impl Unborrow<Target = peripherals::RCC> + 'd) -> Self {
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unborrow!(rcc);
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Self {
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_rb: rcc,
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phantom: PhantomData,
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}
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}
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// Safety: RCC init must have been called
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pub fn clocks(&self) -> &'static Clocks {
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unsafe { get_freqs() }
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}
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}
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/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
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pub trait RccExt {
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fn freeze(self, config: Config) -> Clocks;
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}
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impl RccExt for RCC {
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#[inline]
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fn freeze(self, cfgr: Config) -> Clocks {
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let rcc = pac::RCC;
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let (sys_clk, sw) = match cfgr.mux {
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ClockSrc::HSI16 => {
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// Enable HSI16
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unsafe {
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rcc.cr().write(|w| w.set_hsion(true));
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while !rcc.cr().read().hsirdy() {}
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}
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(HSI_FREQ, 0x00)
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}
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ClockSrc::HSE(freq) => {
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// Enable HSE
|
||||
unsafe {
|
||||
rcc.cr().write(|w| w.set_hseon(true));
|
||||
while !rcc.cr().read().hserdy() {}
|
||||
}
|
||||
|
||||
(freq.0, 0x01)
|
||||
}
|
||||
ClockSrc::LSI => {
|
||||
// Enable LSI
|
||||
unsafe {
|
||||
rcc.csr().write(|w| w.set_lsion(true));
|
||||
while !rcc.csr().read().lsirdy() {}
|
||||
}
|
||||
(LSI_FREQ, 0x03)
|
||||
}
|
||||
};
|
||||
|
||||
unsafe {
|
||||
rcc.cfgr().modify(|w| {
|
||||
w.set_sw(sw.into());
|
||||
w.set_hpre(cfgr.ahb_pre.into());
|
||||
w.set_ppre(cfgr.apb_pre.into());
|
||||
});
|
||||
}
|
||||
|
||||
let ahb_freq: u32 = match cfgr.ahb_pre {
|
||||
AHBPrescaler::NotDivided => sys_clk,
|
||||
pre => {
|
||||
let pre: u8 = pre.into();
|
||||
let pre = 1 << (pre as u32 - 7);
|
||||
sys_clk / pre
|
||||
}
|
||||
};
|
||||
|
||||
let (apb_freq, apb_tim_freq) = match cfgr.apb_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
|
||||
pre => {
|
||||
let pre: u8 = pre.into();
|
||||
let pre: u8 = 1 << (pre - 3);
|
||||
let freq = ahb_freq / pre as u32;
|
||||
(freq, freq * 2)
|
||||
}
|
||||
};
|
||||
|
||||
Clocks {
|
||||
sys: sys_clk.hz(),
|
||||
ahb: ahb_freq.hz(),
|
||||
apb: apb_freq.hz(),
|
||||
apb_tim: apb_tim_freq.hz(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub unsafe fn init(config: Config) {
|
||||
let r = <peripherals::RCC as embassy::util::Steal>::steal();
|
||||
let clocks = r.freeze(config);
|
||||
set_freqs(clocks);
|
||||
}
|
||||
|
|
@ -8,15 +8,26 @@ mod types;
|
|||
#[derive(Clone, Copy)]
|
||||
pub struct Clocks {
|
||||
pub sys: Hertz,
|
||||
|
||||
#[cfg(rcc_g0)]
|
||||
pub apb: Hertz,
|
||||
#[cfg(rcc_g0)]
|
||||
pub apb_tim: Hertz,
|
||||
|
||||
#[cfg(not(rcc_g0))]
|
||||
pub apb1: Hertz,
|
||||
#[cfg(not(rcc_g0))]
|
||||
pub apb1_tim: Hertz,
|
||||
|
||||
#[cfg(not(rcc_g0))]
|
||||
pub apb2: Hertz,
|
||||
#[cfg(not(rcc_g0))]
|
||||
pub apb2_tim: Hertz,
|
||||
|
||||
#[cfg(rcc_wl5)]
|
||||
pub apb3: Hertz,
|
||||
|
||||
pub apb1_tim: Hertz,
|
||||
pub apb2_tim: Hertz,
|
||||
|
||||
#[cfg(any(rcc_l0, rcc_f0, rcc_f0x0))]
|
||||
#[cfg(any(rcc_l0, rcc_f0, rcc_f0x0, rcc_g0))]
|
||||
pub ahb: Hertz,
|
||||
|
||||
#[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb, rcc_wl5))]
|
||||
|
|
@ -77,6 +88,9 @@ cfg_if::cfg_if! {
|
|||
} else if #[cfg(any(rcc_f0, rcc_f0x0))] {
|
||||
mod f0;
|
||||
pub use f0::*;
|
||||
} else if #[cfg(any(rcc_g0))] {
|
||||
mod g0;
|
||||
pub use g0::*;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -444,7 +444,9 @@ pub fn gen(options: Options) {
|
|||
Some(clock) => clock.as_str(),
|
||||
None => {
|
||||
// No clock was specified, derive the clock name from the enable register name.
|
||||
Regex::new("([A-Z]+\\d*).*")
|
||||
// N.B. STM32G0 has only one APB bus but split ENR registers
|
||||
// (e.g. APBENR1).
|
||||
Regex::new("([A-Z]+\\d*)ENR\\d*")
|
||||
.unwrap()
|
||||
.captures(enable_reg)
|
||||
.unwrap()
|
||||
|
|
|
|||
Loading…
Reference in a new issue