rp i2c: allow blocking ops on async contexts
This commit is contained in:
Jeremy Fitzhardinge
parent
09afece93d
commit
e8bb8faa23
1 changed files with 105 additions and 105 deletions
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@ -68,106 +68,6 @@ impl<'d, T: Instance> I2c<'d, T, Blocking> {
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into_ref!(scl, sda);
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Self::new_inner(peri, scl.map_into(), sda.map_into(), config)
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}
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fn read_blocking_internal(&mut self, buffer: &mut [u8], restart: bool, send_stop: bool) -> Result<(), Error> {
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if buffer.is_empty() {
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return Err(Error::InvalidReadBufferLength);
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}
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let p = T::regs();
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let lastindex = buffer.len() - 1;
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for (i, byte) in buffer.iter_mut().enumerate() {
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let first = i == 0;
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let last = i == lastindex;
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// NOTE(unsafe) We have &mut self
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unsafe {
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// wait until there is space in the FIFO to write the next byte
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while Self::tx_fifo_full() {}
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p.ic_data_cmd().write(|w| {
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w.set_restart(restart && first);
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w.set_stop(send_stop && last);
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w.set_cmd(true);
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});
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while Self::rx_fifo_len() == 0 {
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self.read_and_clear_abort_reason()?;
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}
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*byte = p.ic_data_cmd().read().dat();
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}
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}
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Ok(())
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}
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fn write_blocking_internal(&mut self, bytes: &[u8], send_stop: bool) -> Result<(), Error> {
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if bytes.is_empty() {
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return Err(Error::InvalidWriteBufferLength);
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}
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let p = T::regs();
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for (i, byte) in bytes.iter().enumerate() {
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let last = i == bytes.len() - 1;
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// NOTE(unsafe) We have &mut self
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unsafe {
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p.ic_data_cmd().write(|w| {
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w.set_stop(send_stop && last);
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w.set_dat(*byte);
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});
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// Wait until the transmission of the address/data from the
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// internal shift register has completed. For this to function
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// correctly, the TX_EMPTY_CTRL flag in IC_CON must be set. The
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// TX_EMPTY_CTRL flag was set in i2c_init.
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while !p.ic_raw_intr_stat().read().tx_empty() {}
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let abort_reason = self.read_and_clear_abort_reason();
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if abort_reason.is_err() || (send_stop && last) {
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// If the transaction was aborted or if it completed
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// successfully wait until the STOP condition has occured.
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while !p.ic_raw_intr_stat().read().stop_det() {}
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p.ic_clr_stop_det().read().clr_stop_det();
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}
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// Note the hardware issues a STOP automatically on an abort
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// condition. Note also the hardware clears RX FIFO as well as
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// TX on abort, ecause we set hwparam
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// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT to 0.
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abort_reason?;
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}
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}
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Ok(())
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}
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// =========================
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// Blocking public API
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// =========================
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pub fn blocking_read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.read_blocking_internal(buffer, true, true)
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// Automatic Stop
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}
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pub fn blocking_write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.write_blocking_internal(bytes, true)
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}
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pub fn blocking_write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.write_blocking_internal(bytes, false)?;
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self.read_blocking_internal(buffer, true, true)
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// Automatic Stop
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}
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}
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static I2C_WAKER: AtomicWaker = AtomicWaker::new();
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@ -406,7 +306,7 @@ impl<'d, T: Instance> I2c<'d, T, Async> {
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self.read_async_internal(buffer, false, true).await
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}
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pub async fn write_async(&mut self, addr: u16, bytes : impl IntoIterator<Item = u8>) -> Result<(), Error> {
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pub async fn write_async(&mut self, addr: u16, bytes: impl IntoIterator<Item = u8>) -> Result<(), Error> {
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Self::setup(addr)?;
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self.write_async_internal(bytes, true).await
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}
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@ -581,12 +481,112 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
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}
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}
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}
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fn read_blocking_internal(&mut self, buffer: &mut [u8], restart: bool, send_stop: bool) -> Result<(), Error> {
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if buffer.is_empty() {
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return Err(Error::InvalidReadBufferLength);
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}
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let p = T::regs();
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let lastindex = buffer.len() - 1;
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for (i, byte) in buffer.iter_mut().enumerate() {
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let first = i == 0;
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let last = i == lastindex;
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// NOTE(unsafe) We have &mut self
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unsafe {
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// wait until there is space in the FIFO to write the next byte
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while Self::tx_fifo_full() {}
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p.ic_data_cmd().write(|w| {
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w.set_restart(restart && first);
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w.set_stop(send_stop && last);
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w.set_cmd(true);
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});
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while Self::rx_fifo_len() == 0 {
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self.read_and_clear_abort_reason()?;
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}
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*byte = p.ic_data_cmd().read().dat();
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}
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}
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Ok(())
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}
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fn write_blocking_internal(&mut self, bytes: &[u8], send_stop: bool) -> Result<(), Error> {
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if bytes.is_empty() {
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return Err(Error::InvalidWriteBufferLength);
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}
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let p = T::regs();
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for (i, byte) in bytes.iter().enumerate() {
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let last = i == bytes.len() - 1;
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// NOTE(unsafe) We have &mut self
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unsafe {
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p.ic_data_cmd().write(|w| {
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w.set_stop(send_stop && last);
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w.set_dat(*byte);
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});
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// Wait until the transmission of the address/data from the
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// internal shift register has completed. For this to function
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// correctly, the TX_EMPTY_CTRL flag in IC_CON must be set. The
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// TX_EMPTY_CTRL flag was set in i2c_init.
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while !p.ic_raw_intr_stat().read().tx_empty() {}
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let abort_reason = self.read_and_clear_abort_reason();
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if abort_reason.is_err() || (send_stop && last) {
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// If the transaction was aborted or if it completed
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// successfully wait until the STOP condition has occured.
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while !p.ic_raw_intr_stat().read().stop_det() {}
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p.ic_clr_stop_det().read().clr_stop_det();
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}
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// Note the hardware issues a STOP automatically on an abort
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// condition. Note also the hardware clears RX FIFO as well as
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// TX on abort, ecause we set hwparam
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// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT to 0.
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abort_reason?;
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}
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}
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Ok(())
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}
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// =========================
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// Blocking public API
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// =========================
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pub fn blocking_read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.read_blocking_internal(buffer, true, true)
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// Automatic Stop
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}
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pub fn blocking_write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.write_blocking_internal(bytes, true)
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}
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pub fn blocking_write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.write_blocking_internal(bytes, false)?;
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self.read_blocking_internal(buffer, true, true)
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// Automatic Stop
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}
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}
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mod eh02 {
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use super::*;
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impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Read for I2c<'d, T, Blocking> {
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impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, T, M> {
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type Error = Error;
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fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
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@ -594,7 +594,7 @@ mod eh02 {
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}
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}
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impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Write for I2c<'d, T, Blocking> {
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impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, T, M> {
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type Error = Error;
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fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> {
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@ -602,7 +602,7 @@ mod eh02 {
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}
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}
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impl<'d, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T, Blocking> {
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impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T, M> {
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type Error = Error;
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fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> {
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@ -635,7 +635,7 @@ mod eh1 {
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type Error = Error;
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}
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impl<'d, T: Instance> embedded_hal_1::i2c::I2c for I2c<'d, T, Blocking> {
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impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, T, M> {
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fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_read(address, buffer)
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}
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