From ec2e3de0f493cd0cc116f5f67a814ae7c457d9b1 Mon Sep 17 00:00:00 2001 From: Andres Vahter Date: Fri, 19 Jan 2024 20:28:29 +0200 Subject: [PATCH] stm32 uart: fix buffered flush for usart_v1, usart_v2 There is one caveat. For some reason with first send using usart_v1/usart_v2 TC flag appears right after first byte from buffer is written to DR. Consecutive transfers work as expected - TC flag appears when last byte is fully transferred to wire. --- embassy-stm32/src/usart/buffered.rs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs index abc766bc7..c78752883 100644 --- a/embassy-stm32/src/usart/buffered.rs +++ b/embassy-stm32/src/usart/buffered.rs @@ -68,11 +68,16 @@ impl interrupt::typelevel::Handler for Interrupt // indicates that all bytes are pushed out from the FIFO. // For other usart variants it shows that last byte from the buffer was just sent. if sr_val.tc() { + // For others it is cleared above with `clear_interrupt_flags`. + #[cfg(any(usart_v1, usart_v2))] + sr(r).modify(|w| w.set_tc(false)); + r.cr1().modify(|w| { w.set_tcie(false); }); + state.tx_done.store(true, Ordering::Release); - state.rx_waker.wake(); + state.tx_waker.wake(); } // TX