From ee47a3e802a674cd002f944b3362e2ab71e2cf5e Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Tue, 8 Jun 2021 10:41:02 +0200
Subject: [PATCH] Add workaround for STM32H7

---
 stm32-metapac/build.rs | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/stm32-metapac/build.rs b/stm32-metapac/build.rs
index 91b76b2a4..46660d9bd 100644
--- a/stm32-metapac/build.rs
+++ b/stm32-metapac/build.rs
@@ -219,7 +219,12 @@ fn main() {
                 }
                 "spi" => {
                     if let Some(clock) = &p.clock {
-                        let reg = clock.to_ascii_lowercase();
+                        // Workaround for APB1 register being split on some chip families
+                        let reg = if chip.family == "STM32H7" && clock == "APB1" {
+                            format!("{}l", clock.to_ascii_lowercase())
+                        } else {
+                            clock.to_ascii_lowercase()
+                        };
                         let field = name.to_ascii_lowercase();
                         peripheral_rcc_table.push(vec![
                             name.clone(),