From f285a545be80772d1b9dd0d98f8ec89184deb388 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= <joel@systemscape.de>
Date: Thu, 23 May 2024 23:52:18 +0200
Subject: [PATCH] Change bool to Pull
---
embassy-stm32/src/spi/mod.rs | 34 ++++++----------------------------
1 file changed, 6 insertions(+), 28 deletions(-)
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index be8cfcecf..9238e0f6f 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -54,7 +54,7 @@ pub struct Config {
///
/// There are some ICs that require a pull-up on the MISO pin for some applications.
/// If you are unsure, you probably don't need this.
- pub miso_pullup: bool,
+ pub miso_pullup: Pull,
}
impl Default for Config {
@@ -63,7 +63,7 @@ impl Default for Config {
mode: MODE_0,
bit_order: BitOrder::MsbFirst,
frequency: Hertz(1_000_000),
- miso_pullup: false,
+ miso_pullup: Pull::None,
}
}
}
@@ -280,14 +280,8 @@ impl<'d, M: PeriMode> Spi<'d, M> {
};
let miso_pullup = match &self.miso {
- None => false,
- Some(pin) => {
- if pin.pull() == Pull::Up {
- true
- } else {
- false
- }
- }
+ None => Pull::None,
+ Some(pin) => pin.pull(),
};
#[cfg(any(spi_v1, spi_f1, spi_v2))]
@@ -424,15 +418,7 @@ impl<'d> Spi<'d, Blocking> {
peri,
new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()),
new_pin!(mosi, AFType::OutputPushPull, Speed::VeryHigh),
- new_pin!(
- miso,
- AFType::Input,
- Speed::VeryHigh,
- match config.miso_pullup {
- true => Pull::Up,
- false => Pull::None,
- }
- ),
+ new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pullup),
None,
None,
config,
@@ -450,15 +436,7 @@ impl<'d> Spi<'d, Blocking> {
peri,
new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()),
None,
- new_pin!(
- miso,
- AFType::Input,
- Speed::VeryHigh,
- match config.miso_pullup {
- true => Pull::Up,
- false => Pull::None,
- }
- ),
+ new_pin!(miso, AFType::Input, Speed::VeryHigh, config.miso_pullup),
None,
None,
config,