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remove debug code, add some comments

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JuliDi 2023-10-02 09:33:10 +02:00
parent 6ea5aa347d
commit f3aa0cfe5a
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1 changed files with 4 additions and 4 deletions
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8
embassy-stm32/src/qspi/mod.rs
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@ -209,10 +209,6 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
w.set_ckmode(true); w.set_ckmode(true);
}); });
// FOR TESTING ONLY
//T::REGS.ccr().write(|w| w.set_frcm(true));
// END FOR TESTING ONLY
Self { Self {
_peri: peri, _peri: peri,
sck, sck,
@ -260,8 +256,10 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
} }
pub fn blocking_write(&mut self, buf: &[u8], transaction: TransferConfig) { pub fn blocking_write(&mut self, buf: &[u8], transaction: TransferConfig) {
// STM32H7 does not have dmaen
#[cfg(not(stm32h7))] #[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(false)); T::REGS.cr().modify(|v| v.set_dmaen(false));
self.setup_transaction(QspiMode::IndirectWrite, &transaction); self.setup_transaction(QspiMode::IndirectWrite, &transaction);
if let Some(len) = transaction.data_len { if let Some(len) = transaction.data_len {
@ -304,6 +302,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
) )
}; };
// STM32H7 does not have dmaen
#[cfg(not(stm32h7))] #[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(true)); T::REGS.cr().modify(|v| v.set_dmaen(true));
@ -331,6 +330,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
) )
}; };
// STM32H7 does not have dmaen
#[cfg(not(stm32h7))] #[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(true)); T::REGS.cr().modify(|v| v.set_dmaen(true));