stm32: add initial adc f3 impl
This commit is contained in:
xoviat
parent
e2f8bf19ea
commit
f502271940
8 changed files with 331 additions and 23 deletions
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@ -309,14 +309,17 @@ fn main() {
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// Generate RccPeripheral impls
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// TODO: maybe get this from peripheral kind? Not sure
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let refcounted_peripherals = HashSet::from(["USART"]);
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let mut refcounted_peripherals = HashSet::from(["usart"]);
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let mut refcount_statics = HashSet::new();
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if chip_name.starts_with("stm32f3") {
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refcounted_peripherals.insert("adc");
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}
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for p in METADATA.peripherals {
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// generating RccPeripheral impl for H7 ADC3 would result in bad frequency
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if !singletons.contains(&p.name.to_string())
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|| (p.name == "ADC3" && METADATA.line.starts_with("STM32H7"))
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|| (p.name.starts_with("ADC") && p.registers.as_ref().map_or(false, |r| r.version == "f3"))
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|| (p.name.starts_with("ADC") && p.registers.as_ref().map_or(false, |r| r.version == "v4"))
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{
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continue;
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@ -348,13 +351,13 @@ fn main() {
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TokenStream::new()
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};
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let ptype = (if let Some(reg) = &p.registers { reg.kind } else { "" }).to_ascii_uppercase();
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let ptype = if let Some(reg) = &p.registers { reg.kind } else { "" };
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let pname = format_ident!("{}", p.name);
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let clk = format_ident!("{}", rcc.clock.to_ascii_lowercase());
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let en_reg = format_ident!("{}", en.register.to_ascii_lowercase());
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let set_en_field = format_ident!("set_{}", en.field.to_ascii_lowercase());
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let (before_enable, before_disable) = if refcounted_peripherals.contains(ptype.as_str()) {
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let (before_enable, before_disable) = if refcounted_peripherals.contains(ptype) {
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let refcount_static =
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format_ident!("{}_{}", en.register.to_ascii_uppercase(), en.field.to_ascii_uppercase());
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126
embassy-stm32/src/adc/f3.rs
Normal file
126
embassy-stm32/src/adc/f3.rs
Normal file
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@ -0,0 +1,126 @@
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use embassy_hal_internal::into_ref;
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use embedded_hal_02::blocking::delay::DelayUs;
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use crate::adc::{Adc, AdcPin, Instance, SampleTime};
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use crate::time::Hertz;
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use crate::Peripheral;
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pub const VDDA_CALIB_MV: u32 = 3300;
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pub const ADC_MAX: u32 = (1 << 12) - 1;
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// No calibration data for F103, voltage should be 1.2v
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pub const VREF_INT: u32 = 1200;
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pub struct Vref;
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impl<T: Instance> AdcPin<T> for Vref {}
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impl<T: Instance> super::sealed::AdcPin<T> for Vref {
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fn channel(&self) -> u8 {
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18
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}
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}
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pub struct Temperature;
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impl<T: Instance> AdcPin<T> for Temperature {}
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impl<T: Instance> super::sealed::AdcPin<T> for Temperature {
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fn channel(&self) -> u8 {
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16
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}
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}
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impl<'d, T: Instance> Adc<'d, T> {
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pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
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use crate::pac::adc::vals;
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into_ref!(adc);
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T::enable();
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T::reset();
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// Enable the adc regulator
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T::regs().cr().modify(|w| w.set_advregen(vals::Advregen::INTERMEDIATE));
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T::regs().cr().modify(|w| w.set_advregen(vals::Advregen::ENABLED));
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// Wait for the regulator to stabilize
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delay.delay_us(10);
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assert!(!T::regs().cr().read().aden());
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// Begin calibration
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T::regs().cr().modify(|w| w.set_adcaldif(false));
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T::regs().cr().modify(|w| w.set_adcal(true));
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while T::regs().cr().read().adcal() {}
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// Enable the adc
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T::regs().cr().modify(|w| w.set_aden(true));
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// Wait until the adc is ready
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while !T::regs().isr().read().adrdy() {}
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Self {
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adc,
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sample_time: Default::default(),
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}
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}
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fn freq() -> Hertz {
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<T as crate::adc::sealed::Instance>::frequency()
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}
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pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
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match us * Self::freq().0 / 1_000_000 {
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0..=1 => SampleTime::Cycles1_5,
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2..=4 => SampleTime::Cycles4_5,
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5..=7 => SampleTime::Cycles7_5,
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8..=19 => SampleTime::Cycles19_5,
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20..=61 => SampleTime::Cycles61_5,
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62..=181 => SampleTime::Cycles181_5,
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_ => SampleTime::Cycles601_5,
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}
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}
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pub fn enable_vref(&self, _delay: &mut impl DelayUs<u32>) -> Vref {
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T::common_regs().ccr().modify(|w| w.set_vrefen(true));
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Vref {}
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}
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pub fn enable_temperature(&self) -> Temperature {
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T::common_regs().ccr().modify(|w| w.set_tsen(true));
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Temperature {}
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}
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pub fn set_sample_time(&mut self, sample_time: SampleTime) {
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self.sample_time = sample_time;
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}
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/// Perform a single conversion.
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fn convert(&mut self) -> u16 {
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T::regs().isr().write(|_| {});
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T::regs().cr().modify(|w| w.set_adstart(true));
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while !T::regs().isr().read().eoc() && !T::regs().isr().read().eos() {}
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T::regs().isr().write(|_| {});
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T::regs().dr().read().0 as u16
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}
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pub fn read(&mut self, pin: &mut impl AdcPin<T>) -> u16 {
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// pin.set_as_analog();
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Self::set_channel_sample_time(pin.channel(), self.sample_time);
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// Configure the channel to sample
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T::regs().sqr3().write(|w| w.set_sq(0, pin.channel()));
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self.convert()
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}
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fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
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let sample_time = sample_time.into();
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if ch <= 9 {
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T::regs().smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
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} else {
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T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
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}
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}
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}
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@ -1,23 +1,24 @@
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#![macro_use]
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#[cfg(not(any(adc_f3, adc_f3_v2)))]
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#[cfg(not(adc_f3_v2))]
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#[cfg_attr(adc_f1, path = "f1.rs")]
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#[cfg_attr(adc_f3, path = "f3.rs")]
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#[cfg_attr(adc_v1, path = "v1.rs")]
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#[cfg_attr(adc_v2, path = "v2.rs")]
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#[cfg_attr(any(adc_v3, adc_g0), path = "v3.rs")]
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#[cfg_attr(adc_v4, path = "v4.rs")]
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mod _version;
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#[cfg(not(any(adc_f1, adc_f3, adc_f3_v2)))]
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#[cfg(not(any(adc_f1, adc_f3_v2)))]
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mod resolution;
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mod sample_time;
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#[cfg(not(any(adc_f3, adc_f3_v2)))]
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#[allow(unused)]
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#[cfg(not(adc_f3_v2))]
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pub use _version::*;
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#[cfg(not(any(adc_f1, adc_f3, adc_f3_v2)))]
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pub use resolution::Resolution;
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#[cfg(not(any(adc_f3, adc_f3_v2)))]
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#[cfg(not(adc_f3_v2))]
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pub use sample_time::SampleTime;
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use crate::peripherals;
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@ -25,15 +26,17 @@ use crate::peripherals;
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pub struct Adc<'d, T: Instance> {
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#[allow(unused)]
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adc: crate::PeripheralRef<'d, T>,
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#[cfg(not(any(adc_f3, adc_f3_v2)))]
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#[cfg(not(adc_f3_v2))]
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sample_time: SampleTime,
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}
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pub(crate) mod sealed {
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pub trait Instance {
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fn regs() -> crate::pac::adc::Adc;
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#[cfg(not(any(adc_f1, adc_v1, adc_f3, adc_f3_v2)))]
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#[cfg(not(any(adc_f1, adc_v1, adc_f3_v2)))]
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fn common_regs() -> crate::pac::adccommon::AdcCommon;
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#[cfg(adc_f3)]
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fn frequency() -> crate::time::Hertz;
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}
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pub trait AdcPin<T: Instance> {
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@ -45,22 +48,22 @@ pub(crate) mod sealed {
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}
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}
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#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v4)))]
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#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v4, adc_f3)))]
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pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {}
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#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v4))]
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#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v4, adc_f3))]
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pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {}
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pub trait AdcPin<T: Instance>: sealed::AdcPin<T> {}
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pub trait InternalChannel<T>: sealed::InternalChannel<T> {}
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#[cfg(not(stm32h7))]
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#[cfg(not(any(stm32h7, adc_f3)))]
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foreach_peripheral!(
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(adc, $inst:ident) => {
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impl crate::adc::sealed::Instance for peripherals::$inst {
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fn regs() -> crate::pac::adc::Adc {
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crate::pac::$inst
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}
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#[cfg(not(any(adc_f1, adc_v1, adc_f3, adc_f3_v2)))]
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#[cfg(not(any(adc_f1, adc_v1, adc_f3_v2)))]
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fn common_regs() -> crate::pac::adccommon::AdcCommon {
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foreach_peripheral!{
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(adccommon, $common_inst:ident) => {
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@ -74,7 +77,7 @@ foreach_peripheral!(
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};
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);
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#[cfg(stm32h7)]
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#[cfg(any(stm32h7, adc_f3))]
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foreach_peripheral!(
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(adc, ADC3) => {
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impl crate::adc::sealed::Instance for peripherals::ADC3 {
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@ -89,16 +92,43 @@ foreach_peripheral!(
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};
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}
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}
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#[cfg(adc_f3)]
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fn frequency() -> crate::time::Hertz {
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unsafe { crate::rcc::get_freqs() }.adc34.unwrap()
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}
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}
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impl crate::adc::Instance for peripherals::ADC3 {}
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};
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(adc, ADC4) => {
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impl crate::adc::sealed::Instance for peripherals::ADC4 {
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fn regs() -> crate::pac::adc::Adc {
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crate::pac::ADC4
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}
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#[cfg(not(any(adc_f1, adc_v1)))]
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fn common_regs() -> crate::pac::adccommon::AdcCommon {
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foreach_peripheral!{
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(adccommon, ADC3_COMMON) => {
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return crate::pac::ADC3_COMMON
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};
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}
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}
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#[cfg(adc_f3)]
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fn frequency() -> crate::time::Hertz {
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unsafe { crate::rcc::get_freqs() }.adc34.unwrap()
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}
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}
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impl crate::adc::Instance for peripherals::ADC4 {}
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};
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(adc, $inst:ident) => {
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impl crate::adc::sealed::Instance for peripherals::$inst {
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fn regs() -> crate::pac::adc::Adc {
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crate::pac::$inst
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}
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#[cfg(all(not(adc_f1), not(adc_v1)))]
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#[cfg(not(any(adc_f1, adc_v1)))]
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fn common_regs() -> crate::pac::adccommon::AdcCommon {
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foreach_peripheral!{
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(adccommon, ADC_COMMON) => {
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@ -106,6 +136,11 @@ foreach_peripheral!(
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};
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}
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}
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#[cfg(adc_f3)]
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fn frequency() -> crate::time::Hertz {
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unsafe { crate::rcc::get_freqs() }.adc.unwrap()
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}
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}
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impl crate::adc::Instance for peripherals::$inst {}
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@ -1,4 +1,4 @@
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3))]
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#[derive(Clone, Copy, Debug, Eq, PartialEq)]
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pub enum Resolution {
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TwelveBit,
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@ -19,7 +19,7 @@ pub enum Resolution {
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impl Default for Resolution {
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fn default() -> Self {
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3))]
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{
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Self::TwelveBit
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}
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@ -40,7 +40,7 @@ impl From<Resolution> for crate::pac::adc::vals::Res {
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Resolution::TwelveBit => crate::pac::adc::vals::Res::TWELVEBIT,
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Resolution::TenBit => crate::pac::adc::vals::Res::TENBIT,
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Resolution::EightBit => crate::pac::adc::vals::Res::EIGHTBIT,
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3))]
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Resolution::SixBit => crate::pac::adc::vals::Res::SIXBIT,
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}
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}
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@ -56,7 +56,7 @@ impl Resolution {
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Resolution::TwelveBit => (1 << 12) - 1,
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Resolution::TenBit => (1 << 10) - 1,
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Resolution::EightBit => (1 << 8) - 1,
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3))]
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Resolution::SixBit => (1 << 6) - 1,
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}
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}
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@ -1,4 +1,4 @@
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#[cfg(not(any(adc_f3, adc_f3_v2)))]
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#[cfg(not(adc_f3_v2))]
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macro_rules! impl_sample_time {
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($default_doc:expr, $default:ident, ($(($doc:expr, $variant:ident, $pac_variant:ident)),*)) => {
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#[doc = concat!("ADC sample time\n\nThe default setting is ", $default_doc, " ADC clock cycles.")]
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@ -105,3 +105,19 @@ impl_sample_time!(
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("810.5", Cycles810_5, CYCLES810_5)
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)
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);
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#[cfg(adc_f3)]
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impl_sample_time!(
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"1.5",
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Cycles1_5,
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(
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("1.5", Cycles1_5, CYCLES1_5),
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("2.5", Cycles2_5, CYCLES2_5),
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("4.5", Cycles4_5, CYCLES4_5),
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("7.5", Cycles7_5, CYCLES7_5),
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("19.5", Cycles19_5, CYCLES19_5),
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("61.5", Cycles61_5, CYCLES61_5),
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("181.5", Cycles181_5, CYCLES181_5),
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("601.5", Cycles601_5, CYCLES601_5)
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)
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);
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@ -1,5 +1,5 @@
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use crate::pac::flash::vals::Latency;
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use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
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use crate::pac::rcc::vals::{Adcpres, Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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@ -10,6 +10,46 @@ pub const HSI_FREQ: Hertz = Hertz(8_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(40_000);
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#[repr(u16)]
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#[derive(Clone, Copy)]
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pub enum ADCPrescaler {
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Div1 = 1,
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Div2 = 2,
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Div4 = 4,
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Div6 = 6,
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Div8 = 8,
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Div12 = 12,
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Div16 = 16,
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Div32 = 32,
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Div64 = 64,
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Div128 = 128,
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Div256 = 256,
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}
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impl From<ADCPrescaler> for Adcpres {
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fn from(value: ADCPrescaler) -> Self {
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match value {
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ADCPrescaler::Div1 => Adcpres::DIV1,
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ADCPrescaler::Div2 => Adcpres::DIV2,
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ADCPrescaler::Div4 => Adcpres::DIV4,
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ADCPrescaler::Div6 => Adcpres::DIV6,
|
||||
ADCPrescaler::Div8 => Adcpres::DIV8,
|
||||
ADCPrescaler::Div12 => Adcpres::DIV12,
|
||||
ADCPrescaler::Div16 => Adcpres::DIV16,
|
||||
ADCPrescaler::Div32 => Adcpres::DIV32,
|
||||
ADCPrescaler::Div64 => Adcpres::DIV64,
|
||||
ADCPrescaler::Div128 => Adcpres::DIV128,
|
||||
ADCPrescaler::Div256 => Adcpres::DIV256,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy)]
|
||||
pub enum ADCClock {
|
||||
AHB(ADCPrescaler),
|
||||
PLL(ADCPrescaler),
|
||||
}
|
||||
|
||||
/// Clocks configutation
|
||||
#[non_exhaustive]
|
||||
#[derive(Default)]
|
||||
|
|
@ -36,9 +76,18 @@ pub struct Config {
|
|||
/// - The System clock frequency is either 48MHz or 72MHz
|
||||
/// - APB1 clock has a minimum frequency of 10MHz
|
||||
pub pll48: bool,
|
||||
#[cfg(rcc_f3)]
|
||||
/// ADC clock setup
|
||||
/// - For AHB, a psc of 4 or less must be used
|
||||
pub adc: Option<ADCClock>,
|
||||
#[cfg(rcc_f3)]
|
||||
/// ADC clock setup
|
||||
/// - For AHB, a psc of 4 or less must be used
|
||||
pub adc34: Option<ADCClock>,
|
||||
}
|
||||
|
||||
// Information required to setup the PLL clock
|
||||
#[derive(Clone, Copy)]
|
||||
struct PllConfig {
|
||||
pll_src: Pllsrc,
|
||||
pll_mul: Pllmul,
|
||||
|
|
@ -148,6 +197,44 @@ pub(crate) unsafe fn init(config: Config) {
|
|||
});
|
||||
}
|
||||
|
||||
#[cfg(rcc_f3)]
|
||||
let adc = config.adc.map(|adc| match adc {
|
||||
ADCClock::PLL(psc) => RCC.cfgr2().modify(|w| {
|
||||
// Make sure that we're using the PLL
|
||||
pll_config.unwrap();
|
||||
w.set_adc12pres(psc.into());
|
||||
|
||||
Hertz(sysclk / psc as u32)
|
||||
}),
|
||||
ADCClock::AHB(psc) => {
|
||||
assert!(psc as u16 <= 4);
|
||||
assert!(!(psc as u16 == 1 && hpre_bits != Hpre::DIV1));
|
||||
|
||||
// To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be
|
||||
// different from “00”.
|
||||
todo!();
|
||||
}
|
||||
});
|
||||
|
||||
#[cfg(rcc_f3)]
|
||||
let adc34 = config.adc34.map(|adc| match adc {
|
||||
ADCClock::PLL(psc) => RCC.cfgr2().modify(|w| {
|
||||
// Make sure that we're using the PLL
|
||||
pll_config.unwrap();
|
||||
w.set_adc34pres(psc.into());
|
||||
|
||||
Hertz(sysclk / psc as u32)
|
||||
}),
|
||||
ADCClock::AHB(psc) => {
|
||||
assert!(psc as u16 <= 4);
|
||||
assert!(!(psc as u16 == 1 && hpre_bits != Hpre::DIV1));
|
||||
|
||||
// To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be
|
||||
// different from “00”.
|
||||
todo!();
|
||||
}
|
||||
});
|
||||
|
||||
// Set prescalers
|
||||
// CFGR has been written before (PLL, PLL48) don't overwrite these settings
|
||||
RCC.cfgr().modify(|w| {
|
||||
|
|
@ -177,6 +264,10 @@ pub(crate) unsafe fn init(config: Config) {
|
|||
apb1_tim: Hertz(pclk1 * timer_mul1),
|
||||
apb2_tim: Hertz(pclk2 * timer_mul2),
|
||||
ahb1: Hertz(hclk),
|
||||
#[cfg(rcc_f3)]
|
||||
adc: adc,
|
||||
#[cfg(rcc_f3)]
|
||||
adc34: adc34,
|
||||
});
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -74,9 +74,12 @@ pub struct Clocks {
|
|||
#[cfg(stm32f1)]
|
||||
pub adc: Hertz,
|
||||
|
||||
#[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7ab))]
|
||||
#[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_f3))]
|
||||
pub adc: Option<Hertz>,
|
||||
|
||||
#[cfg(rcc_f3)]
|
||||
pub adc34: Option<Hertz>,
|
||||
|
||||
#[cfg(any(rcc_wb, rcc_f4, rcc_f410))]
|
||||
/// Set only if the lsi or lse is configured, indicates stop is supported
|
||||
pub rtc: Option<Hertz>,
|
||||
|
|
|
|||
34
examples/stm32f334/src/bin/adc.rs
Normal file
34
examples/stm32f334/src/bin/adc.rs
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
|
||||
use defmt::info;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::adc::Adc;
|
||||
use embassy_stm32::rcc::{ADCClock, ADCPrescaler};
|
||||
use embassy_stm32::time::Hertz;
|
||||
use embassy_stm32::Config;
|
||||
use embassy_time::{Delay, Duration, Timer};
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) -> ! {
|
||||
let mut config = Config::default();
|
||||
config.rcc.hse = Some(Hertz(8_000_000));
|
||||
config.rcc.sysclk = Some(Hertz(16_000_000));
|
||||
config.rcc.adc = Some(ADCClock::PLL(ADCPrescaler::Div1));
|
||||
|
||||
let mut p = embassy_stm32::init(config);
|
||||
|
||||
let mut adc = Adc::new(p.ADC1, &mut Delay);
|
||||
|
||||
let mut vrefint = adc.enable_vref(&mut Delay);
|
||||
|
||||
let _vref = adc.read(&mut vrefint);
|
||||
let _pin = adc.read(&mut p.PA0);
|
||||
|
||||
loop {
|
||||
info!("Hello World!");
|
||||
Timer::after(Duration::from_secs(1)).await;
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue